IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`IEEE JOURNAL! OF SC)LID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`
`961
`961
`
`A Two Chip PCM Voice CODEC with Filters
`A Two Chip PCM Voice CODEC with Filters
`
`YUSUF A. HAQUE, ROUBIK GREGORIAN, MEMBER, IEEE, RICHARD W. BLASCO,
`YUSUF A. HAQUE, ROUBIK GREGORIAN,
`MEMBER,
`IEEE, RICHARD
`W. BLASCO,
`ROGER A. MAO, MEMBER, IEEE, AND WILLIAM E. NICHOLSON, Jr., MEMBER, IEEE
`ROGER
`A. MAO, MEMBER,
`IEEE, AND WILLIAM
`E. NICHOLSON,
`Jr., MEMBER,
`IEEE
`
`Abstract-Architecture and design of a monolithic voice CODEC is
`Abstracf-Architecture
`and design of a monolithic
`voice CODEC is
`described.
`described.
`The CODEC consists of 2 chips-the transmit chip includes the com-
`The CODEC consists
`of 2 chips–the
`transmit
`chip includes
`the com-
`panding coder (nonlinear A/D) along with filtering functions, and the
`panding
`coder
`(nonlinear
`A/D)
`along with
`fiitering
`functions,
`and the
`receive chip consists of the expanding decoder (nonlinear D/A) chip
`receive
`chip
`consists
`of
`the expanding
`decoder
`(nonlinear
`D/A)
`chip
`with its smoothing filter.
`with its smoothing
`fiiter.
`Experimental results show the circuit to meet accepted requirements.
`Experimental
`results
`show the circuit
`to meet accepted
`requirements.
`
`F OR MORE THAN a decade analog-to-digital
`r digital-to-analog (D/A) conversion, i.e., the coder-decoder
`
`I.
`I. INTRODUCTION
`INTRODUCTION
`OR MORE THAN a decade analog-to-digital (A/D) and
`(A/D)
`and
`digital-to-analog
`(D/A)
`conversion,
`i.e., the coder-decoder
`(CODEC) function has been required in the telephone system
`(CODEC)
`function
`has been required in the telephone system
`for transmission of voiceband signals. This involved the use of
`for
`transmission of voiceband signals. This involved the use of
`over 24, 32, am96 channels
`a high-speed CODEC multiplexed over 24, 32, or 96 channels
`a high-speed CODEC lmultiplexed
`using pulse amplitude modulation techniques. Technological
`using pulse amplitude modulation
`techniques.
`Technological
`advances have allowed the use of time division multiplexed
`advances have allowed
`the use of
`time division multiplexed
`digital switching networks to replace older space division analog
`digital switching networks to replace older space clivision analog
`switching networks. This has created yet another market for
`switching
`networks.
`This has created yet another market
`for
`CODEC's (in addition to the channel bank application) for use
`CODEC’S (in addition to the channel bank application)
`for use
`in PBX's and local switching networks. The large volumes in-
`in PBX’S and local switching networks.
`The large volumes in-
`volved, coupled with the economics of LSI circuits, make the
`volved, coupled with the economics of LSI circuits, make the
`development of monolithic per channel CODEC's viable.
`development of monolithic
`per channel CODEC’S viable.
`The CODEC to be described uses pulse-code modulation
`The CODEC to be described uses pulse-code modulation
`(PCM) for voice digitization. PCM is widely used in commer-
`(PCM)
`for voice digitization.
`PCM is widely used in commer-
`cial telephony switching and is deeply entrenched in world
`cial
`telephony
`switching
`and is deeply entrenched
`in world
`networks for short haul transmission. In order to achieve the
`networks
`for short haul
`transmission.
`In order
`to achieve the
`required greater than 70 dB dynamic range with an 8 bit digi-
`required greater
`than ’70 dB dynamic range with an 8 bit digi-
`tal word, compression/expansion technique is performed by
`tal word,
`compression/expansion
`technique is performed
`by
`using coding laws, the two internationally recognized laws for
`using coding laws,
`the two internationally
`recognized laws for
`8 bit PCM being the segmented p255 law and the A Law [1] .
`8 bit PCM being the segmented p255 law and the A Law [1].
`The µ255 version has been implemented here and the A Law
`The v255 version has been implemented
`here and the A Law
`version is a metal mask option.
`version is a metal mask option.
`The standard sampling rate for PCM coding is 8 kHz. This
`The standard sampling rate for PCM coding is 8 kHz.
`This
`requires that the signals applied to the coder be band-limited
`requires that
`the signals applied to the coder be band-limited
`to below 4 kHz (Nyquist frequency) to prevent aliasing. In
`to below 4 kHz (Nyquist
`frequency)
`to prevent. aliasing.
`In
`the decoder direction, after the digital word is decoded and is
`the decoder direction,
`after
`the digit al word is decoded and is
`applied to the sample-and-hold, a smoothing filter is required
`applied to the sample-and-hold,
`a smoothing filter
`is required
`to remove the high-frequency components from the sample-
`to remove the high-frequency
`components
`from the sample-
`and-hold signal. These filtering functions have also been inte-
`and-hold signal. These filtering
`functions have also been inte-
`grated on the same chip with the associated data converters.
`grated on the same chip with the associated data converters.
`
`II. SELECTIC~N OF PROCESS TECHNOLOGY
`II. SELECTION OF PROCESS TECHNOLOGY
`Silicon gate CMOS technology was chosen to fabricate the
`Silicon
`gate CMOS
`technology
`was chosen
`to fabricate
`the
`CODEC. This choice was motivated by the availability of low-
`CODEC.
`This choice was motivated
`by the availability
`of
`low-
`power digital circuitry and by the superior analog capability
`anallog capability
`power
`digital
`circuitry
`and by the superior
`
`Manuscript received July 2, 1979; revised August 13, 1979.
`Manuscript
`received July 2, 1979; revised August 13, 1979.
`Y. A. Hague, R. Gregorian, R. W. Blasco, and W. E. Nicholson, Jr.,
`Y. A. Haque, R. Gregorian, R. W. Blasco, and W. E. Nicholson,
`Jr.,
`are with American Microsystems, Inc., Santa Clara, CA 95051.
`are with American Microsystems,
`Inc., Santa Clara, CA 95051.
`R. A. Mao was with American Microsystems, Inc., Santa Clara, CA
`R. A. Mao was with American Microsystems,
`Inc., Santa Clara, CA
`95051. He is now with Synertek, Inc., Santa Clara, CA.
`95051. He is now with Synertek,
`Inc., Santa Clara, CA.
`
`of CMOS compared to single channel MOS. The CODEC with
`of CMOS compared to single channel MOS. The CODEC with
`filters has a large mix of analog and digital circuitry on the
`filters has a large mix of analog and digital
`circuitry
`on the
`same chip. Thus digital feedthrough and noise can be coupled
`same chip. Thus digital
`feedthrough and noise can be coupled
`onto analog signal paths (for instance, through operational am-
`onto analog signal paths (for
`instance,
`through operational am-
`plifier power supplies). Single channel operational amplifiers
`plifier
`power supplies). Single channel operational
`amplifiers
`do not have a comparable power supply rejection from both
`do not have a comparable power supply rejection from both
`supplies compared to CMOS operational amplifiers. This allows
`supplies compared to CMOS operational amplifiers.
`This allows
`for a smaller decoupling requirement on CMOS analog cir-
`for a smaller decoupling
`requirement
`on CMOS analog cir-
`cuitry power supply lines and also allows a wider operating
`cuitry
`power supply lines and also allows a wider operating
`voltage range. In addition, CMOS has vertical n-p-n bipolar
`voltage range.
`In addition, CMOS has vertical n-p-n bipolar
`transistors which provides low output impedance devices with
`transistors which provides low output
`impedance devices with
`high current drive capability.
`high current drive capability.
`Thin oxide voltage invariant capacitors were used for the
`Thin oxide voltage invariant
`capacitors were used for
`the
`CODEC. The polysilicon-to-aluminum capacitors are thermally
`CODEC. The polysilicon-to-ahrminum
`capacitors are thermally
`grown using a double contact process. The first contact mask
`grown using a double contact process. The first contact mask
`is used to define normal diffusion or polysilicon-to-metal con-
`is used to define normal diffusion or polysilicon-to-metal
`con-
`tact openings and capacitor areas. A second contact mask is
`tact openings and capacitor areas. A second contact mask is
`used after the wafer goes through a reflow process to remove
`used after
`the wafer goes through a reflow process to remove
`oxide from normal contact areas. This mask is identical to the
`oxide from normal contact areas. This mask is identical
`to the
`first contact mask if no capacitors are present. Thus, capac-
`first contact mask if no capacitors are present.
`Thus, capac-
`itors are fabricated without the need for additional masking
`itors are fabricated without
`the need for additional masking
`steps.
`steps.
`
`111. CHIP ARCHITECTURE
`III. CHIP ARCHITECTURE
`The encoder and decoder with their corresponding filtering
`The encoder
`and decoder with
`their
`corresponding
`filtering
`functions were integrated on two separate chips. This con-
`functions
`were integrated
`on two
`separate
`chips.
`This
`con-
`figuration guarantees good isolation between the transmit and
`figuration
`guarantees
`good isolation
`between
`the transmit
`and
`receive functions. Integrating both functions on the same chip
`receive
`functions.
`Integrating
`both functions
`on the same chip
`makes such isolation difficult to achieve, especially under an
`makes
`such isolation
`difficult
`to achieve,
`especially
`under
`an
`asynchronous mode of operation. In addition, each chip of
`asynchronous
`mode
`of operation.
`In addition,
`each chip of
`such a pair is smaller than a single chip version and, as such,
`such a pair
`is smaller
`than a single chip version
`and, as such,
`yields are higher and costs are lower. Further, many applica-
`yields
`are higher
`and costs are lower.
`Further, many
`applica-
`tions exist where either the transmit or receive functions are
`tions
`exist where
`either
`the transmit
`or
`receive
`functions
`are
`separately required.
`separately
`required.
`Fig. 1(a), and (b) show the block diagram of the transmit
`Fig.
`1(a), and (b)
`show the block
`diagram of
`the transmit
`and receive chip, respectively. In the transmit chip the voice
`and receive
`chip,
`respectively.
`In the transmit
`chip the voice
`signal is applied to a switched capacitor active low-pass filter
`signal
`is applied
`to a switched
`capacitor
`active low-pass
`filter
`through an uncommitted operational amplifier. The uncom-
`through
`an uncommitted
`operational
`amplifier.
`The uncom-
`mitted operational amplifier is required for constructing an
`mitted
`operational
`amplifier
`is required
`for
`constructing
`an
`antialiasing filter with external passive components. These
`antialiasing
`filter
`with
`external
`passive
`components.
`These
`components can also be used for gain trimming. The low-pass
`components
`can also be used for gain trimming.
`The low-pass
`filter is followed by a high-pass filter which also acts as a
`filter
`is followed
`by
`a high-pass
`filter
`which
`also acts as a
`sample-and-hold for the encoder. The encoder performs the
`sample-and-hold
`for
`the encoder.
`The encoder
`performs
`the
`A/D conversion using a binary area ratioed capacitor array and
`A/D conversion
`using a binary
`area ratioed
`capacitor
`array and
`a linear resistor string. An auto zero loop is also included to
`a linear
`resistor
`string.
`An auto zero loop
`is also included
`to
`cancel any dc offset in the encoder/filter combination.
`cancel any dc offset
`in the encoder/filter
`combination.
`The phase-locked loop (PLL) synchronizes to an externally
`The phase-locked
`loop
`(PLL)
`synchronizes
`to an externally
`supplied strobe, typically 8 kHz, and provides all internal tim-
`supplied
`strobe,
`typically
`8 kHz,
`and provides
`all
`internal
`tim-
`ing. In addition, the PLL powers down the chip during the ab-
`ing.
`In addition,
`the PLL powers down the chip during
`the ab-
`
`0018-9200/79/1200-0961800.75 © 1979 IEEE
`001 8-9200/79/1200-0961$00.75
`@ 1979 IEEE
`
`Authorized licensed use limited to: Kilpatrick Townsend & Stockton LLP. Downloaded on May 11,2021 at 20:56:28 UTC from IEEE Xplore. Restrictions apply.
`
`TCL & Hisense
`Ex. 1008
`Page 1
`
`

`

`962
`962
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`
`—VREF
`‘VREF
`
`~
`
`BUFF
`BUFF
`
`+
`
`r
`r -+
`
`C ARRAY
`c ARRAY
`
`r
`,,,
`
`-
`COMP
`COMP
`
`AUTO ZERO
`AUTO ZERO
`
` 0 AZ FILTER
`AZ FILTER
`
`I
`
`A
`
`1°
`
`LOW
`
`PASS
`
`HIGH
`
`PASS
`
`128 Hz
`
`IBKHz
`
`A
`
`R STRING
`
`I ,’“– -/ ;0
`
`TEST
`TEST
`
`MODE
`MOOE
`
` 0 TEST
`TEST
`
`OUTPUT
`OUTPUT
`BUFFER
`BUFFER
`REGISTER
`REGISTER
`
`+
`
`+
`
` Q SHIFT CLOCK
`SHIFT CLOCK
`o
`
` -0 PCM OUT
`PCM OUT
`
`w
`
` 0 OUT CONTROL
`
`_ -“---&OuTcONTROTR
`
`SIGNALING
`SIGNALING
`LOGIC
`LOGIC
`
`I 1
`
`4
`
` 0 A SIG IN
`0
`A SIG 1’
`
`+
`
` 0 B SIG IN
`o
`B SIG IN
`
` 0
`
`A/B SELECT
`(A/B OUT)1
`
`A/D LOGIC
`A/O LOGIC
`
`.–_.
`
`__–___–
`
`t
`
`;
`
`I
`
`I I
`
`I
`L._
`L
`
`PHASE-LOCKED
`LOOP
`
`I
`
`I
`
`►
`
`L
`
`WER DOWN
`
`► 8KHz OUT (PROBE PAO)
`8KHz OUT (PROBE PAO)
`
`VINF 0
`
`‘IN+
`
`VIN —
`‘IN -
`
`STROBE
`STROBE
`(8KHz)
`(8KHz)
`
`LOOP
`LOOP
`FILTER 0
`FILTER o
`
`VDD 0
`
`Vss
`
`:;:LoG~
`
`ANALOG
`GND
`DIGITAL
`OIGITAL
`END
`GNo
`
`0 —
`
`$wER OOWN
`
`OPT,ON
`1, cc,~ A,B s,~’A~,NG
`CCIS A/8 SIGNALING OPTION
`
`S3501 ENCODER WITH FILTER BLOCK DIAGRAM (18 PIN PKG)
`S3501 ENCODER WITH FILTER BLOCK DIAGRAM
`(18 PIN PKG)
`(a)
`(a)
`~—_—_— —.—— ——.——— -—---——— 1
`r-
`
`YOUTH
`‘OUTH
`
`0 1(
`w
`
`LOOP
`LOOP
`FILTER 0
`o
`FILTER
`
`LOW PASS FILTER
`LOW PASS FILTER
`W SINX/X
`W SINX/X
`CORRECTION
`CORRECTION
`A
`
`128 KHz
`128 KHz
`
`I
`
`I
`SW
`
`8KHz
`
`S & H
`
`1i
`
`C ARRAY
`
`BUFF 4
`
`STROBE 0
`STROBE
`o
`
`PHASE-LOCKED LOOP
`
`R STRING
`
`IN
`IN -
`
`VOUTL
`‘OUTL
`
`VDD 0
`Voo ~
`
`v.
`
`vss ()-
`DIGITAL
`:::AL
`GND
`ANALOG
`ANALOG
`END
`GNO
`
`~
`
`~
`
`0
`o
`
`O
`o
`
`-
`
`VREF
`‘REF
`
` 0 SHIFT CLOCK
`o
`SHIFT CLOCK
`
`•
`o
`
`PCM IN
`PCM 1’
`
`I
`
`I
`I
`
`I
`
`I
`
`I I I
`
`i
`
`I
`
`I
`
`I
`
`J
`
`+0
` 10
`
`ABUT
`‘oUT
`
` PO BOUT
`M
`‘OUT
`
`•
`o
`
`A/B SELECT (A/B IN)*
`A/s SELECT (A/B IN)”
`
` Q POLARITY
`POLARITY
`o
`(CND OR 1/00)
`(G ND ORVSJ
`
`0/A LOGIC
`
`POWER
`DOWN
`8KHz
`(PROBE PAD)
`IPROSE PAO)
`
`INPUT BUFFER
`INPUT BUFFER
`REGISTER
`REGISTER
`
`+
`
`A
`
`=
`
`ENABLE
`ENABLE
`
`~———— —-——--—-——————
`
`►
`
`*
`
`I
`
`SIGNALING LOGIC
`SIGNALING LOGIC
`
`4
`
`1
`
`• CCIS A/B SIGNALING OPTION
`*CCIS A/B SIGNALING OPTION
`
`S3502 DECODER WITH FILTER BLOCK DIAGRAM (16 PIN PKG)
`S3502 DECODER WITH FILTER BLOCK DIAGRAM
`(16 PIN PKG)
`
`(b)
`(b)
`Fig. 1.
`(a) Block diagram for the transmit chip.
`(b) Block diagram for the receive chip.
`Fig. 1. (a) Block diagram for the transmit chip. (b) Block diagram for the receive chip.
`
`sence of the 8 kHz strobe by driving a power-on reset (POR)
`sence of
`the 8 kHz strobe by driving a power-on reset (POR)
`circuit. The converted 8 bit PCM word is shifted out by a shift
`circuit.
`The converted 8 bit PCM word is shifted out by a shift
`clock using a tristate output driver. This facilitates tying the
`clock using a tristate output driver.
`This facilitates
`tying the
`PCM outputs of multiplexed CODEC's on a time shared bus.
`PCM outputs of multiplexed CODEC’S on a time shared bus.
`The receive chip accepts the PCM word and performs the D/A
`The receive chip accepts the PCM word and performs the D/A
`
`conversion. The output of the decoder is sampled and held
`conversion.
`The output
`of
`the decoder
`is sampled and held
`and introduced into a switched-capacitor active low-pass re-
`and introduced
`into a switched-capacitor
`active low-pass re-
`construction filter. A separate uncommitted-low output-
`construction
`filter.
`A separate uncommitted-low
`output-
`impedance operational amplifier is provided in this chip capable
`impedance operational amplifier
`is provided in this chip capable
`of driving a 600 Q hybrid.
`For users not
`requiring this func-
`of driving a 600 &2 hybrid. For users not requiring this func-
`
`Authorized licensed use limited to: Kilpatrick Townsend & Stockton LLP. Downloaded on May 11,2021 at 20:56:28 UTC from IEEE Xplore. Restrictions apply.
`
`TCL & Hisense
`Ex. 1008
`Page 2
`
`

`

`HAQUE et al.: TWO CHIP PCM VOICE CODEC WITH FILTERS
`HAQfJE et al.: TWO CHIP PCM VOICE CODEC WITH FILTERS
`
`963
`963
`
`FROM OTHER
`POINTS IN
`HIGH PA55 FILTER
`
`LOG/C
`LOGIC
`
`i L
`
`LOWER PLATE
`O w.SR PUT.=
`SWITCH CONTROL
`SWITCH
`CONTROL
`
`SA
`
`OUTPUT 0
`,,
`SAND LIMIT
`FILTER
`
`,n
`
`128c
`
`COMPARATOR
`COMPMAT06
`
`-,,f
`
`&“”’]
`
`,3
`
`AuToZERo LOOP
`AUTOZERO
`LOOP
`
`~
`
`.pJ_LI13t3113AJ
`
`,
`
`9
`
`1
`
`VREF
`
`VREF
`
`AUTO ZERO LOOP
`AUTOZEROLOOP
`Fig. 2. Block diagram representation of the key section of A/D.
`Fig. 2. Block diagram representation of
`the key section of A/D.
`
`tion the operational amplifier can be effectively turned off to
`tion the operational amplifier
`can be effectively
`turned off
`to
`save power.
`save power.
`Both chips include functions required for supervision and
`Both chips include
`functions
`required for supervision and
`signaling in telephone systems. Both in band signaling (where
`signaling in telephone systems. Both in band signaling (where
`the LSB of the processed word is replaced every sixth frame
`the LSB of
`the processed word is replaced every sixth frame
`by A signal and B signal inputs) and common channel interof-
`by A signal and B signal
`inputs) and common channel
`interof-
`fice signaling (CCIS) schemes (where a separate signaling high-
`fice signaling (CCIS) schemes (where a separate signaling high-
`way exists) are implemented. In addition, noninverted and in-
`way exists) are implemented.
`In addition, noninverted
`and in-
`verted (for relay drive applications) signaling options are
`verted
`(for
`relay
`drive applications)
`signaling options
`are
`available.
`available.
`The use of the PLL makes the system very flexible, since the
`The use of the PLL makes the system very flexible,
`since the
`8 kHz strobe (an internationally accepted standard) fixes all
`8 kHz strobe (an internationally
`accepted standard)
`fixes all
`internal timing independent of the shift clock rate which is used
`internal
`timing independent of
`the shift clock rate which is used
`to shift out the converted PCM data. The shift clock rate of
`to shift out
`the converted PCM data. The shift clock rate of
`the chip can be arbitrary to 3.1 MHz. The architecture of
`the chip can be arbitrary
`to 3.1 MHz.
`The architecture
`of
`these chips was aimed at minimizing overall cost of the sys-
`these chips was aimed at minimizing
`overall cost of
`the sys-
`tem where the CODEC will be used. This was achieved by in-
`tem where the CODEC will be used. This was achieved by in-
`tegrating the described features and by making the chip re-
`tegrating
`the described features and by making the chip re-
`quirements flexible. Hence, the operating power supplies are
`quirements
`flexible.
`Hence,
`the operating power supplies are
`allowed to vary from -±4.75 to ±7.5 V. In addition, only one
`allowed to vary from t4.75
`to *7.5 V.
`In addition, only one
`common reference is required which can be shared among
`common
`reference is required which can be shared among
`several CODEC's (i.e., 24 or 32 in a channel bank). This is
`several CODEC’s (i.e., 24 or 32 in a channel bank).
`This is
`achieved by buffering the reference on-chip. Also power sup-
`achieved by buffering
`the reference on-chip.
`Also power sup-
`ply and reference voltage decoupling were kept minimal (i.e.,
`ply and reference voltage decoupling were kept minimal
`(i.e.,
`0.1 µF capacitor). The use of the PLL (which eliminates the
`0.1 flF capacitor).
`The use of
`the PLL (which eliminates the
`need for extra clock inputs) and the use of multiplexing on
`need for extra clock inputs) and the use of multiplexing
`on
`certain pins enabled the chips to be packaged in an 18 pin
`certain pins enabled the chips to be packaged in an 18 pin
`(16 pins for the receive chip) 300 mil wide package. The narrow
`(16 pins for
`the receive chip) 300 mil wide package. The narrow
`packages have lower cost, are machine insertable, and result in
`packages have lower cost, are machine insertable, and result
`in
`a compact printed circuit board layout. To fit the package,
`a compact printed
`circuit board layout.
`To fit
`the package,
`the chip dimensions were tailored to be narrow on one side.
`the chip dimensions were tailored to be narrow on one side.
`
`IV. CIRCUIT
`IV. CIRCUIT DESIGN
`DESIGN
`A. AID and D/A Conversion Schemes
`A. A/D and D/A Conversion Schemes
`The CODEC design is based on charge redistribution in a
`The CODEC design is based on charge redistribution
`in a
`binary weighted array of capacitors [2] . In the present work,
`binary weighted array of capacitors
`[2]
`.
`In the present work,
`a capacitor array is used to define the decision levels corre-
`a capacitor array is used to define the decision levels corre-
`sponding to the end points of the companding segments. To
`sponding to the end points of
`the commanding segments. To
`
`generate the linearly spaced decision levels within the segments,
`generate the linearly spaced decision levels within the segments,
`however, a resistor array is used instead of another capacitor
`however, a resistor array is used instead of another capacitor
`array, and buffer amplifier. Use of a resistor array for this ap-
`array and buffer amplifier.
`Use of a resistor array for
`this ap-
`plication has been reported in previous work [3] . However,
`plication
`has been reported in previous work
`[3]
`. However,
`the configuration of the array used here is different.
`the configuration
`of
`the array used here is different.
`The design approach to be described here differs from other
`The design approach to be described here differs from other
`designs based on the charge redistribution principle in that it
`designs based on the charge ~edistribution
`principle in that
`it
`uses state sequencing of switches to achieve data conversion of
`uses state sequencing of switches to achieve data conversion of
`bipolar signals with a single polarity reference. This is achieved
`bipolar signals with a single polarity
`reference. This is achieved
`by switching the capacitors in the capacitor array from analog
`by switching the capacitors in the capacitor array from analog
`ground to V re f (reference voltage) for a +VTef increment, and
`ground to V’ref (reference voltage)
`for a + Vref increment,
`and
`from Vref to analog ground for a - Vref increment. Apart from
`from Vref to analog ground for a - V,ef increment.
`Apart
`from
`the fact that only one reference is needed, this scheme has the
`the fact
`that only one reference is needed,
`this scheme has the
`advantage that the two reference swings achieved at the ca-
`advantage that
`the two reference swings achieved at
`the ca-
`pacitor array are identical in magnitude, i.e., no mismatch
`pacitor
`array are identical
`in magnitude,
`l.e., no mismatch
`occurs.
`occurs.
`Fig. 2. shows a simplified schematic of the analog portion of
`Fig. 2. shows a simplified schematic of
`the analog portion of
`the transmit circuit. Initially, the input analog voltage from
`the transmit
`circuit.
`Initially,
`the input analog voltage from
`the band-limiting filter is sampled on the top plate of the ca-
`the band-limiting
`filter
`is sampled on the top plate of
`the ca~
`pacitor array with the bottom plate being connected to Vref
`pacitor array with the bottom plate being connected io V,ei
`(normally -3 V). This corresponds to position 1 for the lower
`(normally
`-3 V). This corresponds to position 1 for
`the lower
`plate switches. The sign of the signal is then determined and if
`plate switches. The sign of
`the signal
`is then determined and if
`the signal is positive the lower plates are connected to position
`the signal
`is positive the lower plates are connected to position
`3 (i.e., ground) with switch SA still being on. If the signal is
`3 (i.e., ground) with switch S’ still being on.
`If
`the signal
`is
`negative, the lower plates are left connected in position 1 and
`negative,
`the lower plates are left connected in position 1 and
`switch SA is turned off. The segment bits (i.e., chords) are
`switch S~ is turned off.
`The segment bits (i.e., chords) are
`found by a sequential technique where, starting with the small-
`found by a sequential
`technique where, starting with the small-
`est capacitor, the voltage on the lower' plate of the array is
`est capacitor,
`the voltage on the lower plate of
`the array IS
`changed by -Vref (for a negative signal) by switching the lower
`changed by - Vref (for a negative signal) by switching the 10wer
`plate connection from position 1 to 3, or by Wref (for a posi-
`plate connection
`from position
`1 to 3, or by +Vref (fc)r a posi-
`tive signal) by changing the lower plate switch from position 3
`tive signal) by changing the lower plate switch from position 3
`to 1 until the comparator changes sign. This determines the
`to 1 until
`the comparator
`changes sign. This determines the
`chord. The linear resistor string with 32 taps is then used to
`chord.
`The linear
`resist or string with 32 taps is then used to
`present (Vref/32) k V (k = 0 to 32) to the lower plate of one
`present
`(Vref/32)
`k V (k= O to 32)
`to the lower plate of one
`capacitor (selected by the sequential search for the chords) in
`capacitor
`(selected by the sequential search for
`the chords)
`in
`the capacitor array. A successive approximation technique is
`the capacitor array. A successive approximation
`technique is
`then used to determine the 4 bits corresponding to the linear
`then used to determine the 4 bits corresponding
`to the linear
`division of the chords (this technique was not used for the
`division
`of
`the chords (this technique was not used for
`the
`
`Authorized licensed use limited to: Kilpatrick Townsend & Stockton LLP. Downloaded on May 11,2021 at 20:56:28 UTC from IEEE Xplore. Restrictions apply.
`
`TCL & Hisense
`Ex. 1008
`Page 3
`
`

`

`964
`964
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979
`IEEE JOURNAL
`OF SOLID-STATE
`CIRCUITS,
`VOL.
`SC-14, NO. 6, DECEMBER
`1979
`
`,,
`chords because for coding of the smallest signal more than one
`chords because for coding of the smallest signal more than one
`capacitor needs to be switched simultaneously, as opposed to
`capacitor needs to be switched simultaneously,
`as opposed to
`only one in the sequential scheme, thus increasing the risk of
`thus increasing the risk of
`only one in the ,sequential scheme,
`disturbing the sensing node during a critical phase of the con-
`disturbing the sensing node during a critical phase of the con-
`version). The decoder uses similar principles to achieve the
`version).
`The decoder uses similar principles
`to achieve the
`data conversion. The linear resistor string has 32 equal taps on
`data conversion. The linear resistor string has 32 equal taps on
`the transmit chip to implement the half-step shift adjacent to
`the transmit
`chip to implement
`the half-step shift adjacent
`to
`the origin. In the decoder, 32 equal taps are used to implement
`the origin.
`In the decoder, 32 equal taps are used to implement
`half-step shifts corresponding to the signaling frames (where
`half-step shifts corresponding
`to the signaling frames (where
`the LSB of the processed word is replaced by signaling bits)
`the LSB of
`the processed word is replaced by signaling bits)
`and information frames (where the unaltered 8 bit PCM word
`and information
`frames (where the unaltered 8 bit PCM word
`is available).
`is available).
`
`,’
`B. Offset Compensation
`B. Offset Compensation
`In order to meet stringent system requirements, it is necessary
`In order to meet stringent system requirements,
`it is necessary
`to cancel any offset voltage in the encoder. The offset is
`to cancel any offset
`voltage in the encoder.
`The offset
`is
`caused by comparator and filter offset voltages and by clock
`caused by comparator
`and filter offset voltages and by clock
`feedthrough on the top plates of the capacitor array through
`feedthrough
`on the top plates of
`the capacitor array through
`the parasitic capacitance of the switch driving it. Offset can-
`the parasitic capacitance of
`the switch driving it. Offset can-
`cellation is achieved by integrating the PCM sign bit (using an
`cellation is achieved by integrating the PCM sign bit
`(using an
`on-chip resistor and an external capacitor) and feeding back the
`on-chip resistor and an external capacitor) and feeding back the
`result into the last stage of the high-pass filter, as shown in
`result
`into the last stage of
`the high-pass filter,
`as shown in
`Fig. 2. The time constant of the auto zero loop is several sec-
`Fig. 2. The time constant of
`the auto zero loop is several sec-
`onds. For faster acquisition of offsets immediately after
`For
`faster acquisition
`of offsets immediately
`after
`onds.
`power-up, a dual bandwidth loop was implemented. The auto
`power-up, a dual bandwidth
`loop was implemented.
`The auto
`zero loop is powered up immediately on application of the
`zero loop is powered up immediately
`on application
`of
`the
`strobe signal. The loop starts with a large bandwidth by se-
`strobe signal.
`The loop starts with a large bandwidth
`by se-
`lecting a smaller on-chip integrating resistance. The PLL in the
`lecting a smaller on-chip integrating resistance. The PLL in the
`meantime acquires lock and drives a POR circuit to enable the
`meantime acquires lock and drives a POR circuit
`to enable the
`chip. As soon as the chip is enabled, the auto zero loop
`chip.
`As soon as the chip is enabled,
`the auto zero loop
`switches to a lower bandwidth. This feature not only im-
`switches to a lower bandwidth.
`This feature not only im-
`proves circuit performance immediately after power-up but
`proves circuit
`performance
`immediately
`after power-up but
`also eases automated testing of these chips.
`also eases automated testing of
`these chips.
`
`C. Operational Amplifiers
`C. Operational Amplifiers
`The transmit and receive chips required 20 operational am-
`The transmit
`and receive chips required 20 operational
`am-
`plifiers, out of which three had to have low-impedance out-
`plifiers,
`out of w~ch
`three had to have low-impedance
`out-
`puts capable of driving 600 E2 loads. Due to the large number
`puts capable of driving 600 S? loads. Due to the large number
`of amplifiers, the power dissipation of each amplifier had to be
`of amplifiers,
`the power dissipation of each amplifier had to be
`minimized. In addition, due to the large mix of digital and
`minimized.
`In addition,
`due to the large mix of digital and
`analog circuitry, the power supply rejection had to be accept-
`analog circuitry,,
`the power supply rejection had to be accept-
`able to limit noise from power supply lines getting coupled onto
`able to limit noise from power supply lines getting coupled onto
`analog signal paths.
`analog signal paths.
`Figs. 3 and 4 show the schematic of a high and low output
`Figs. 3 and 4 show the schematic of a high and low output
`impedance operational amplifier. A key feature of the circuits
`impedance operational
`amplifier.
`A key feature of
`the circuits
`is the class A-B operation of the output stage which results in
`is the class A-j
`operation of the output stage which results in
`significantly reduced power dissipation and higher open loop
`si&ificantly
`reduced power dissipation and higher open loop
`gain. Further reduction in power dissipation is obtained by
`gain.
`Further
`reduction
`in power dissipation
`is obtained by
`using a frequency compensation scheme which does not use a
`using a frequency
`compensation
`scheme which does not use a
`buffer amplifier (normally used to prevent the feedforward of
`buffer amplifier
`(normally
`used to prevent
`the feedforward
`of
`the signal through the compensation capacitor which creates a
`the signal
`through the compensation capacitor which creates a
`low-frequency zero in the transfer function [4]). Instead, the
`low-frequency
`zero in the transfer
`function
`[4]).
`Instead,
`the
`compensation capacitor is introduced through a resistor (using
`compensation
`capacitor
`is introduced
`through a resistor
`(using
`Q10, Q11). This creates a zero in the position of the second
`QIO, Q1 1). This creates a zero in the position of
`the second
`dominant pole and helps stabilize the amplifier. In principle,
`dominant pole and helps stabilize the amplifier.
`In principle,
`the operational amplifier can be stabilized using C1 only. Use
`the operational
`amplifier
`can be stabilized using Cl only. Use
`of C2 along with C1 , however, improves the power supply re-
`of Cz along with C’l, however,
`improves the power supply re-
`jection ratio (PSRR) as follows: node 1 (in Fig. 3) is a high-
`jection
`ratio (PSRR) as follows:
`node 1 (in Fig. 3) is a high-
`
`Qb
`
`Q I
`
`I
`
`QS
`
`A ‘
`Q+
`Qs1-
`
`CI
`
`QH
`
`05
`
`cz
`
`B AS
`BIAS
`
`II
`
`03
`Q3
`
`09
`
`Qa
`
`Schematic of high-output impedanceoperational amplifier.
`Fig. 3. Schematic of high-output impedance operational amplifier.
`Fig. 3.
`
`00
`
`VDO,’
`
`--i
`
`Oa Vs
`
`BMS
`6/4
`
`Q3
`
`V.r.s 1’
`
`vss
`
`07
`
`0/
`
`08
`
`C,
`
`CZ
`
`9/C
`
`0//
`
`C3
`
`09
`
`1 ]
`
`OZ
`
`Q/2
`/2
`
`1
`
`I
`
`Fig. 4. Schematic of the low-output impedance operational amplifier.
`Fig. 4. Schematic of
`the low-output
`impedance operational amplifier.
`
`impedance point and any noise on VDD appears essentially un-
`impedance point and any noise on V~~ appears essentially un-
`attenuated on it at low frequencies. Thus, at low frequencies
`attenuated on it at low frequ