880
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7 , JULY 1996
`
`A 1 GHz CMOS RF Front-End IC for a
`Direct-Conversion Wireless Receiver
`
`Ahmadreza Rofougaran, James Y.-C. Chang, Maryam Rofougaran, and Asad A. Abidi, Fellow, IEEE
`
`integrated low-noise amplifier and downconver-
`Abstract-An
`sion mixer operating at 1 GHz has been fabricated for the first
`time in 1 pm CMOS. The overall conversion gain is almost 20 dB,
`the double-sideband noise figure is 3.2 dB, the IIP3 is $8 dBm,
`and the circuit takes 9 mA from a 3 V supply. Circuit design
`methods which exploit the features of CMOS well suited to these
`functions are in large part responsible for this performance. The
`front-end is also characterized in several other ways relevant to
`direct-conversion receivers.
`
`I. INTRODUCTION
`OTIVATED by the growing needs for low-power and
`low-cost wireless transceivers, mainstream IC technolo-
`gies are competing to integrate more W functions onto a single
`chip. Bipolar circuits dominate integration at 1 GHz today,
`followed by GaAs IC’s. As recent results demonstrate, CMOS
`too is a viable contender in this frequency range [1]-[6].
`If CMOS is shown to perform in certain important respects
`as well as circuits in other established technologies, and it
`successfully merges analog and digital blocks, its use at RF
`may become as compelling as it is in baseband circuits.
`To date, most research on CMOS RF circuits shows the
`feasibility of elementary RF building blocks, such as stand-
`alone tuned amplifiers [l], mixer IC’s [2], [5], and oscillators
`[7]. The next development step calls for the integration of
`these building blocks into subcells, comparable in function to
`currently available small-scale RF IC’s in bipolar or GaAs
`technology. The most common example of such an IC is an
`RF low-noise amplifier (LNA) combined with a downconver-
`sion mixer, often labeled the front-end for an RF receiver.
`Integrated front-ends are widely used because they combine
`all the RF signal processing on one chip, often requiring only
`a small overhead of off-chip components, and they produce
`an amplified signal translated down to a conveniently low
`intermediate frequency (IF) at the output. Thereafter, it is
`relatively simple to implement IF and baseband circuits for
`the rest of the receiver. The work reported here is the first
`implementation of a 1 GHz front-end in CMOS.
`The front-end of a wireless receiver must meet several
`exacting specifications. First is sensitivity. The input noise of
`the front-end must be sufficiently low to enable it to detect
`
`Manuscript received January 23, 1996; revised March 5, 1996. This work
`was supported by the U.S. Advanced Research Projects Agency, Rockwell
`Intemational, Texas Instruments, Harris Semiconductor, Advanced Micro
`Devices, Hewlett-Packard Company. and the State of California MICRO
`Program.
`The authors are with the Integrated Circuits & Systems Laboratory, Elec-
`trical Engineering Depautment, University of Califomia, Los Angeles, CA
`90095-1594 USA.
`Publisher Item Identifier S 0018-9200(96)04472- 1.
`
`Fig. I. A direct-conversion receiver suitable for FSK modulation.
`
`weak input signals. The front-end gain must be high enough to
`overcome the noise contributions of later circuits, which may
`otherwise degrade the receiver sensitivity. Second, a front-end
`with a wide input dynamic range can tolerate large undesired
`signals nearby in frequency to a weak desired signal, which
`may otherwise, through intermodulation distortion, create en-
`ergy at frequencies overlapping the desired channel. Third, the
`RF input impedance of the front-end must be a good match to
`the antenna characteristic impedance over the frequency band
`of interest.
`The LNA and mixer together determine the performance
`of the front-end. For instance, although a large LNA gain is
`desirable as mentioned above, too large a gain may overload
`the mixer and compromise dynamic range. On the other hand,
`the gain must be large enough to overcome the fundamentally
`higher mixer noise. It is also desirable to connect the LNA in
`some simple way to the mixer input, without a power-hungry
`RF buffer. The front-end design is influenced by its intended
`use, as discussed below. Therefore, good performance is only
`obtained through careful co-design of the front-end building
`blocks.
`This front-end is intended for a direct-conversion, or zero-
`IF, frequency-shift keying (FSK) receiver [8], which simplifies
`how the blocks are connected together (Fig. 1). In a su-
`perheterodyne receiver, a passive filter-usually
`a second
`preselect filter of the type connected to the antenna-follows
`the LNA [9] to suppress the amplifier noise in the image of the
`RF input band, where there is no signal. Without this filter, the
`downconverted signal must contend with downconverted noise
`from both the signalebearing and the idle sidebands. In a direct-
`conversion receiver, On the Other hand, the local oscillator
`(LO) is centered in the desired channel, so useful signal energy,
`and noise, occupy both upper and lower sidebands,
`there
`is now no idle sideband to be filtered, the LNA is directly
`connected to the downconversion mixer. Therefore, when a
`
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`ROFOUGARAN et al.: A 1 GHz CMOS RF FRONT-END IC FOR A DIRECT-CONVERSION WIRELESS RECEIVER
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`881
`
`t
`
`Low-noise amplifier with tuned load and an off-chip tuning inductor
`Fig. 3.
`at the input port.
`
`Lo
`
`I
`
`I
`
`1s
`
`RF In
`
`(a)
`(b)
`Candidate FET LNA input stages. (a) Common-source stage, with
`Fig. 2.
`lossless matching network. (b) Common-gate stage.
`
`modulation !such as FSK permits use of direct-conversion [ 101,
`the receiver may be integrated with a need for very few
`off-chip components. There are several advantages to this,
`mainly small physical volume, less wasted power in buffering
`high-frequency signals off-chip, and lower assembly costs.
`However, the receiver requires a vector baseband signal path,
`consisting of two branches downconverted in quadrature to
`prevent the signal-bearing image sidebands from aliasing on
`one another.
`
`11. CIRCUIT DESIGN
`
`A. Low-Noise AmplGer
`The LNA. must simultaneously attain high RF gain, low
`input noise, and a good input match to 50 R. These require-
`ments are often interdependent in a simple circuit, and may
`require iterative design for all to be fulfilled. The following
`discussion on a CMOS LNA design covers input impedance
`matching first, then input noise, and finally voltage gain.
`The gate of a FET fabricated in 1-pm technology is ca-
`pacitive to frequencies beyond 1 GHz.' However, a lossless
`matching network, consisting only of inductors and capacitors
`can transform the FET input into a pure resistance over
`some frequency band of interest. The most common matching
`network for FET's consists of a series feedback inductor, L,,
`in the FET source, and another inductor, L,, in series with
`the gate to tune out the capacitance C,,, resulting in an input
`resistance gm L,/C,, where gm is the FET transconductance
`[Fig. 2(a)] [ 111. This method is preferred over resistor feed-
`back because the matching network introduces no noise of
`its own. However, loss in practical inductors L, and L, will
`tend to degr,ade noise figure. With sufficiently good inductors,
`though, a noise figure well below 3 dB may be obtained
`with this technique, ultimately limited by such transistor
`imperfections as nonzero gate resistance.
`When a noise figure of 3 dB is acceptable, as it is in our
`receiver, it is simpler to regulate the input impedance with
`a common-gate input stage [12] [Fig. 2(b)]. For the sake of
`discussion, first suppose that the load resistance at the drain
`is much lesis than the FET TdS, and that gTnTds 2 10. Then
`the input resistance at the FET source is l/gTn. At 1 GHz,
`the FET C,:, and parasitic input capacitance, Cp, due to
`the bonding pads and external strays significantly shunt this
`
`'This assumes the FET is laid out sensibly. The gate resistance of a FET
`with a certain channel width is lowered by an interdigitated gate, whereas
`without such a layout, this resistance may dominate the FET input impedance
`.
`.
`
`at high frequencies.
`
`resistance. Therefore, to achieve a good impedance match, the
`size and bias of the FET are selected for l/gm = 50 R, and an
`inductor tunes out the shunt capacitance: by parallel resonance
`in a frequency band around 1 GHz. As the capacitance at the
`LNA input is to be tuned, it makes good sense to do so with
`a grounded off-chip low-loss inductor, which also carries the
`LNA bias current.
`Fortuitously, a FET with a small-signal channel resistance
`of 50 R produces a lower thermal nois': current than a linear
`resistor of the same value [13]. The noise current spectral
`density in the FET is 4kTyg,A21Hz, where y 3 0.67 owing
`to the distributed inversion layer. Thus, ruling out any other
`noise sources in a matched LNA, the noise figure due to
`the FET alone is 101og 1.67 = 2.2 dB. In a short-channel
`FET biased at unfavorable conditions, hot-electron effects may
`augment this [14] to raise the noise figure. Flicker noise in the
`FET is unimportant at RF.
`A tuned load peaks the frequency response of the LNA in
`the band of interest (Fig. 3), in effect transforming the inherent
`lowpass characteristic of the amplifier to a bandpass. The load
`also helps to reject out-of-band signalr and noise. However,
`the LNA passband is seldom sufficiently flat and narrow for
`RF preselection, that is, to suppress image channels and out-
`of-band interferers. Rather, a sharply tuned discrete filter, such
`as SAW or dielectric resonator, is inserted before the LNA for
`this purpose. Discrete filters usually operate at a characteristic
`impedance of 50 R or 75 R. As explained above, no preselect
`filter need follow this LNA, nor the IRF buffer required to
`drive the filter.
`The tuned load, therefore, comprises an inductor resonating
`with the FET drain capacitance, CD, and the sum, Cp, of the
`input capacitance of the subsequent dow nconversion mixer and
`any other parasitics. Another advantage of the common-gate
`stage is that the somewhat large CGD of the FET returns its
`current to a fixed bias, rather than to the input node as it
`would in a common-source amplifier. This current undergoes
`rapid phase-shifts with frequency in an RF tuned amplifier,
`and makes it difficult to design an input matching circuit.
`The inductance, L, to tune this total capacitive load to the
`resonant frequency W O , in our case 27r Grads, is
`L = 1 / w i (CO + cl>).
`In most modern FET's, the drain junction capacitance CD 3
`CCS. Furthermore. the unitv-current gain freauencv. WT =
`
`U"
`
`c
`
`1
`
`(1)
`
`, I
`
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`882
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996
`
`g m / C G S . The inductance may then be expressed as
`1
`W & L l W T + C P ) '
`L =
`(2)
`If inductor loss, as modeled by a series resistance Rs, limits
`the impedance of the tuned load at resonance, then using (2),
`the voltage gain of the common-gate stage is
`
`Gain = gm-
`
`( W o - q 2
`R S
`
`This form makes it clear which parameters are within the
`circuit designer's reach to determine RF gain. WT mainly
`depends on FET channel length, but is also controlled by
`gate bias. However, even with infinite W T , parasitic-related
`quantities will limit the maximum achievable gain to
`
`Fig. 4.
`fitted to
`
`(4)
`
`In the common-gate amplifier, the desired input impedance
`sets gm. Thus, a large parasitic capacitance at the drain means
`a smaller achievable gain, unless the loss in the load inductor
`is somehow lowered to boost the gain. The relative quality of
`the inductor, L/Rs, depends on how it is physically realized,
`and there are limits to how large this may be in practice. For
`instance, at 1 GHz the L / R s is 4 nWR for a discrete 10 nH
`chip inductor meant for RF applications [15]. This argues for
`an on-chip inductor load, because it is unlikely that a discrete
`off-chip inductor can overcome, simply because of a higher
`quality, the RF gain loss due to the large parasitic capacitance
`of the bond pads, bondwires, package leads, and board traces.
`The LNA fulfills its specifications at the price of power
`dissipation. At low values of gate drive voltage, long-channel
`FET laws fairly well describe the dependence of bias current,
`I D , on the transconductance
`1
`i g m ( v G S - &).
`
`ID
`
`(5)
`
`7
`6
`
`5 s 4
`u \ 3 *+
`2
`1
`
`0.1
`
`0.2
`v
`V,,-V,,
`Measured f r versus VGS - Vt for MOSIS 1-pm NMOSFET (points)
`simple expression (line).
`
`0.3
`
`0.4
`
`0.5
`
`160
`
`0
`
`5
`15
`10
`Na of Turm in Spiral
`
`20
`
`2000,
`
`No. of turns in spiral
`
`Similarly, at low gate drives, the WT of a FET theoretically
`follows the dependence
`
`Fig. 5. Design curves for square spiral on-chip inductor. (a) Inductance and
`resistance of spiral versus number of turns and (b) capacitance of inductor
`(assuming it is an equipotential) to substrate through 1 p m thick field oxide.
`
`where 8 captures how the inversion-layer mobility, k, degrades
`with gate electric field [16]. While (5) is readily verified by
`measurement, there is little data in the literature on CMOS wT
`to validate (6). Therefore, the s-parameters of a single, large
`1-pm NFET were characterized on a CascadeTM probe station,
`from which WT was deduced. The measured data (Fig. 4)
`conforms closely to (6) in the V& - V,
`shows that WT = 2
`~
`f
`~
`
`range of interest. This curve serves as an important design aid.
`Using (2), the load inductance may be calculated which
`tunes the LNA to a certain frequency in the absence of any
`significant parasitics. For instance, if the FET is biased at an
`f~ of 5 GHz, then the LNA requires a 40 nH inductor load
`to achieve a peak at 1 GHz in its frequency response. The
`inductor may be implemented on-chip as a square spiral in
`
`Metal-2, with the return conductor in Metal-1. Greenhouse's
`formula accurately specifies how the inductance grows with
`the number of turns [17], while the series resistance accu-
`mulates with the number of squares of metal comprising the
`spiral [Fig. S(a)]. The spiral grows outwards from a 140 pm
`square hole in the middle. Any turns within the hole would
`enclose relatively little magnetic flux, but would contribute
`a nonnegligible unwanted resistance. These curves show that
`in the inductance range of 40 to 50 nH, the relative quality,
`LIRs, of the spiral is about 0.7 nWR. It is seen from (3),
`(5), and Fig. 4 that the LNA may achieve a gain as large as
`20 dB at 1 GHz in the absence of parasitic capacitance, while
`drawing 1.5 mA of current per FET.
`The main impediment to a practical implementation of the
`tuned amplifier arises from the parasitic capacitance of a SO nH
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`ROFOUGARAN t r t al.: A 1 GHz CMOS RF FRONT-END IC FOR A DIRECT-CONVERSION WIRELESS RECEIVER
`
`883
`
`spiral inductor to the semiconductor substrate. This is so large
`through the typical 1 pm-thick field oxide [Fig. 5(b)] that the
`spiral self-resonates at 700 MHz, and at 1 GHz appears as a
`capacitive, rather than inductive, load on the LNA. This is why
`it is general1.y believed that medium- to large-value inductors
`may only be integrated on semi-insulating substrates, while on
`a standard silicon substrate inductors no larger in value than
`5 to 10 nH are usable at 1 GHz [18].
`In earlier vvork, we have described a method to eliminate the
`parasitic capacitance under the spiral inductor by selectively
`removing thle underlying silicon substrate [ 11. This leaves
`the spiral encased in a layer of oxide suspended above an
`air-gap. Inductors as large as 100 nH may be fabricated
`in CMOS, whose self-resonance frequency, now limited by
`the small fringing capacitance through the air gap to the
`distant ground plane, lies beyond 2 GHz. This maskless,
`post-fabrication etching of the substrate does not require any
`foundry modiifications in the 1-pm CMOS process available
`through MOSIS. Via holes which will expose the surface of the
`silicon after fabrication and passivation surround the spiral. A
`selective etchant removes the exposed silicon at a much higher
`rate than it does oxide and metal. After sufficient exposure to
`the etchant, a deep cavity forms under the inductor, while the
`remaining active area on the chip is left intact. A passivating
`coat protects the exposed silicon on the sides and back of the
`chip from inadvertent etching.
`The substrate was removed in the earlier work by a liquid-
`phase, aniso1.ropic etchant [ 11, resulting in a spiral inductor
`surrounded by large trapezoidal openings, and attached by
`four oxide bridges to the rest of the CMOS substrate. This has
`since been replaced by a gas-phase, isotropic etchant. Through
`small circular openings surrounding the spiral, the etchant
`now excavates hemispherical pits whose radius increases with
`exposure time. Etching is stopped when the multiple pits
`coalesce into one large pit with a depth of roughly half of
`one side of the spiral (Fig. 6). This suspended inductor enables
`wholly-integrated RF components in CMOS. In addition to the
`LNA, it is also used in the local oscillator, power amplifier, and
`even as a low quality bandpass filter. As a survey in a recent
`publication shows [ 191, no simpler method has yet been found
`to realize large-value integrated inductors.
`It was assumed in the earlier analysis that the impedance,
`2, of the LlVA tuned load is much less than the FET yds.
`When this is not so, the expressions for the gain and input
`impedance must be modified to
`
`The complete LNA is a balanced circuit (Fig. 7). A power-
`conserving, passive balun converts a single-ended antenna
`signal into a balanced input drive to the LNA. A printed-circuit
`balun may even be integrated into the transceiver case. The
`bias, VG, at the common-gate FET’s regulates the LNA input
`impedance. An on-chip scaled-down replica circuit stabilizes
`this impedance against variations in process and temperature
`as follows. .An op-amp drives the V G bias voltage of the
`replica to servo the dc value of l/gm to an off-chip reference
`
`Suspended 50 nH spiral inductor over a hemispherical cavity etched
`Fig. 6.
`underneath through surrounding via holes.
`
`7
`
`r-+l
`
`50nH 9
`
`Fig. 7. Low-noise amplifier circuit diagram
`
`resistance, and the same voltage is then applied to the main
`LNA, thereby regulating its input impedance to within the FET
`matching in the replica and the main circuits. As the feedback
`loop bandwidth is well below 1 MHz, the op-amp does not
`contribute any RF noise. The inductor loads on each half of
`the circuit share a common top-node, which connects to the
`3 V power supply through a triode-region PFET. By adjusting
`the gate voltage, V C , the dc voltage drop across this PFET
`resistor may be changed, and this sets the dc level at the LNA
`output.
`The LNA FET’s are biased at V.S - 1: = 0.35 V, and drain
`2.2 mA each. Taking into account the capacitive load of the
`mixer, the LNA requires 50 nH load inductors to obtain a peak
`at 1 GHz in its frequency response. From (4) and Fig. 4, this
`means that in the absence of parasitics (Cp = 0), the peak
`RF gain is at most 26 dB.
`
`B. Downconversion Mixer
`The amplified signal at the LNA output is converted down
`in frequency for further amplification, channel-select filtering,
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`884
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7 , JULY 1996
`
`and detection. The frequency mixer is an integral part of the
`RF front-end.
`There are two fundamentally different ways to implement a
`mixer in CMOS. The first, somewhat unconventional method,
`uses a MOSFET as a wideband analog switch. A passive
`track-and-hold circuit, consisting of a 1-pm FET switch and a
`grounded capacitor, is designed for a track-mode bandwidth of
`greater than 1 GHz. This follows the waveform of a modulated
`1 GHz carrier and samples it at a much lower rate, which
`must be at least twice the modulation bandwidth. An op-amp
`feedback circuit clocked at this low sample rate buffers the
`held output, and removes signal-dependent charge injected by
`the switch. When the sample rate is an integer submultiple
`of the carrier frequency, the interpolated samples directly
`downconvert the RF signal to dc. A prototype evaluated at a
`900 MHz RF [2] shows very good linearity, but fundamentally
`suffers from a large noise figure, because while tracking the
`narrowband signal, it also tracks and aliases wideband noise.
`This, and the difficulty of buffering such a switched mixer to
`the inductive load of an integrated LNA, make it inappropriate
`in a sensitive receiver.
`The second, more conventional, mixer resembles the Gilbert
`analog multiplier. It consists of a linear RF voltage-to-current
`(V-I) converter, or RF transconductor, whose output current
`is commutated by the local oscillator (LO). As commutation
`conserves the total current, it downconverts a fraction of
`the RF current to the IF, and the remaining RF current
`upconverts around one or more harmonics of the LO. The
`voltage conversion-gain of the active mixer is independently
`set by choice of the transconductance and load resistance. The
`internal current conversion-loss penalizes mixer noise. as is
`analyzed in a later section.
`A good mixer is highly linear, and its input-referred noise
`does not overwhelm the amplified noise of the preceding LNA.
`The mixer handles larger signals than the LNA, and therefore
`its nonlinearity must be lower by at least a factor of the LNA
`gain if it is not to become the bottleneck to receiver dynamic
`range. This is why the following discussion concentrates on
`mixer nonlinearity, as the LNA, with the choice of bias
`voltages, is not the bottleneck to front-end linearity.
`Third-order intermodulation distortion in a double-balanced
`mixer may cause two large adjacent-channel signals to create
`energy at spurious frequencies coincident with a weak desired
`channel. The linearity of a front-end is specified by the input-
`referred third-order intercept point (IlP3) [ZO]. Often this i s set
`by the static and dynamic nonlinearity in the RF V-I converter
`of the mixer, or by the static nonlinearity in the mixer load.
`Linear MOS transconductance circuits have been studied
`extensively in the context of continuous-time active filters [21]
`operating at frequencies up to tens o f MHz. These circuits
`exploit the property that the dominant second-order nonlin-
`earity in a MOSFET circuit cancels in balanced differential
`inputs and outputs. For instance, if two identical common-
`source FET’s conforming to the classic long-channel I-V
`characteristics are biased at some VGS [Fig. 8(a)] and excited
`differentially by a large signal V;, whose amplitude is less
`
`+:
`
`:4 %lout
`
`+-
`
`IF+ ?
`
`Lo+
`
`f IF-
`
`Lo+
`
`(b)
`Fig. 8.
`(a) Linear MOS transconductor. (b) Downconversion mixer circuit
`diagram.
`than 2 ( V i ~ - q), then the differential output current
`l o u t = Yc;,(w/q(VGs - v,)V,ll
`(8)
`depends linearly on V,,, and the bias V i s - V, sets the
`transconductance [22].
`Residual third-order nonlinearity produces a small distortion
`in the transconductor. Its large signal handling is limited by
`clipping when an input swing of V& - V, turns off one of
`the FET’s in the circuit. These sources of static nonlinearity
`are expected to govern the mixer up to and beyond 1 GHz, as
`no significant nonquasi-static effects are likely to set in given
`the short carrier transit time in the 1-pm channel. Dynamic
`nonlinear currents which grow with frequency will flow in any
`voltage-dependent FET capacitance and might even become
`the significant form of distortion at 1 GHz. The MOSFET,
`however, is benign in this respect, as its main capacitance,
`CGS. is relatively independent of bias for V& > V, and
`behaves like a linear capacitor in the saturation region of
`operation.
`The MOS downconversion mixer is a balanced circuit
`[Fig. 8(b)] comprising a linear common-source FET transcon-
`ductor (ac opposed to a differential pair in the bipolar Gilbert
`multiplier), four commutating FET switches, and a high-swing
`load consisting of a center-tapped FET resistor across pull-up
`current sources. Common-mode feedback from the center tap
`biases the current sources at a well-defined voltage. The LNA
`output is directly connected into the differential mixer input.
`The mixer attains its peak conversion gain when a sinewave
`of at least +5 dBm (1 V ptp) is applied to the commutating
`switches M6-M9. This also lowers the total front-end noise
`figure. While it is obvious that incomplete commutation leads
`to conversion loss, what may not be evident is how it also
`degrades noise figure. The transconductor FET’s and the
`loads clearly contribute noise in the mixer. In addition, the
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`ROFOUGARAN et al.: A 1 GHr CMOS RF FRONT-END IC FOR A DIRECT-CONVERSION WIRELESS RECEIVER
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`-
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`ss5
`
`commutating switch FET’s also contribute noise at discrete
`time intervalls over the switching cycle. The time-varying
`aspects of the circuit must be understood to estimate the
`magnitude of this contribution. Over most of the duty cycle,
`one FET in each switched pair appears as a resistor in series
`with transcoinductor, while its companion FET is OFF. The
`series FET contributes very little noise, determined only by
`the finite output impedance of the transconductor FET’s at
`1 GHz. However, during a zero-crossing of the LO, the two
`companion switch FET’s carry comparable drain currents, and
`act, for the purposes of noise analysis, like a differential pair
`amplifier. They then contribute a short burst of balanced noise
`current to the mixer load with a spectral density proportional to
`the switch FET transconductance, elevating the average mixer
`output noise [23]. A larger LO drive to the mixer forces zero
`crossings with a greater slope, and as the switches now dwell
`for a shorter fraction of the period in the high noise condition,
`the overall mixer noise is lowered.
`It is a good assumption that under large LO drive, the mixer
`commutates the RF transconductance current with a square
`wave. Simple expressions may now be derived for the mixer
`conversion gain and its equivalent input noise. Referring to
`Fig. 8(b), suppose a unit sinusoidal input voltage of frequency
`WRF is linearly converted to a current, and commutated by the
`switches at WLO, which amounts to multiplying the sinusoidal
`current by a square wave, sq(wLot), alternating between $1
`and -1. The current flowing into the loads, I I F , is then
`
`IIF = gTn4 sin W R F t x sqwLot
`
`where the square wave is expanded as a Fourier series, and the
`term containing the downconverted frequency at WRF - WLO
`is retained. ]Equation (9) shows a current conversion loss of
`at least 2 / ~ ( = 0 . 6 4 ) through this mixer. The overall mixer
`voltage gain is
`
`As M4 and MI2 share the same bias current, it follows that
`with the FET sizes used in this circuit
`
`From (1 1) and (12), this means that noise voltage referred at
`the mixer input is 1 . 8 ~ larger than if the input FET’s (M4)
`were the sole source of noise. In the cas? of direct-conversion
`where WIF = 0, flicker noise in the load will further elevate,
`indeed dominate, the mixer input noise.
`The NFET’s at the mixer input are b k e d at VGS -Vt = 0.75
`V, and drain 2.4 mA each from the 3 V supply. From ( l l ) ,
`the referred input noise voltage level clf this mixer is about
`3.5 nV/dHz, which is overwhelmed by LNA output noise of
`roughly 12 nVIdHz due to its own FET’s. We conclude that
`the mixer does not appreciably degrade the noise figure of the
`front-end.
`The V& - V, of the pull-up PFET current sources is also
`0.75 V, and as the signal level at the mixer input is 1 . 4 ~
`at the output, clipping will commence at the transconductor
`input. It may be shown with straightforward calculus that the
`rms value of a sinewave falls by 1 dB when it is clipped
`to 81% of its undistorted amplitude. This predicts that at
`the above bias points, the conversion gain of the front-end
`will compress by 1 dB due to clipping at the mixer input
`when a balanced sinewave of about - 4 dBm is applied to
`the LNA.
`For the purposes of standalone testing, open-drain PFET’s
`connect to the mixer output to drive off-chip loads. They
`require an additional bias current, which is high enough to
`enable them to drive a large power level into the 50 R
`impedance of measuring instruments. Hc wever, in the intended
`on-chip use, they will be radically scaled down in size to drive
`a small capacitive load. The signal from the mixer output
`onwards is at a low or even a zero IF, so considerations
`of noise, not bandwidth, set the pouer dissipation in the
`subsequent stages.
`
`Mixer Gain = (2/7r)gm4RL
`
`(10)
`
`111. IMPLEMENTATION AND MEASUREMENTS
`
`which may be adjusted to any reasonable value by the load re-
`sistance, RL, attached to the low-frequency output node. Noise
`due to the mixer loads is referred to the input in the following
`way: the noise current is divided by the conversion loss; the
`noise spectrum is translated from W I F to W R F ; and the noise
`is distributed equally between two image sidebands around
`WLO which ,will downconvert to the same W I F . ~ Suppose that
`the transconductor and load FET’s (Ml2, M13) [Fig. 8(b)]
`produce only thermal (white) noise, that the commutating
`switch FET’s contribute no noise, and that the noise due to the
`spectral density FET resistor loads (4,410, M11) is negligible.
`Then the noise referred to the mixer input is
`
`’This assumes that the conversion gain is equal from both sidebands, which
`is a very good approximation for low W I T .
`
`A. Layout Issues
`The RF front-end, comprising the LNA and mixer, is laid
`out for fabrication in a standard two-levl:l metal, 1-pm CMOS
`process offered by MOSIS. The two on-chip spiral inductors
`in the LNA dominate the 1.3 x 2 mm active area of the
`die (Fig. 9). There are two features O F note on this layout.
`First, circular via-holes surround the inductors to expose the
`silicon substrate after fabrication and passivation. Second, the
`LNA input pads are unusual. The standard MOSIS pad consists
`of 100-pm squares of Metal 2 and Metal 1 shorted together.
`This pad is, however, unsuitable for RF’ applications, because
`it is capacitively coupled through the oxide to the nonzero
`spreading resistance of the grounded I ilicon substrate. At 1
`GHz, the pad impedance is mainly resistive and about SO f2.
`This parasitic resistance upsets the inpui: impedance matching,
`but more seriously, it is a significant source of thermal noise.
`In fact, due to the pad alone, the LNA noise figure would
`
`ParkerVision Ex. 2027
`IPR2021-00990
`Page 6 of 10
`
`

`

`886
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. I, JULY 1996
`
`25
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`20
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`15
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`10
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`5
`0
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`-5
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`
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`
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`m ;.
`.-
`$
`4
`5
`
`SPICE Simulation
`
`-10
`0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
`Frequency, CHI
`
`(a)
`
`-9
`-10
`- I 1
`-12
`m
`U -
`-13
`E -14
`-
`a n
`E -15
`-16
`
`0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
`Frequency, GHz
`
`(b)
`Fig. 11. Measured characteristics of low-noise amplifier. (a) Gain versus
`frequency, compared with SPICE simulation. (b) Input reflection coefficient
`versus frequency.
`
`B. Experimental Results
`All the following measurements are made with the chip
`mounted in a ceramic microwave package, to which a low-loss,
`power-conserving balun applies a balanced RF stimulus from a
`single-ended signal source. A low frequency power-combiner
`converts the balanced output into a single-ended signal for
`measurement. In most cases, the LO is offset from the RF
`input to produce a 10 MHz IF, which makes it easy to use
`ac-coupled instruments. However, the circuit is also evaluated
`in selected ways as a direct-conversion front-end. The LNA
`frequency response [Fig. 1 l(a)] is deduced from measurements
`on the overall conversion gain, by accounting for the mixer
`gain from transient simulations. SPICE, with standard static
`FET models and a simple three-element inductor model [l],
`predicts the LNA response very well. The scattering parameter
`s11 measures the input reflection coefficient, and thus the
`quality of the LNA input impedance match [Fig. ll(b)]. An
`s l l of - 16 dB at 1 GHz is satisfactory for many applications,
`and implies a net input resistance of about 70 0, consistent
`with the FET gm.
`Another relevan