736
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 30, NO. 7. JULY 1995
`
`A 1.5 GHz Highly Linear
`CMOS Downconversion Mixer
`
`Jan Crols, Student Member, IEEE and Michel S. J. Steyaert, Senior Member, IEEE
`
`Abstract-A CMOS mixer topology for use in highly integrated
`downconversion receivers is presented. The mixing is based on
`the modulation of nMOS transistors in the triode region which
`renders an excellent linearity independent of mismatch. With two
`extra capacitors added to the classical cross-coupled MOSFET •
`C lowpass filter structure, GHz signals can be processed while
`only a low-frequency opamp is required as output amplifier.
`The downconversion mixer has an input bandwidth of 1.5 GHz.
`The measured third-order intercept point (IP3) of 45.2 dBm
`demonstrates the high linearity. The mixer has been implemented
`in a 1.2 µm CMOS process. It takes up 1 mm2 of total chip area
`and its power consumption is 1.3 mW from a single 5 V power
`supply.
`
`l
`
`INTRODUCTION
`
`THE NEED FOR highly integrated receivers in the 1-
`
`2 GHz range has grown considerably with the introduc(cid:173)
`tion of new wireless telecommunication services like digital
`cellular telephone. Key issues in the design of receivers for
`these applications are the quality of the signal reception, the
`level of integration, the power consumption and the cost prize.
`Several realizations of the RF part for these receivers have
`been presented in the past [ 1 ]-[ 4). They are all realized in
`either a GaAs or Si bipolar process. The use of the bipolar
`technology is often prefered over GaAs for its lower cost
`prize and equally good performance in the 1-2 GHz range. A
`further integration, i.e., combining the analog RF, the analog
`LF and the digital part on one chip, will be the next goal.
`The analog LF and the digital part are preferably realized
`in a CMOS technology. Combining these with the RF part
`would require the use of a BiCMOS technology and although
`these technologies are ever more used in telecommunication
`applications, they are not suited for the realization of receivers
`for frequencies above I GHz. The quality of the bipolar
`devices is in todays BiCMOS processes not sufficient. The
`value of their ft and more important of their Tb is not so
`good as what is available in bipolar only processes. At this
`time, using CMOS is the only way to obtain a further and full
`integration. With the ongoing further decreasing of CMOS
`gatelengths this becomes ever more feasible [5]-[8].
`In this paper a full CMOS downconversion mixer is pre(cid:173)
`sented. It is a key building block for the realization of a
`fully integrated CMOS I GHz zero-IF receiver. The presented
`downconversion mixer is not only important for the fact
`that it is implemented in CMOS, its linearity is also much
`better than any bipolar or GaAs realization that has been
`
`Manuscript received December 20, 1994; revised Apnl l 1, 1995.
`The authors are with the Katholieke Universiteil Leuven. ESAT-MICAS.
`Kardinaal Mcrcicrlaan 94, R-3001 Hcvcrlec, Rclgium.
`IEEE Log Numher 9412406.
`
`previously presented. A CMOS I GHz downconversion mixer
`has been proposed before [5], but it was based on the use
`of subsampling. Such a circuit can only cope with smallband
`input signals, resulting in the need for the use of a high-quality
`HF filter which can not be realized in an integrated way. The
`mixer which is presented in this paper.is a true double balanced
`multiplier, capable of downconverting broadband input signals
`by multiplication with a sinusoidal local oscillator.
`The second section of this paper describes the topology of
`the presented downconversion mixer. The topology is based on
`the use of four cross-coupled CMOS transistors operated in the
`triode region and connected to a virtual ground point [6]. Two
`important capacitors of 25 pF have been added to this topology
`on the virtual ground points. With these capacitors it becomes
`possible to realize a very high input bandwidth (as high as
`1.5 GHz) with the use of a low-frequency opamp (IO MHz).
`The third and fourth part of this text describe the design
`aspects. The fifth and sixth part are respectively on the noise
`capabilities of the presented structure and the relationschips
`between linearity, noise and power consumption. The last two
`parts describe the practical realization and the measurement
`results.
`
`II. MIXER TOPOLOGY
`The linearity of an RF mixer is in most cases rather
`limited. The Gilbert topology is the most common used in
`a bipolar technology [9]. Its operation is based on a translin(cid:173)
`ear configuration, i.e., the use of the exponential voltage to
`current conversion of the bipolar transistor. Techniques like
`predistortion and emittor degeneration are necessary to obtain
`a reasonable linearity. Imperfections in this structure combined
`with a limited matching will render a third-order intercept
`point (IP3) which can only be slightly larger than O dBm [10).
`In CMOS a double balanced structure which cancels out the
`quadratic term of the MOS transistor can be used [II], [12].
`These mixer have not only a limited linearity which highly
`depends on matching, even more important is their limited
`frequency range. The input transistors of these mixers can
`only be biased with a relatively small VGs - VT in order
`lo keep them in saturation at all times. The result is large
`input transistors which limits the maximal achievable input
`bandwidth to about I 00 MHz.
`A better solution is to use the transistor, in the linear
`region, preferably with a large Vc;s - Vi. In this way a
`small R011 can be realized with a small tran,i,tor, allowing
`a high input bandwidth. This property has been used to
`realize high frequency GaAs commutating mixers [13]. The
`
`0018-9200/95$04.00 © 199S IEEE
`
`ParkerVision Ex. 2026
`IPR2021-00990
`Page 1 of 7
`
`

`

`CROLS AND STEYAERT: A 1.5 GHz HIGHLY LINEAR CMOS DOWNCONVERSION MIXER
`
`737
`
`c.
`
`Fig. l. The mixer topology with the extra capacitor on the virtual ground nodes.
`
`transistors are being used as pass-transistors and the linearity
`of these mixers does therefore not depend on the voltage
`to current conversion characteristic of the transistors. The
`linearity is mainly determined by the speed limitation of
`the pass-transistor and by the generation of spurious signals
`during switching. This technique can also be used in CMOS.
`The output signal after commutation is however still a high(cid:173)
`frequency signal and it can therefore not be further processed
`in CMOS. However, receivers only require a downconversion
`mixer and this means that the output bandwidth may be
`limited. A solution based on subsampling with a switched(cid:173)
`capacitor structure has been proposed in [5]. The MOS(cid:173)
`transistors are used as pass-transistors and an IP3 of 27 dBm
`has been reported.
`A CMOS mixer with very high linearity can be realized
`by using the linear voltage to current charateristic of the
`MOS transistor in its triode region [6]. The use of a double
`balanced structure cancels out the common-mode de biasing
`signals and the nonlinear dependence of gos on Vos- The
`remaining problem is still the further processing of the high(cid:173)
`frequency output current. This limits in [6] the bandwidth to
`200 MHz at the cost of a high power consumption and a
`reduced linearity of the output stage. The mixer presented in
`this paper is based on this topology (see Fig. 1). There are
`however two very important capacitors added on the virtual
`ground nodes of this topology (the capacitors C,, in Fig. 1).
`Indeed, the output stage, the opamp and the feedback resistors,
`which convert the output current of the mixing transistors back
`into a voltage, must, in a downconversion mixer, only be able
`to produce low-frequency output signals. However, in order
`to let the input structure operate correctly for all frequencies,
`there may not be a signal on the virtual ground nodes of the
`mixer at any time. This is normally done with the feedback
`structure over the opamp which creates the virtual ground at its
`inputs. The transistors in the input structure would operate as
`pass-transistor for high-frequency signals when the frequency
`capability of the opamp would not be high enough. Therefore
`the capacitors C,, have been added. They make sure that all
`
`high-frequency currents injected to the virtual ground nodes
`are filtered out and not converted into voltages. The opamp
`still generates the virtual ground for )ow-frequencies. By using
`this structure, it becomes possible to split the design of the
`input structure and the opamp. The input structure can now be
`optimized for operation at very high frequencies (more than
`l GHz), while the opamp can be designed for low-frequency
`operation (a few MHz).
`With a perfect virtual ground the currents through the
`modulated transistors are
`
`( +
`Ins,1 = {Ji · VRF - Vi,o,nc - Vrnl -
`
`V1"t- V10.oc)
`2
`
`· (VLt - V10,nc)
`Ios,2 = /32 · ( VitF - Vw,nc
`
`V
`Tn,2 -
`
`VLo - V10,oc)
`2
`
`· (VLO - Vw,oc)
`( +
`Ios,3 = /33 · VRF - V10,DC - VTn,3 -
`
`. (VLO - VLO,DC)
`
`Ios,4 = /34 · VRF - VLO,DC - VTn,4 -
`
`~
`
`(
`
`V10 - Vw oc)
`'
`2
`
`V,+ -
`LO
`
`\/Lo DC)
`'
`2
`
`· (vL+o - Vw,nc)-
`
`(l)
`
`The bulk effect gives in first order a linear change around
`the bias point which is cancelled with the double balanced
`structure [6]. Assuming perfect matching and no bulk-effect,
`the output signal is then
`v~t,. - V,;;;,. = R1 · ((Ii - /4) - (/:i - I2))
`=/3 · R1 · (vitF - ViF) · W1t- vi:;-i)-
`
`(2)
`
`Mismatch between the input transistors has two effects. f3
`and VT mismatches both result in the appearance of residual
`de-offset voltages. These offset voltages either appear directly
`on the ontput of the mixer or they result in direct feedthrough
`of the RF and LO signal to the output caused by multiplication
`
`ParkerVision Ex. 2026
`IPR2021-00990
`Page 2 of 7
`
`

`

`738
`
`IEEE JOURNAL OF SOUD-STATE CrRCUITS, VOL. 30, NO. 7, JULY 1995
`
`quadratic components in the voltage to current conversion
`characteristic of the modulated transistors are cancelled out
`[9], [10]. The LO de level is taken to be 1.15 V, making the
`maximal LO signal that can be applied 4.6 V ptp differential
`(i.e., 17.2 dBm). An RF de level of 3.85 V allows an input
`signal of 4 times VRF,DC - VLo.Dc - Vr, which gives 8 V ptp
`differential or 22.0 dBm for the 1.2 Jtm CMOS process which
`has been used for the mixer which is presented here. These
`are very high values for an RF mixer, resulting in a topology
`which renders an excellent linearity. Saturation will occur
`when VRF + VLo > 8 V ptp· The applied LO signal is for this
`reason limited to 2.5 V ptp, so that an RF signal of 5.5 V ptp
`still can be applied without driving any of the modulated
`transistors into its saturation region.
`
`IV. FREQUENCY DOMAIN BEHAVIOR
`The well known negative feedback configuration of Fig. 2
`suppresses any signal at the virtual ground node when a perfect
`opamp is used. An opamp has however always a limited
`gain-bandwidth GBW and de-gain A 0 . With a limited GBW
`becomes the transfer function from the input to the virtual
`ground (Ao, C1, and C,, are not taken into account)
`
`Rt _ w
`A.
`w
`. J 21r . GBW
`R;n . J 21r · GBW
`- - - - ' "~ - - - - - - - ~ --~~~~~-
`R1 + R;n
`1 + A
`.
`w
`w
`.
`1 + ~--- · J - - - -
`. .J 21r · GBW
`21r · GBW
`R;n
`(4)
`
`The transfer function from the input to the output is
`
`- R1
`-A
`R
`--~-~___,·i=n ____ ~ - - - - -~ - -
`Rj + R;n
`.
`w
`w
`.
`1 + ~ - - · J
`l +A. J 211" · GBW
`,
`21r · GB\\
`R;u
`
`(5)
`
`Normally, the conclusion to be drawn from these equations
`is that the GBW must be a certain factor higher than the
`highest frequency component that has to be processed. This
`is also true if the circuit would be used as lowpass filter with
`an extra capacitor Cf in the feedback loop. However, here
`in the mixer topology is the situation different. There is a
`very large spectrum of input currents to the virtual ground
`node, basically starting from de up to twice the LO frequency
`(more than 2 GHz), but the wanted signal takes up only a few
`hundred kHz situated at the baseband. The output bandwith
`BW, given in (5) as GBW /A, only has to be 500 kHz or
`more. By designing it to he I MHz this specification is fullillcd
`independent of absolute parameter variations. Equation (5)
`shows that this limited bandwidth can be realized by using
`an opamp with a small GBW. In cPmbination with a feedback
`capacitor C.r can the bandwidth he lowered further and c.111 it
`be positioned more accurately. The use of an opamp with a
`small GBW poses however a problem. As (4) rctlects. beyond
`the BW is the input signal directly transferred to the virtual
`ground node. It is not suppressed anymore by the opamp via
`the feedback con.struction. The solution for this problem can
`
`Fig. 2. The negative feedback configuration.
`
`(3)
`
`of these signals with the offset voltage. The RF and LO signal
`are however high-frequency signals. They will therefore be
`strongly suppressed by the added capacitors Cv. The second
`effect, caused by /3 mismatch, is the appearance of a quadratic
`Vu) component in the output signal.
`V,;;;t - V,;;;t = (J · R1 · (VtF - ViF)(VLri - VL-o)
`+ b../i · R1 · (V1t - V1ol 2 ·
`This explains why the RF signal is best applied to the gates
`of the modulating transistors. A quadratic VRF component
`would be highly unwanted. The squared RF signal has fre(cid:173)
`quency components at twice its center frequency and at the
`baseband. The high-frequency components are filtered out, but
`the baseband components will degrade the wanted baseband
`signal. The bandwidth of this parasitic baseband signal is equal
`to the bandwidth of the RF signal (e.g., 100 MHz), but most of
`its power will be situated at the lower frequencies, in a band
`equal to the correlation bandwidth of the RF signal, which is
`about equal to the bandwidth of a transmission channel (e.g.,
`200 kHz). The squared LO signal results only in an extra de
`component at the output of the opamp. This de signal can
`also be a problem. It can be as large as the wanted signal and
`in that case it will saturate the succeeding filters. There are
`however techniques available to suppres the de component
`without generating to much distortion. One of them is the
`use of a DSP which measures the de component and then
`suppresses it, using a dynamic and nonlinear algoritm I 14].
`
`III. MIXER DESIGN
`
`The de biasing levels of the RF and LO signal must be
`chosen carefully. There will be a lot of distortion when the
`modulating lransi,tnrs are not kept in the triode region at all
`times. The smallest possible level that can appear at the gates
`(i.e., ViiF,nc - Vin·,,,.c) must be at least a V1 higher than
`the largest possihle source level (i.e., \io,nc). O!herwise the
`transistors will be turned off during a mixing period. Saturation
`of the modulated transistors will appear when the largest drain(cid:173)
`source voltage Vi::>s (i.e., Vi.o AC) becomes higher than the
`smallest lc;s Vy (i.e .. Vii.r.Dc -- VRF .. \c
`\io.Dc Vy).
`However, saturation does not directly result in distortion. The
`cross-coupled double balanced structure makes sure that all
`
`ParkerVision Ex. 2026
`IPR2021-00990
`Page 3 of 7
`
`

`

`CROLS AND STEYAERT: A 1.5 GHz HIGHLY LINEAR CMOS DOWNCONVERSION MIXER
`
`739
`
`Gain (log)
`
`A
`
`0
`
`NA-''+-----___,
`
`defined as the ratio of the output signal over the input signal
`<Va"tt - Vo~t/ViiF - ViF) and follows from (2):
`
`G = (Va~t - v,;;;t)ptp
`(Viti,. - ViF)rtr
`+
`1
`1
`= ,12 · ../2 ·fl· R1 · (Vw
`
`v1.olrtp•
`
`(7)
`
`The first ../2 appears because the multiplication is performed
`with a sine and not a square wave. This implies that the rms
`value of the LO signal has to be used. The second ,./2 is
`necessary because only the low-frequency mixing product is
`regarded as wanted. Deviding (6) by (7) results in
`
`l/(21tR.,C ,) 1/(211 R, Cr)
`
`Freq
`
`Fig. 3. Transfer function of the mixer used as amplifier.
`
`be found in adding extra capacitance to the virtual ground
`nodes. This introduces an extra pole in both (4) and (5) situated
`at 1/(21r · R;nCv)- In order to suppres the signals appearing
`on the virtual ground without changing the output bandwidth,
`its value must be positioned between 1/(21r · R1C1) and the
`BW. Fig. 3 displays the transfer function from the input to the
`virtual ground and the output.
`
`V. NOISE, PoWER CONSUMPTION, AND OPTIMIZATION
`The noise figure (NF) of the HF mixer is a very important
`parameter in receiver design. In a receiver is the mixer
`positioned directly after the LNA and a mixer with a high
`NF can only be used in combination with a high-quality LNA.
`In this case the LNA must have a high gain which, in tum, can
`only be allowed when the antenna signal is first filtered with a
`high Q HF filter. The problem with mixers is that its NF can
`not be made arbritrarely small. Their NF can not even be in
`the proximity of the NF's that can be achieved with LNA's.
`This is due to the intrinsic nature of the mixing process.
`The two main noise sources in the presented mixer are
`the modulated input transistors in the triode region and the
`input stage of the LF opamp. The thermal output noise density
`generated by these devices is (with the factor 2 introduced by
`the differential operation)
`
`2
`
`9m,m,eq
`
`(2 1
`dvout = 2 · 4kT- 3 · --. -
`· (R1 · 2gos)
`2
`+ 2gos · RJ) · df.
`
`(6)
`
`Equation (6) gives the output noise density for the mixer
`biased in its static operation point. The modulated transistors
`have however, under transient conditions, always the same
`impedance (2g08) to the virtual ground nodes. For this reason
`is (6), for the presented topology, also a good measure for
`the output noise density under transient operation conditions.
`The equivalent input noise can be found by deviding this
`expression by the conversion gain G. The conversion gain is
`
`=8kT.
`
`(
`
`4gos
`)
`f3 • (Vr:o - VLo)ptp
`( 2
`1
`1 )
`· - · - -+ - -df
`3 9m,in,eq
`2gos
`:=8kT. (2. 2gos )2. (~. _1_ + _1_) • df.
`
`2
`1
`2
`2
`(
`a (V,+
`dvin = G2 · dvout = R
`I . /J '
`LO -
`2
`
`)
`
`v,- )
`LO ptp
`
`2
`
`2
`· dvout
`
`Agos
`
`3 9m,in,eq
`
`2gos
`
`(8)
`
`The factor 4gos/ Ag03 is the extra term intrinsic to any
`mixer or double balanced structure. It is equal to the ratio
`between the gain of the mixer used as single balanced amplifier
`and the conversion gain A/G. For low noise, this term should
`be as low as possible. The noise can also be lowered by using
`a larger Ym,in,eq and g08 , but this is at the expense of a higher
`power consumption. The minimal value for this extra term is
`found when the swing of the LO signal is maximal.
`~ = 2 . 2gos = 4 · /3 · (Vcs - VT)
`f3. (VL+O - VLo)ptp
`G
`A.gos
`= 4 . VaF,DC - V1.o,oc - Vr
`(vL+o - vLo)ptp
`= 4 · (VaF,DC - Vw,oc - VT)
`2 · VLo,oc
`= 4 · (VaF,oc - VLO,oc - ~T) = 2 _
`2 · (VaF,DC - V1.o,oc -
`\-r)
`
`(9)
`
`(10)
`
`(~)
`G min,RF@gates
`( ~)
`G min,LO@gates
`
`(11)
`
`So, according to (11) for the case in which the LO signal is
`applied to the gates of the modulated transistors, this means
`that the mixing function adds at least 6 dB to the NF. For
`the rest is the NF directly determined by the conductivity of a
`single modulated transistor (gos) and by the transconductance
`value of the opamp input stage (gm,in,eq), just like in any
`other amplifier with negative feedback. The noise of the opamp
`input stage can be made sufficiently small without requiring
`toq much power by using large input transistors (and a small
`Vcs - Vr ). This is possible because the opamp only has to be
`LF and there is already standing 25 pF (Cv) at the input nodes.
`The value of gos can not be made arbitrarely large because
`this conductor has to be driven by the LO.
`
`ParkerVision Ex. 2026
`IPR2021-00990
`Page 4 of 7
`
`

`

`740
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30. NO. 7, JULY 1995
`
`From (10) it might seem that the NF can be made arbitrarely
`small when the RF signal is applied to the gates by taking
`VRF,DC - VT< 2 · VLo,DC• This implies however a reduction
`of the input swing and in this way the dynamic range (DR) at
`the input is not improved. It is not only necessary to minimize
`the NF of a mixer. It is the input signal capability (i.e., the
`DR) which must be compared with the power consumption.
`A good measure for the performance of a mixer is therefore
`the DR per Watt. Here this gives
`
`(D:) RF@gates = (! r !
`
`-BW
`
`(VRF,DC - VLQ,DC - VT )2
`= BkT- (~) 2
`• - 1-
`2gos
`G
`1
`(VLci - VLo)2 · 9DS
`1
`16-4kT-BW
`
`(12)
`
`Equation (12) takes does not take the power consumption
`and the noise of the opamp into account. Only a low-frequency
`opamp is needed and its power consumption and noise can
`therefore be made sufficiently small. 4kT- BW is the intrinsic
`noise power of a signal with bandwidth BW and the noise
`of any electronic buiding block with input bandwidth BW
`can thus never be lower than this value. The factor 1/16 can
`herefore be defined as the power efficiency for this mixer.
`It is independant of the choosen input swing, noise level,
`input bandwidth, or power consumption. In fact, this power
`efficiency depends, for the presented topology and in first
`order, only on the topology itself and it can be defined for
`many other building blocks likes LNA's, amplifiers, filters,
`AID converters and any other type of mixer.
`
`Sfuput Pintrinsic noise
`TJ=--·
`2
`Nin put
`Ptotal
`
`]
`.
`.
`[ V 2
`4kT
`Watt · V 2 /Hz = d1mens1onless .
`
`(13)
`
`The power efficiency of a high-quality low-frequency ampli(cid:173)
`fier can be almost 50%. The power efficiency of the presented
`mixer topology, not taking the power efficiency of the LO
`signal source into account, is almost 6% and this is, for
`high-frequency mixers, a very high value.
`Equation ( 12) is slightly different when the LO signal
`instead of the RF signal is applied to the gates of the modulated
`transistors
`
`S I
`(DR)
`Vea oc
`p
`LO@gates = N. p 8kT. (~)2 • _ _ 1_. BW
`2gos
`G
`
`1
`4 · Vlo,oc · 9os ·
`
`(14)
`
`And only when A/G is minimal this reduces to
`
`(D:) LO@gates
`
`1
`16·4kT-BW'
`
`(15)
`
`The main difference is that in this case the efficiency of 6%
`is only obtained with the maximal LO signal. The efficiency of
`6% is in the situation of (12) always obtained, independant of
`the amplitude of the LO signal. This is caused by the fact that,
`when the LO signal is applied to the sources of the modulated
`transistors, a lower conversion gain is compensated by a lower
`power consumption for the LO signal source. This is another
`reason why the topology with the RF signal applied to the
`gates is preferred over the topology in which the LO signal is
`applied to the gates of the modulated transistors.
`
`VI. REALIZATION
`The mixer has been designed and realized in a 1.2 µm
`CMOS process to illustrate the high linearity and high input
`frequency capabilities of the proposed topology. The RF and
`LO signal are externally made differential by means of baluns.
`They are, as stated in Section III, chosen to be biased at,
`respectively, 3.85 V (for the RF signal, applied at the gates)
`and 1. 15 V (for the LO signal, applied at the sources and
`drains) because this renders a VGs - VT for the modulated
`transistors of 2.5 V. Such a large value for the VGs - VT
`results in an excellent linearity and a high input bandwidth.
`The applicable voltage swing for the RF input is peak-to-peak
`four times this VGs - VT. The large Vas - Vi makes it also
`possible to realize a large 9DS with a small transistor, which
`gives small parasitic capacitances (less than 20 tF) and thus a
`high input bandwidth. The W / L of the modulated transistors
`is 6, their gos is 1 mS. These four modulated transistors are
`the only high frequency part on the chip and they take up
`very little area. Because of their small parasitic capacitances
`is the on-chip RF to LO crosstalk, which is mainly determined
`by the absolute mismatch between CGs values, also very
`small. Hence, RF to LO crosstalk is mainly caused by off(cid:173)
`chip crosstalk and crosstalk between the bonding wires. The
`input bandwidth is also completely determined by the bonding
`pads capacitances and as a result extremely high frequency
`performances can be achieved.
`The opamp topology is shown in Fig. 4. It is a load
`compensated folded cascode structure succeeded by a source
`follower which performs buffering and level shifting. The
`opamp runs on a single 5 V power supply. The output de
`level is l.15 V. It is kept on this level with a standard type
`common-mode feedback. The GBW of the opamp is 100 MHz,
`but because of the partial feedback the second nondominant
`pole is situated at only 30 MHz. The feedback resistors over
`the opamp are 60 kn, which makes the conversion gain very
`high. The conversion gain is almost 20 dB for a 12 dBm
`LO signal. An extra lowpass filter of I MHz is implemented
`with the feedback capacitors C1 (2.5 pF). This small output
`bandwidth and the high conversion gain are required by the
`zero-IF structure. The extra filtering and amplification that
`is performed in the output stage of the mixer relaxes the
`
`ParkerVision Ex. 2026
`IPR2021-00990
`Page 5 of 7
`
`

`

`CROLS AND STEYAERT: A 1.5 GHz HIGHLY LINEAR CMOS DOWNCONVERSION MIXER
`
`741
`
`Fig. 4. The opamp topology.
`
`80
`
`60 c-
`
`40 ~
`
`t
`20 ;:. ◊-
`
`e
`m
`~
`iii
`C
`al
`iii
`:i a.
`:i -20
`0
`
`0 r
`
`·40
`
`-60 ..
`0
`
`,,.-o
`o·
`
`◊-◊
`
`1
`
`d
`
`(>
`
`◊ ~;,
`
`-~ - _..L-.J........._ .............
`
`j__,.(
`
`10
`40
`30
`20
`Input Signal (dBm]
`
`50
`
`ii
`~ -2 ~
`- 4 ~
`iii
`:, 5 -6 ~-
`
`0
`
`• 8 ~
`
`-10 -
`100
`
`'·-'-·----'-~--'~'I -
`
`1000
`Freq [MHz]
`
`Fig. 5. The input bandwidth measurement.
`
`specifications for the output stage of the opamp and for the
`succeeding stages of the reciever.
`
`Fig. 6. The IP3 measurement.
`
`VII. RESULTS
`
`The realized mixer is measured via external high fre(cid:173)
`quency baluns for both the RF and LO input. These baluns
`are transformers which convert a 50 !! signal source into
`two symmetrical 100 !! signals sources superimposed on a
`common-mode de bias voltage. Fig. 5 shows the measured
`input bandwidth. It is from de to 1.5 GHz. The input bandwidth
`is measured at 6 dB attenuation, because both input signals are
`falling off at the same time. The measured 1.5 GHz maximum
`input bandwidth is equal to the specified bandwidth of the
`baluns which have been used to generate the differential input
`signals. The output bandwidth is determined by the untuned
`value of 1 /Rf Cf. For the application in mind it must be at
`least 500 kHz and it is designed to be I MHz so that it can cope
`with the large absolute processing value spreads. The measured
`output bandwidth is 780 kHz. The measured conversion gain
`is 18 dB for a 12 dBm differential LO signal.
`The IP3 measurement, shown in Fig. 6, proves that the
`linearity is very high. The IP3 is 45.2 dBm. This value does not
`depend on the magnitude of the LO signal. An input signal of
`
`22 dBm, the theoretic value for the maximal applicable input
`swing, gives an IM3 of -46.4 dB. The IM3 measurement
`was performed with the downconverted carriers lying out of
`the output band (at 10 MHz) and the IM3 product lying in
`the passband (at 200 kHz). This made it possible to measure
`the distortion of the input stage and not the output stage for
`signals which would normally produce an output signal of
`up to 40 dBm. The measured noise figure (NF, compared to
`a 50 n noise source) is 32 dB. This is mainly caused by the
`input stage of the opamp which has not been optimized for low
`noise. By using large input transistors for the low-frequency
`opamp, which has no effect on the high frequency performance
`of the mixer, the noise figure can easily be improved down to
`24 dB. The intermodulation free dynamic range (IMFDR3) of
`this mixer is 59.6 dB. The mixer is designed in a 1.2 µm
`CMOS process. The measured power consumption is 1.3 mW
`which is all taken up in the low-frequency opamp. The total
`chip area is I mm2 • The modulated transistors only take up
`300 µm2 of this area. A microphotograph of the realized chip
`is shown in Fig. 7.
`
`ParkerVision Ex. 2026
`IPR2021-00990
`Page 6 of 7
`
`

`

`742
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 7, JULY 1995
`
`[5] P. Y. Chan, A. Rofougaran, K. A. Ahmed, and A. A. Abidi, "A
`highly linear I-GHz CMOS downconversion mixer," in Proc. ESSCIRC,
`Sevilla, Sept. 1993, pp. 210-213.
`[6] B.-S. Song, "CMOS RF circuits for data communications applications,"
`IEEE J. Solid-State Circuits, vol. SC-21, no. 2, pp. 310-317, Apr. 1986.
`[7] R. G. Meyer, "Intermodulation in high-frequency bipolar transistor
`integrated-circuit mixers," IEEE J. Solid-State Circuits, vol. SC-21, no.
`4, pp. 534-537, Aug. 1986.
`[8] J. N. Babanezhad and G. C. Ternes, "A 20-V four quadrant CMOS
`analog multiplier," IEEE J. So/id-State Circuits, vol. SC-20, no. 6, pp.
`1158-1168, Dec. 1985.
`[9] H. Song and C. Kim, "A MOS four-quadrant analog multiplier using
`simple two-input squaring circuits with source followers," IEEE J.
`Solid-State Circuits, vol. 25, pp. 841-848, June 1990.
`[10] K. Kanazawa et al., "A GaAs double-balanced dual-gate FET mixer IC
`for UHF receiver front-end applications," in IEEE MIT Int. Microwave
`Symp. Dig., 1985, pp. 60--62.
`[11] D. Rabaey and J. Sevenhans, ''The challenges for analog circuit design
`in mobile radio VLSI chips," in Proc. AACD Workshop, Leuven, Mar.
`1993, vol. 2, pp. 225-236.
`
`Jan Crols (SM'90) was born in Turnhout, Belgium,
`in 1969. He received the M.Sc. degree in electri(cid:173)
`cal and mechanical engineering in 1992 from the
`Katholieke Universiteit Leuven, Belgium.
`He is currently a Research Assistant at the ESAT(cid:173)
`MICAS laboratories of the Katholieke Universiteit
`Leuven. He is working toward, the Ph.D. degree
`on the design of high-performance highly integrated
`receivers in CMOS technologies. For this work he
`obtained a fellowship of the Flemish Institute for
`Promotion of Scientific-Technological Research in
`Industry (IWT). His research interests are in high-frequency analog integrated
`circuits for telecommunication.
`
`Michel S. J, Steyaert (S'85-A'89--SM'92) was
`born in Aalst, Belgium, in 1959. He received the
`Master's degree in electrical-mechanical engineer(cid:173)
`ing and the Ph.D. degree in electronics from the
`Katholieke Universiteit Leuven (K. U. Leuven),
`Heverlee. Belgium in 1983 and I 987, respectively.
`From 1983-1986, he obtained the IWNOL fel(cid:173)
`lowship (Belgian National Foundation for Industrial
`Research) which allowed him to be with the Labora(cid:173)
`tory ESAT at K. U. Leuven as a Research Assistant.
`In 1987 he was responsible for several industrial
`projects in the field of analog micropower circuits at the Laboratory ESAT
`as an IWONL Project Researcher. In 1988 he was a Visiting Assistant
`Professor at the University of California, Los Angeles. In 1989 he was
`appointed as a NFWO Research Associate and since 1992 a NFWO Senior
`Research Associate at the Laboratory ESAT, K. U. Leuven, where he
`has been an Associate Professor since 1990. His current research interests
`are in high-performance and high-frequency analog integrated circuits for
`telecommunication systems and analog signal processing.
`Dr. Steyaert received the 1990 European Solid-State Circuits Conference
`Best Paper Award, and the 1991 NFWO Alcatel-Bell-Telephone award for
`innovative work in integrated circuits for telecommunicahons.
`
`Fig. 7. Chip mkrophotograph.
`
`VIII. CONCLUSIONS
`In this paper it is shown how the low resistance of small
`MOS transistors in the triode area can be used to design
`a high frequency downconversion mixer. A continuous-time
`multiplier has been presented for use in zero-IF receivers. The
`large Vcs - Vr of the triode transistors makes a low noise
`mixer with a high input bandwidth possible. The measured
`input bandwidth is more than 1.5 GHz. Its structure is based on
`the cross-coupled triode-MOSFET-C filter structure. The high
`frequency performances have been achieved due to the intro(cid:173)
`duction of two extra capacitors placed at the virtual ground
`nodes. These capacitors reduce the opamp specifications to
`low frequency CMOS performances. In this paper it has been
`shown how the cross-coupled triode MOS-transistors render
`a very high linearity which is independent of mismatch. The
`measured IP3 is 45.2 dBm differential. This very high value
`for GHz downconversion mixers has been achieved due to the
`use of triode transistors in combination with the introduced
`virtual ground capacitors.
`
`REFERENCES
`
`[I] J. Sevenhans, A. Vanwelsenaers, J. Wenin, and J. Baro, "An integrated
`Si bipolar transceiver for a zero IF 900 MHz GSM digital mobile radio