Oversampling Delta-Sigma
`Data Converters
`Theory, Design, and Simulation
`
`Edited by
`James C. Candy
`AT&T Bell Laboratories
`
`Gabor C. Ternes
`Oregon State University
`
`IEEE Circuits and Systems Society, Sponsor
`
`+IEEE
`
`The Institute of Electrical and Electronics Engineers, lnc.,NewYork
`
`roWILEY(cid:173)
`~INTERSCIENCE
`
`A JOHN WILEY & SONS, INC., PUBLICATION
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 1 of 12
`
`

`

`IEEE PRESS
`445 Hoes Lane, PO Box 1331
`Piscataway, NJ 08855-1331
`
`1991 Editorial Board
`Leonard Shaw, Editor in Chief
`William C. Guyker, Editor, Selected Reprint Series
`
`J. E. Brittain
`S. H. Charap
`R. C. Dorf
`J. J. Farrell III
`L. J. Greenstein
`J. D. Irwin
`
`W. K. Jenkins
`S. Luryi
`E. K. Miller
`J. G. Nagle
`J. D. Ryder
`A. C. Schell
`
`M. Simaan
`M. I. Skolnik
`G. S. Smith
`Y. Sunahara
`R. Welchel
`J. W. Woods
`
`Dudley R. Kay, Executive Editor
`Carrie Briggs, Administrative Assistant
`
`Karen G. Miller, Assistant Editor
`
`Circuits and Systems Society
`Randall L. Geiger, President
`
`© 1992 by
`THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC.
`345 East 47th Street, New York, NY 10017-2394
`
`ISBN 0-7803-31045-4
`Wiley-interscience-IEEE-Press
`Requests to the Publisher for permission should be addressed to the Permissions Department, John
`Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, e(cid:173)
`mail: permcoordinator@wiley.com. All rights reserved. For general information on our other
`products and services please contact our Customer Care Department within the U.S. at 877-762...
`2974, outside the U.S. at 317-572-3993 or fax 317-572-4002.
`
`Library of Congress Cataloging-in-Publication Data
`
`Oversampling delta-sigma data converters : theory, design, and
`simulation / edited by James C. Candy, Gabor C. Ternes.
`p.
`em.
`"IEEE Circuits and Systems Society, sponsor."
`Reprints of articles from various IEEE publications, 1962-1990.
`"A selected reprint volume. "
`Includes bibliographical references and index.
`ISBN 0-87942-285-8 :
`2. Digital-to-analog converters.
`1. Analog-to-digital converters.
`1. Candy, James C.
`II. Ternes, Gabor, C.,
`3. Pulse code modulation.
`TK7887.6.09
`1992
`621.39 '814-dc20
`
`91-19110
`CIP
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 2 of 12
`
`

`

`Preface
`
`Introduction
`Oversampling Methods for AID and DIA Conversion
`J. C. Candy and G. C. Ternes
`
`Part 1: Basic Theory and Analysis
`
`An Analysis of Nonlinear Behavior in Delta-Sigma Modulators
`S. H. Ardalan and J. J. Paulos
`IEEE Transactions on Circuits andSystems, June 1987
`
`A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters
`J. C. Candy
`IEEE Transactions on Communications, March 1974
`
`The Structure of Quantization Noise from Sigma-Delta Modulation
`J. C. Candy and O. J. Benjamin
`IEEE Transactions on Communications, September 1981
`
`Multistage Sigma-Delta Modulation
`W. Chou, P. W. Wong, and R. M. Gray
`IEEE Transactions on Information Theory, July 1989
`
`Oversampled Sigma-Delta Modulation
`R. M. Gray
`IEEE Transactions on Communication, May 1987
`
`Quantization Noise Spectra
`R. M. Gray
`Transactions on Information Theory, November 1990
`
`Double-Loop Sigma-Delta Modulation with dc Input
`N. He, F. Kuhlmann, and A. Buzo
`IEEE Transactions on Communication, April 1990
`
`A Unity Bit Coding Method by Negative Feedback
`H. Inose and Y. Yasuda
`Proceedings of the IEEE, November 1963
`
`Design of Stable High Order I-Bit Sigma-Delta Modulators
`T. Ritoniemi, T. Karema, and H. Tenhunen
`IEEE Proceedings of the International Symposium on Circuits and Systems'90, May 1990
`
`Reduction of Quantizing Noise by Use of Feedback
`H. A. Spang III and P. M. Schultheiss
`IRE Transactions on Communications Systems, December 1962
`
`Oversampled, Linear Predictive and Noise-Shaping Coders of Order N> 1
`S. K. Tewksbury and R. W. Hallock
`IEEE Transactions on Circuits and Systems, July 1978
`
`iii
`
`Contents
`
`IX
`
`Xl
`
`33
`
`44
`
`52
`
`60
`
`73
`
`81
`
`106
`
`115
`
`127
`
`131
`
`139
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 3 of 12
`
`

`

`CONTENTS
`
`Part 2: Design, Simulation Techniques, and Architectures for Oversampling
`Converters
`
`Design Methodology for LdM
`B. P. Agrawal and K. Shenoi
`IEEE Transactions on Communication, March 1983
`
`Table-Based Simulation of Delta-Sigma Modulators
`R. J. Bishop, J. J. Paulos, M. B. Steer, and S. H. Ardalan
`IEEE Transactions on Circuits and Systems, March 1990
`
`Simulating and Testing Oversampled Analog-to-Digital Converters
`B. E. Boser, K.-P. Karrnann, H. Martin, and B. A. Wooley
`IEEE Transactions on Computer-Aided Design, June 1988
`
`A Use of Double Integration in Sigma Delta Modulation
`J. C. Candy
`IEEE Transactions on Communication, March 1985
`
`An Oversampling Analog-to-Digital Converter Topology for High-Resolution Signal
`Acquisition Systems
`L. R. Carley
`IEEE Transactions on Circuits and Systems, January 1987
`
`Digitally Corrected Multi-Bit ~~ Data Converters
`T. Cataltepe, A. R. Kramer, L. E. Larson, G. C. Ternes, and R. H. Walden
`IEEE Proceedings of the International Symposium on Circuits and Systems'89, May 1989
`
`A Higher Order Topology for Interpolative Modulators for Oversampling AID Converters
`K. C.-H. Chao, S. Nadeem, W. L. Lee, and C. G. Sodini
`IEEE Transactions on Circuits and Systems, March 1990
`
`One Bit Higher Order Sigma-Delta AID Converters
`P. F. Ferguson Jr., A. Ganesan, and R. W. Adams
`IEEE Proceedings of the International Symposium on Circuits and Systems'90, May 1990
`
`Optimization of a Sigma-Delta Modulator by the Use of a Slow ADC
`A. Gosslau and A. Gottwald
`IEEE Proceedings of the International Symposium on Circuits and Systems'Bs, June 1988
`
`Circuit and Technology Considerations for MOS Delta-Sigma AID Converters
`M. W. Hauser and R. W. Brodersen
`IEEE Proceedings of the International Symposium on Circuits and Systems'Bti. May 1986
`
`Technology Scaling and Performance Limitations in Delta-Sigma Analog-Digital
`Converters
`M. W. Hauser
`IEEE Proceedings of the International Symposium on Circuits and Systems'90, May 1990
`
`Delta-Sigma AIDs with Reduced Sensitivity to Op Amp Noise and Gain
`P. J. Hurst and R. A. Levinson
`IEEE Proceedings of the International Symposium on Circuits and Systems'89, May 1989
`
`Multibit Oversampled ~-d AID Converter with Digital Error Correction
`L. E. Larson, T. Cataltepe, and G. C. Ternes
`Electronics Letters, August 1988
`
`An Improved Sigma-Delta Modulator Architecture
`T. C. Leslie and B. Singh
`IEEE Proceedings of the International Symposium on Circuits and Systems'90, May 1990
`
`A 13 Bit ISDN-Band Oversampled ADC Using Two-Stage Third Order Noise Shaping
`L. Longo and M. Copeland
`IEEE Proceedings of the Custom Integrated Circuits Conference, January 1988
`iv
`
`153
`
`163
`
`168
`
`174
`
`184
`
`192
`
`196
`
`206
`
`209
`
`213
`
`219
`
`223
`
`227
`
`229
`
`233
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 4 of 12
`
`

`

`CONTENTS
`
`A 16-Bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise
`Shaping
`Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome
`IEEE Journal of Solid-State Circuits, December 1987
`
`Improved Signal-to-Noise Ratio Using Tri-Level Delta-Sigma Modulation
`J. J. Paulos, G. T. Brauns, M. B. Steer, and S. H. Ardalan
`IEEE Proceedings of the International Symposium on Circuits and Systems'87, May 1987
`
`A Second-Order High-Resolution Incremental AID Converter with Offset and Charge
`Injection Compensation
`J. Robert and P. Deval
`IEEE Journal of Solid-State Circuits, June 1988
`
`Improved Double Integration Delta-Sigma Modulations for A to D and D to A Conversion
`Y. Shoji and T. Suzuki
`IEEE Proceedings of the International Symposium on Circuits and Systems'87, May 1987
`
`Oversampling A-to-D and D-to-A Converters with Multistage Noise Shaping Modulators
`K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata
`IEEE Transactions on Acoustics, Speech, and Signal Processing, December 1988
`
`Architectures for High-Order Multibit L~ Modulators
`R. H. Walden, T. Cataltepe, and G. C. Ternes
`IEEE Proceedings of the International Symposium on Circuits and Systems'90, May 1990
`
`Constraints Analysis for Oversampling A-to-D Converter Structures on VLSI
`Implementation
`A. Yukawa
`IEEE Proceedings of the International Symposium on Circuits and Systems'87, May 1987
`
`Part 3: Implementations and Applications of Oversampling AID Converters
`Design and Implementation of an Audio 18-bit Analog-to-Digital Converter Using
`Oversampling .Techniques
`R. W. Adams
`Journal of the Audio Engineering Society, March 1986
`
`The Design of Sigma-Delta Modulation Analog-to-Digital Converters
`B. E. Boser and B. A. Wooley
`IEEE Journal of Solid-State Circuits, December 1988
`A Noise-Shaping Coder Topology for 15+ Bit Converters
`L. R. Carley
`IEEE Journal of Solid-State Circuits, April 1989
`
`A Dual-Channel Voice-Band PCM Codec Using };~ Modulation Technique
`V. Friedman, D. M. Brinthaupt, D.-P. Chen, T. W. Deppa, J. P. Elward, Jr., E. M. Fields,
`J. W. Scott, and T. R. Viswanathan
`IEEE Journal of Solid-State Circuits, April 1989
`
`MOS ADC-Filter Combination That Does Not Require Precision Analog Components
`M. W. Hauser, P. J. Hurst, and R. W. Brodersen
`ISSCC Digital Technical Papers, February 1985
`
`A Multistage Delta-Sigma Modulator without Double Integration Loop
`T. Hayashi, Y. Inabe, K. Uchimura, and T. Kimura
`ISSCC Digital Technical Papers, February 1986
`
`An Oversampled Sigma-Delta AID Converter Circuit Using Two-Stage Fourth Order
`Modulator
`T. Karema, T. Ritoniemi, and H. Tenhunen
`IEEE Proceedings of the International Symposium on Circuits and Systems'90, May 1990
`v
`
`237
`
`245
`
`249
`
`255
`
`259
`
`266
`
`270
`
`279
`
`293
`
`304
`
`311
`
`317
`
`320
`
`322
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 5 of 12
`
`

`

`CONTElvTS
`
`A 12-Bit Sigma-Delta Analog-to-Digital Converter with I5-MHz Clock Rate
`R. Koch, B. Heise, F. Eckbauer, E. Engelhardt, J. A. Fisher, and F. Parzefall
`IEEE Journal of Solid-State Circuits, December 1986
`
`Area-Efficient Multichannel Oversampled PCM Voice-Band Coder
`B. H. Leung, R. Neff, P. R. Gray, and R. W. Brodersen
`IEEE Journal of Solid-State Circuits, December 1988
`
`An 18b Oversampling AID Converter for Digital Audio
`K. Matsumoto, E. Ishii, K. Yoshitate, K. Amano, and R. W. Adams
`ISSCC Digital Technical Papers, February 1988
`
`A I4-Bit 80-kHz Sigma-Delta AID Converter: Modeling, Design, and Performance
`Evaluation
`s. R. Norsworthy, I. G. Post, and H. S. Fetterman
`IEEE Journal of Solid-State Circuits, April 1989
`
`Fully Differential CMOS Sigma-Delta Modulator for High Performance Analog-to-Digital
`Conversion with 5 V Operating Voltage
`T. Ritoniemi, T. Karema, H. Tenhunen, and M. Lindell
`IEEE Proceedings of the International Symposium on Circuits and Systems'Bs, June 1988
`
`A High-Resolution CMOS Sigma-Delta AID Converter with 320 kHz Output Rate
`M. Rebeschini, N. van Bavel, P. Rakers, R. Greene, J. Caldwell, and J. Haug
`IEEE Proceedings of the International Symposium on Circuits and Systems'Bs, May 1989
`
`A CMOS Slope Adaptive Delta Modulator
`J. W. Scott, W. Lee, C. Giancario, and C. G. Sodini
`ISSCC Digital Technical Papers, February 1986
`
`Stereo 16-Bit Delta-Sigma AID Converter for Digital Audio
`D. R. WeIland, B. P. Del Signore, E. J. Swanson, T. Tanaka, K. Hamashita, S. Hara, and
`K.. Takasuka
`Journal of the A udio Engineering Society, June 1989
`
`Part 4: Digital Filters for Oversampling AID Converters
`
`Using Triangularly Weighted Interpolation to Get I3-Bit PCM from a Sigma-Delta
`Modulator
`J. C. Candy, Y. C. Ching, and D. S. Alexander
`IEEE Transactions on Communication, November 1976
`
`A Voiceband Codec with Digital Filtering
`J. C. Candy, B. A. Wooley, and o. J. Benjamin
`IEEE Transactions on Communication, June 1981
`
`Decimation for Sigma Delta Modulation
`J. C. Candy
`IEEE Transactions on Communication, January 1986
`
`Multirate Filter Designs Using Comb Filters
`S. Chu and C. S. Burrus
`IEEE Transactions on Circuits and Systems, November 1984
`
`Interpolation and Decimation of Digital Signals-A Tutorial Review
`R. E. Crochiere and L. R. Rabiner
`Proceedings of the IEEE, March 1981
`
`Wave Digital Decimation Filters in Oversample AID Converters
`E. Dijkstra, L. Cardoletti, o. Nys, C. Piguet, and M. Degrauwe
`IEEE Proceedings of the International Symposium on Circuits and Systems'Bs, June 1988
`
`vi
`
`326
`
`333
`
`340
`
`342
`
`353
`
`359
`
`363
`
`365
`
`377
`
`385
`
`400
`
`405
`
`417
`
`449
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 6 of 12
`
`

`

`CONTENTS
`
`A Design Methodology for Decimation Filters in Sigma Delta AID Converters
`E. Dijkstra, M. Degrauwe, J. Rijmenants, and O. Nys
`IEEE Proceedings of the International Symposium on Circuits and Systems'Br, May 1987
`
`On the Use of Modulo Arithmetic Comb Filters in Sigma Delta Modulators
`E. Dijkstra, o. Nys, C. Piguet, and M. Degrauwe
`IEEE Proceedings on the International Conference on Acoustics, Speech, and Signal
`Processing '88, April 1988
`
`Nine Digital Filters for Decimation and Interpolation
`D. J. Goodman and M. J. Carey
`IEEE Transactions on Acoustics, Speech, and Signal Processing, April 1977
`
`A Novel Architecture Design for VLSI Implementation of an FIR Decimation Filter
`H. Meleis and P. Le Fur
`IEEE Proceedings of the International Conference on Acoustics, Speech, and Signal
`Processing'Bi ; March 1985
`
`Efficient VLSI-realizable Decimators for Sigma-Delta Analog-to-Digital Converters
`T. Saramaki and H. Tenhunen
`IEEE Proceedings of the International Symposium on Circuits and Systems'88, June 1988
`
`Part 5: Theory and Implementations of Oversampling D/A Converters
`
`Double Interpolation for Digital-to-Analog Conversion
`J. C. Candy and A.-N. Huynh
`IEEE Transactions on Communication, January 1986
`
`A 16-Bit 4th Order Noise-Shaping D/A Converter
`L. R. Carley and J. Kenney
`IEEE Proceedings of the Custom Integrated Circuits Conference, 1988
`
`A CMOS Stereo 16-Bit DIA Converter for Digital Audio
`P. J. A. Naus, E. C. Dijkmans, E. F. Stikvoort, A. J. McKnight, D. J. Holland, and W. Bradinal
`IEEE Journal of Solid-State Circuits, June 1987
`
`Author Index
`
`Subject Index
`
`Editor's Biographies
`
`453
`
`457
`
`461
`
`467
`
`471
`
`477
`
`482
`
`486
`
`491
`
`493
`
`499
`
`vii
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 7 of 12
`
`

`

`Table-Based Simulation of Delta-Sigma Modulators
`
`RICHARD J. BISHOP, JOHN 1. PAULOS, MICHAELB.
`STEER, AND SASAN HOUSTON ARDALAN
`
`Abstract - The program ZSIM (nonlinear Z -domain SIMulator) is used
`to explore the benefits and limitations of a table-based approach to the
`simulation of delta-sigma modulators with switched-capacitor integrators.
`Simulations demonstrating the effects of clock feedthrough and incomplete
`settling are presented, as wen as simulations demonstrating the importance
`of the use of an accurate and charge conservative circuit simulator for the
`table point transient simulations. ·The methods used are appropriate for
`other discrete time systems where simulation of system-level perfonnance
`is desired based on the results of transient circuit simulation.
`
`I.
`INTRODUCTION
`Delta-sigma modulators [1] are one of a class of AjD convert(cid:173)
`ers that use oversampling to achieve a high level of precision at a
`lower sampling rate. Delta-sigma modulators can be imple...
`mented with few precision circuits and the component tolerances
`need not be precise [2], [3]. Also, delta-sigma modulators are
`easily implemented in digital MOS Ie technologies through the
`use of switched capacitor integrators [4], [5].
`A block diagram of a first-order delta-sigma modulator is
`shown in Fig. 1. The analog input signal x(t) is encoded into a
`digital pulse stream p( t). The feedback loop minimizes the error
`signal e( t), where
`
`e(I) =f[x( I) - P( I)] dl.
`
`(1)
`
`The error signal is quantized, sampled, and held for one clock
`cycle by the comparator to produce one output pulse. The system
`attempts to track the input signal x( t) with the encoded output
`stream p(t), so that the output p(t) matches the input x(t) .in
`an integrated error sense. The pulsetrain p( t) is a pulse density
`representation of x( r), and the input can be reconstructed by
`passing the pulsetrain through a low-pass filter. In most appli~a­
`tions, the pulsetrain is filtered and decimated to a lower sampling
`frequency to provide a more conventional PCM (pulse co~e
`modulation) representation of the input with high signal-to-noise
`ratio (SNR). The discrete time equivalent of Fig. 1 can be
`implemented using a switched-capacitor integrator. The error
`signal e( I) is now represented by the following difference equa(cid:173)
`tion:
`
`elk] = elk -1] +(x[k] - p[k])
`
`(2)
`
`where p[k]
`is the sampled and held result of
`comparator decision.
`Delta-sigma modulators are difficult to simulate since tens oC
`thousands of clock cycles are required in order to obtain mean-
`
`the previous
`
`Manuscript received February 23, 1989; revised May 24, 1989. This work
`was supported in part by a grant from Texas Instruments, Inc. and by the
`Center for Communications and Signal Processing. This paper was recom-
`mended by Associate Editor C.A.T. Salama.
`.
`.
`The authors are with the Department of Electrical and Computer Engineer(cid:173)
`ing. North Carolina State University, Raleigh, NC 27695-7911.
`IEEE Log Number 8933451.
`
`~ fs
`xlI) ~
`
`L~
`
`Fig. 1. Block diagram of a first-order delta-sigma modulator.
`
`ingful measures of SNR or signal-to-distortion ratios. Using
`accurate transistor-level circuit simulation, the transient analysis
`of a single clock cycle of the switched capacitor integrator may
`take several minutes of CPU time on a minicomputer or worksta(cid:173)
`tion. Detailed signal-to-noise curves would, therefore, take months
`or years of CPU time. Alternatively, difference equation models
`of the integrator can be used with dramatically reduced simula(cid:173)
`tion time", but it is not easy to capture the actual nonidealities oC
`the circuit in such a model. These nonidealities include the effects
`of finite bandwidth and slew rate of the operational amplifier,
`charge dump from the MOSFET switches, and nonlinearity of
`the amplifier transfer curve. Most of these effects can be modeled
`individually using difference equations. However, combinations
`of these effects are extremely difficult to model analytically, and
`the models obtained may only approximate the actual circuit
`behavior.
`
`II. ZSIM
`ZSIM (nonlinear Z-domain SIMulator) [6J, [7] combines the
`speed of difference equation simulation with the completeness of
`a transistor-level simulator. ZSIM uses tables (one table for each
`integrator) which are generated by a transistor-level simulator.
`Each table is a discrete representation of the nonlinear difference
`equation Cor a switched capacitor integrator which includes the
`effects of actual circuit nonlinearities. ZSIM uses these externally
`generated tables to quickly simulate the modulator over several
`thousand clock cycles.
`ZSIM can be used to simulate delta-sigma modulators using
`either ideal difference equations or externally generated tables.
`Z51M includes FFT-based signal analysis routines to compute
`SNR, signal-to-total harmonic distortion ratios (STHD), and
`signal-to-(noise + THD) ratios (SDR), as well as baseband spec(cid:173)
`tra. ZSIM also generates a histogram of
`the table usage which
`allows the user to determine the most efficient table discretiza(cid:173)
`tion.
`The tables used by ZSIM allow for the discretization of the
`input and output data for the linear and nonlinear regions of
`operation of the integrator. The output of an ideal integrator can
`be represented by
`
`y[k] =y[k-l]+a(x[k]- p[k])
`
`(3)
`
`where x[k] is the input signal during the current clock cycle,
`y[ k -1] is the integrator output from the previ.ous clock cycle,
`p(k] is the current output of the comparator w~ch wa~ sampled
`the end of the previous clock cycle, and a IS the Integrator
`at
`
`Reprinted from IEEE Trans. Circuits and Sys., vol. CAS-37, pp. 447-451, March 1990.
`
`163
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 8 of 12
`
`

`

`1.2 pF
`
`I
`
`1.8 pF
`
`1.
`
`4'1 0.06 pF ~2
`../T1~
`~2
`~t
`~
`
`)
`
`8 P1 ~
`
`Inverter
`
`Inverter
`
`FF
`
`Fig. 2.
`
`.Schematic of the second-order delta-sigma modulator.
`
`gain. The output of the binary comparator, p[k], is discrete, but
`the input signal x[k] and the integrator output y[k -1] are
`continuously valued and can,
`in general,
`range between the
`power supply rails. Therefore, the integrator tables are effectively
`divided into 2 two-dimensional
`tables (planes), with each plane
`corresponding to one value of p[ k]. Within each plane, the rows
`the input signal x[k] and the
`represent
`the discretization of
`columns represent
`the discretization of the previous integrator
`output y[ k - 1]. The table-based representation of the integrator
`can.
`therefore, be described by
`y ( kI = T( x ( kI' y [ k - 1] , P( k ])
`where T( x, y, p) denotes an interpolation of the table data. In its
`current Iorrn, ZSIM uses linear interpolation. Linear interpola(cid:173)
`tion is considered to be adequate for delta-sigma modulators
`since the system components arc designed to be approximately
`linear. The goals of this paper are: 1) to explore the limitations in
`table-based simulation as a result of
`finite precision in the
`transistor-level transient analyses used to construct thc integrator
`tables and 2)
`to explore the effects of circuit
`limitations in
`dclta-xigrnn modulators such as incomplete settling and charge
`dump from the MOSFET switches.
`
`(4)
`
`III. CIRCUIT DESCRIPTION
`
`The circui t used in this study is a second-order delta-sigma
`modulator using switched capacitor integrators, The schematic
`for this circuit is shown in Fig. 2. The switches arc composed of
`an n-channel MOSFET in parallel with a p-channel MOSFET in
`order to minimize clock feedthrough (charge dump) [8]. These
`switched-capacitor integrators require the usc of a two phase
`clock. The inputs to the modulator must be valid before the rising
`edge of clock phase q>l and must remain valid for thc duration of
`that clock phase, The output of the first integrator is valid at the
`cnd of clock phase <PI' and the output of the second integrator is
`valid at the end of clock phase <Pl' Each clock has a rise/fall time
`of 4 ns. The clock phases are aligned such that
`there is a 2-ns
`delay between the falling edge of <PI and the rising edge of <P2
`and vice-versa.
`The modulator is simulated for a 14-bit digital audio applica(cid:173)
`tion, sui table for low-grade consumer electronics. For this appli(cid:173)
`cation a clock rate of 5.6448 MHz is used with a decimation
`factor of 32, yielding a 176.4-kl-Iz sampling frequency.
`In a
`typical application,
`this 4x ovcrsamplcd data stream would be
`filtered and decimated again to obtain a 20-kl-Iz signal band(cid:173)
`width at a 44.l-kHz sampling rate.
`
`IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL 37, No.3, MARCH 1990
`
`the switched
`The operational amplifier used to implement
`capacitor integrators is a single-ended class AD amplifier operat(cid:173)
`ing from a single 5-V supply. The amplifier has an offset of 0.125
`mV, a de gain of 20000, and a unity-gain bandwidth of 20 MHz.
`The first (inverting) integrator has an input gain of 0.1 and a
`feedback gain of 0.1. The second (noninverting) integrator has an
`input gain of 0.5 and a feedback gain of 0.05. With these gains.
`typical simulations show an output swing of about - 0.6 -0.6 V
`for the first integrator, and an output swing of about - 0.S·-0.8 V
`for the second integrator with respect to analog ground (2.5 V).
`The table discretization of the columns (input values) of the first
`integrator table was chosen to be 0, - 5, - 10. - 20, and - 30 dB
`relative to a full scale swing of 5 ~p' These levels correspond to
`± 2.5, ± 1.4, ± 0.8, ± 0.25, and ± 0.08 V. The discretization of
`the rows (initial output values) of the first integrator table was
`chosen to accommodate the expected output swing of the integra(cid:173)
`tor. The discretization points for y[k -1] range from - 0.9 to
`+ 0.9 V in increments of 0.2 V. The discretization of both the
`input (columns) and previous output (rows) for the second inte-
`grator
`table is identical
`to the discretization of
`the previous
`output of the first integrator. Discretization points at 0 V were
`avoided to prevent spurious distortion of small signals due to
`small slope discontinuities ncar zero.
`
`IV. GENERATING TABLES
`
`In order for ZSIM to produce accurate results, the integrator
`tables used hy ZSIM must be accurate. To accomplish this the
`transistor-level circuit simulator used must be capable of accu(cid:173)
`rately simulating switched-capacitor integrators, the correct tim(cid:173)
`ing must be maintained during the table point transient analyses.
`and the table point transient analyses must start from the correct
`initial conditions. Tables were generated using both SPICE (ver..
`sion 2G.6) (9] and CAzM (Circuit Analyzer with Macromodcling)
`[10]. [11]. In both cases the LEVEL 2 MOSFET model was used.
`CAzM is a table-based circuit simulator developed at the Micro(cid:173)
`electronics Center of North Carolina. CAzM has t\VO advantages
`over SPICE. First. since CAzM is a table-based simulator, it is
`significantly faster
`than SPICE. Second, CAzM is a strictly
`charge-based simulator. Using SPICE,
`the switched-capacitor
`integrators operating at 5.6448 MHz exhibited errors of up to 20
`mV relative to the ideal difference equations. Using CAzM.
`errors of less than 2 mV were observed. Fig. 3 shows the errors
`relative to the ideal difference equation for one row of a table
`using both SPICE and CAzM. Fig. 4 compares the SDR curves
`generated using both CAzM and SPICE tables to the SDR curve
`generated using ideal difference equations. These simulations
`were performed for a 2576.25-Hz input signal, and the noise
`calculations assume a 20..kllz bandwidth of interest.
`is clear
`It
`from Fig. 4 that
`the tables generated with CAzM predict more
`ideal performance than do the tables generated with SPICE. The
`greater accuracy seen in the CAzM tables is believed to be due to
`the fact that, unlike SPICE, CAzM is strictly charged-based and
`completely free from conservation of charge errors. In contrast.
`SPICE 2G.6 is capacitance-based. and it has been established
`that capacitance-based simulation is not accurate for nonlinear
`dynamic circuits since charge is lost as a result of numerical
`It is especially important
`integration errors [12). [13].
`to keep
`track of charge in switched capacitor circuits, since small errors
`in charge can accumulate to produce an appreciable error over
`the transient analysis. Therefore. it is important to avoid the usc
`of capacitance-based circuit simulators (such as SPICE) to gener(cid:173)
`ate the integrator tables.
`
`164
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 9 of 12
`
`

`

`IEEE TRANSACTIONS ON CIRCUITS AND SYSnMS, VOl. 37, No .3. MARCil 1990
`
`Err or (mV)
`20.0,...--
`
`--,--
`
`--,--
`
`-----,-- - . , - -,-----,-- -
`
`SPICE, p[kl = - 1
`-
`-- - SPICE, plk] = + 1
`- "- CAzM, l,[k] = - 1
`-- - CAzM , p[k] = + 1
`
`'------- --- -- - "
`
`"
`
`"
`
`---,
`
`\
`
`\,,
`
`\,,
`
`\
`
`\
`
`\
`
`\
`
`15.0
`
`10.0
`
`5.U
`
`1- .- .- . - - '-.- -- '-' -
`- .-. _. -
`-_ . - -_ ."- " -
`'-" -.
`0.3
`
`- .-
`
`0.1
`
`0.5
`
`"-
`
`·0 .5
`
`·0 .3
`
`· 0.1
`
`Init ial Val ue (Volts)
`
`Fig. 3. Errors of SPICE and CAzM tables relative to ideal difference equa(cid:173)
`tions.
`
`Differen ce Equation
`-
`. _- CAzM
`_. - SPICE
`
`SDR (d Il)
`9U.0
`
`70.0
`
`50.0
`
`30.0
`
`/
`
`;'
`
`/
`
`,/
`
`.>
`
`, /
`
`10.0 L--_ -L_
`·60 .0
`
`_
`
`-'--_.--JL-_ -'-__-'--_ --.J
`.40.0
`-20.0
`0.0
`Amp litud e (dB)
`
`Fig . 4. SDR versus amplitude using 5.6448-MHz CAzM tabl es. SPICE ta(cid:173)
`bles, and ideal difference equations.
`
`Another important consideration when generating integrator
`tables is the timing used during the transient analysis. This
`timing must exaetly mimic the operation of the integrators during
`normal operation. The table point simulations must begin just
`prior to the end of the previous eycle and then continue for one
`clock period;
`it
`is critical
`that
`the simulations begin when the
`assumed initial condition is valid. Referring to Fig . 2, the simula(cid:173)
`integrator must begin just prior to the end or
`tion of the first
`clock phase <1>1' and the simulation of the second integrator must
`begin just prior to the end of clock phase <1>2'
`Finally, it is critical when generating integrator tables to ensure
`that
`the transient analysis starts from the correct initial condi(cid:173)
`tions. Since the points in the table arc determined by simulating
`the circuit for a given input value and a given initial output for
`is important that the output of the integrator
`the integrator, it
`not drift before the first clock change. As an example, the table
`integrator # 1 was created using the circuit configuration
`for
`shown in Fig. 5. The inductor (1 MH) acts as a short circuit at
`de, allowing the circuit to converge to the proper initial condition
`the virtual ground node for the given initial output voltage.
`at
`The voltage source J< is varied from -0.9 to 0.9 V in increments
`of 0.2 V to create the y[k -IJ initial conditions. As the transient
`
`Fig. 5. Circuit configuration for table gener ation .
`
`analysis begins, the inductor effectively becomes an open circuit
`which disconnects the voltage source. The switches at the output
`of the integrator are necessary to account for the loading effects
`of the second integrator. These switches also can produce errors
`in the first
`integrator due to ac coupling of the switching tran(cid:173)
`sients back through the feedback capacitor. Therefore. it is im(cid:173)
`portant
`to include these switches when generating the table Ior
`integrator # 1. The circuit used to generate the table for integra(cid:173)
`there were no switches
`tor #2 was identical to Fig . 5 except that
`at the output of the integrator.
`
`V. RESULTS or ZSIM SIMULATIONS
`
`This section discusses the results of ZSIM simulations for three
`variations of thc delta-sigma modulator and some of the prob(cid:173)
`lems associated with table-based simulation. The first configura(cid:173)
`tion is the nominal case , where the modulator is clocked at 5.6448
`MHz. This circuit is nearly ideal and performs at the limit of the
`accuracy of CAzM's transient analysis. The second case is the
`same circuit clocked at 11.2896 MHz. The higher clock rate is
`interesting since it can provide true 16-bit digital audio perfor(cid:173)
`mance with a decimation factor or 64. However.
`to facilitate
`comparison to the 5.644&-MHz case the ZSIM simulations for
`this case arc identical
`to the 5.6448·MHz case. except
`that
`11.2896-MHz integrator tables arc used. This case is used to
`the
`finite bandwidth and slew rate of
`examine the effects of
`operational amplifier and provides an example of spurious errors
`which may occur during transient analysis. In the third case. the
`widths and lengths of the switches arc increased by a factor or
`five to examine the effects or charge dump from the MOSFET
`switches.
`
`A. Nominal Case
`
`In the nominal case the circuit is clocked at 5.644& MHz. and
`the circuit errors arc almost negligible. The SDR curve generated
`using CAzM tables tracks the SDR curve using ideal difference
`equations fairly well, as shown in Fig. 4, up to a signal
`level of
`- 30 dB . In an actual design situation it would be critical
`to
`determine at this point whether thc discrepancy above - 30 dB is
`due to nonlinearity in the circuit or due to artifacts in the table
`generation process. Some indication can be obtained by examin(cid:173)
`ing the tables themselves.
`The tables generated using CAzM (or SPICE) can be com(cid:173)
`pared to tables generated using the ideal difference equations.
`and several error measures can be calculated. First. a table of
`point by point differences between each CAzM table and an ideal
`table was calculated, The average value of this difference table
`to eliminate the integrator
`was then computed and removed,
`
`165
`
`ParkerVision Ex. 2033
`IPR2021-00985
`Page 10 of 12
`
`

`

`output-referred offset. The offset error is due to the offset of the
`op-arnp and charge dump from the switches and docs not greatly
`affect the SNR or SDR performance. The slopes of the rows of
`the difference table was then calculated. These values were aver(cid:173)
`aged, and the linear error was subtracted from the offset cor(cid:173)
`rected difference table. This eliminates the linear gain error of the
`integrator, which again docs not significantly affect
`the SNR or
`SDR performance. This linear gain error arises due to the finite
`de gain and finite bandwidth of the operational amplifier. Fi(cid:173)
`nally, an overall
`rms error was calculated using the adjusted
`difference table with offset and linear gain errors removed . This
`error represents only the nonlinearities of
`the circuit and/or
`random errors arising from the finite precision of
`the circuit
`simulator. Spurious or random noise in the tables will cause the
`entire SDR curve to shift downward, while actual saturating
`nonlinearities in the circuit will cause the SDR curve to flatten
`out or fall off at higher amplitudes.
`Using this methodology, the offset errors for the CAzM tables
`for the nominal circuit were found to be - 0.25 mV for integrator
`# 1 and -0.44 mV for integrator #