(12) United States Patent
`Jungck et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,210,022 B2
`Apr. 24, 2007
`
`US007210022B2
`
`(54) APPARATUS AND METHOD FOR
`INTERCONNECTING A PROCESSOR TO
`CO-PROCESSORS USING ASHARED
`MEMORY AS THE COMMUNICATION
`INTERFACE
`
`(75) Inventors: Peder J. Jungck, San Jose, CA (US);
`Andrew T. Nguyen San Jose, CA
`~.
`s
`(US); Zahid Najam, San Jose, CA (US)
`(73) Assignee: Cloudshield technologies, Inc., San
`Jose, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 459 days.
`(21) Appl. No.: 09/858,308
`9
`May 15, 2001
`
`(*) Notice:
`
`(22) Filed:
`
`5,870,109 A * 2/1999 McCormack et al. ....... 345,565
`5,938,737 A
`8/1999 Smallcomb et al. ........ 709/247
`5,953,503 A
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`5.991,713 A 11/1999 Unger et al. ................... TO4/9
`6,014,660 A
`1, 2000 Lim et al. ...................... 707/3
`6,016,512 A
`1/2000 Huitema
`... TO9.245
`6,046,980 A
`4/2000 Packer ...
`... 370,230
`6,052,718. A
`4/2000 Gifford ................
`... TO9,219
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`5/2000 Narendran et al. ......... TO9,226
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`O 865 180 A2
`3, 1998 .................... 12.56
`
`EP
`
`(Continued)
`OTHER PUBLICATIONS
`
`(65)
`
`Prior Publication Data
`US 2003 FOOO9651 A1
`Jan. 9, 2003
`• - s
`
`(51) Int. Cl.
`(2006.01)
`G06F 3/00
`(52) U.S. Cl. ........................................................ 712/34
`(58) Field of Classification Search .................. 71234
`712.238,235. 7021,700/215.237,235.
`709/250, 238; 34.5/503
`See application file for complete search history.
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`(Continued)
`Primary Examiner Eric Coleman
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`Gilson & Lione
`(57)
`
`ABSTRACT
`
`An apparatus and method for interfacing a processor to one
`or more co-processors provides a dual ported memory to be
`used as a message passing buffer between the processor and
`the co-processors. Both the processor and co-processors can
`connect asynchronously to the dual ported memory. Control
`logic monitors activity by the processor to alert the co
`processors of communications by the processor written to
`the memory and otherwise allows the processor and co
`processors to think they are interfacing directly with one
`another.
`
`42 Claims, 16 Drawing Sheets
`
`BUS
`
`
`
`
`
`
`
`
`
`
`
`
`
`SSRAM 28A
`
`
`
`230B
`A
`DPSSRAM
`
`SRAM
`Control
`20B Logic
`228B
`
`24(122A, 122B)
`
`-
`
`238
`
`C.
`Processor
`
`103
`
`Pro
`
`t l
`
`238
`
`Cloudflare - Exhibit 1086, page 1
`
`

`

`US 7,210,022 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
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`
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`Cisco Enterprise Solutions, “Quality of Service,” obtained at
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`prodlit? secmn ov.htm.
`Alteon Web Systems, White Paper "Optimizing ISP Networks and
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`
`Cloudflare - Exhibit 1086, page 2
`
`

`

`US 7,210,022 B2
`Page 3
`
`Cisco Systems, "Cisco 10000 Edge Service Router,” obtained at
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`* cited by examiner
`
`Cloudflare - Exhibit 1086, page 3
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 1 of 16
`
`US 7,210,022 B2
`
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`Cloudflare - Exhibit 1086, page 4
`
`

`

`U.S. Patent
`
`Apr.24, 2007
`
`Sheet 2 of 16
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`US 7,210,022 B2
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`Cloudflare - Exhibit 1086, page 5
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`U.S. Patent
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`Apr. 24, 2007
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`

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`U.S. Patent
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`Apr. 24, 2007
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`Sheet 4 of 16
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`US 7,210,022 B2
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`Cloudflare - Exhibit 1086, page 7
`
`

`

`U.S. Patent
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`Apr. 24, 2007
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`Sheet S of 16
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`Cloudflare - Exhibit 1086, page 10
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`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 8 of 16
`
`US 7,210,022 B2
`
`FIG. 8
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`Cloudflare - Exhibit 1086, page 11
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 9 of 16
`
`US 7,210,022 B2
`
`FIG. 9
`
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`Cloudflare - Exhibit 1086, page 12
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 10 of 16
`
`US 7,210,022 B2
`
`FIG 10)
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`
`Cloudflare - Exhibit 1086, page 13
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 11 of 16
`
`US 7,210,022 B2
`
`
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`Cloudflare - Exhibit 1086, page 14
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`Cloudflare - Exhibit 1086, page 14
`
`
`
`
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 12 of 16
`
`US 7,210,022 B2
`
`7FFF (H)
`
`Global
`Registers
`32K x 32
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`Cloudflare - Exhibit 1086, page 15
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 13 of 16
`
`US 7,210,022 B2
`
`FIG. 13
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`Cloudflare - Exhibit 1086, page 16
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 14 of 16
`
`US 7,210,022 B2
`
`FIG. 14
`
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`Cloudflare - Exhibit 1086, page 17
`
`

`

`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 15 of 16
`
`US 7,210,022 B2
`
`F.G. 1S
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`Cloudflare - Exhibit 1086, page 18
`
`

`

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`U.S. Patent
`
`Apr. 24, 2007
`
`Sheet 16 of 16
`
`US 7,210,022 B2
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`Cloudflare - Exhibit 1086, page 19
`
`Cloudflare - Exhibit 1086, page 19
`
`
`
`
`
`
`
`
`
`
`

`

`US 7,210,022 B2
`
`1.
`APPARATUS AND METHOD FOR
`INTERCONNECTING A PROCESSOR TO
`CO-PROCESSORS USING ASHARED
`MEMORY AS THE COMMUNICATION
`INTERFACE
`
`RELATED APPLICATIONS
`
`The following co-pending and commonly assigned U.S.
`patent applications have been filed on the same date as the
`present application. These applications relate to and further
`describe other aspects of the embodiments disclosed in the
`present application and are herein incorporated by reference:
`U.S. patent application Ser. No.09/858,309, “EDGE
`ADAPTER APPARATUS AND METHOD, filed herewith
`now U.S. Pat. No. 7,032,031 ;
`U.S. patent application Ser. No. 09/858.323, “EDGE
`ADAPTER ARCHITECTURE APPARATUS ANT)
`METHOD, filed herewith now U.S. Pat. No. 7,144,008:
`U.S. patent application Ser. No. 09/858.324, “APPARA
`TUS AND METHOD FOR INTERFACING WITH A HIGH
`SPEED BI-DIRECTIONAL NETWORK, filed herewith
`now U.S. Pat. No. 7,082,502.
`
`10
`
`15
`
`REFERENCE TO APPENDIX
`
`An appendix A is included at the end of this document
`containing exemplary processor to co-processor instruction
`formats according to one embodiment.
`
`COPYRIGHT NOTICE
`
`A portion of the disclosure of this patent document
`contains material which is subject to copyright protection.
`The copyright owner has no objection to the facsimile
`reproduction by anyone of the patent document or the patent
`disclosure, as it appears in the Patent and Trademark Office
`patent file or records, but otherwise reserves all copyright
`rights whatsoever.
`
`BACKGROUND
`
`25
`
`30
`
`35
`
`40
`
`2
`to the exponential growth in the user of traditional network
`applications, such as the world wide web and electronic
`mail. This growth is placing an incredible strain on the
`Internet infrastructure that causes network traffic to slow and
`hardware to overload. In particular, some of these new
`applications for the network are dependent upon the quality
`of service (“OoS) of the network and cannot tolerate
`arbitrary reductions in throughput. For example, traffic inter
`ruptions in a voice telephony application may result in
`garbled or delayed communications which may not be
`tolerable to the users of Such an application.
`A way to solve these resultant network traffic jams is to
`increase the speed of the network and increase its band
`width. Another solution is to retrofit the existing infrastruc
`ture to use new technologies. Such as optical fiber intercon
`nections, which Substantially increases network throughput
`and bandwidth.
`Unfortunately, a network, and in particular the Internet, is
`not simply a collection of interconnections. Other devices,
`Such as routers, Switches, hubs, and cache servers, form an
`integral part of the network infrastructure and play important
`roles in its performance. Upgrading the interconnections of
`the network without also upgrading the hardware which
`makes all of those interconnections function, will only serve
`to move the bottlenecks but not eliminate them. Further,
`hardware devices, which seek to enhance the network, Such
`as content delivery devices or security devices, must simi
`larly be upgraded so as not to degrade any overall enhance
`ments to the network infrastructure.
`While network technologies continue to advance, some of
`these technologies advance at a quicker pace than others.
`Where these technologies interface, it is often necessary to
`adapt the slower evolving technology to keep up with the
`faster evolving technology. In Such a case, advances in
`optical networking technologies are far exceeding advances
`in the technologies to enhance the communications being
`carried by the network.
`In particular, many network enhancement applications,
`Such as security applications or content delivery applica
`tions, require the interception and processing of data from
`the network in order to perform their function. By default
`then, these devices become a choke point through which all
`the data of the network must pass. Therefore, this intercep
`tion and processing device needs to operate at or beyond the
`wire speed, i.e. the operating throughput of the network, or
`the device becomes a bottle neck. In most cases, where the
`device cannot keep pace with the network, any benefits of
`the application will be outweighed by the degradation
`caused in network throughput. Unfortunately, optical net
`working technologies are increasing wire speeds beyond the
`current capabilities of packet processing technology.
`Accordingly, there is a need for a way to cost effectively
`adapt existing packet processing technologies so as not to
`degrade network performance.
`
`45
`
`50
`
`55
`
`Computer networks, in general, interconnect multiple
`computer systems for the purpose of sharing information
`and facilitating communications. Computer networks
`include private networks which interconnect computers
`within a particular enterprise, Such as an intranet, and public
`networks, which interconnect one or more of the computers
`of enterprises, public institutions and/or private individuals.
`One exemplary public network is the Internet. The Internet
`is a packet switched network which utilizes the Transport
`Control Protocol/Internet Protocol (“TCP/IP) suite to com
`municate data.
`Networking computers together generally increases effi
`ciency and reduces wasted resources. These advantages are
`spurring significant growth in the number of computers/user
`being connected by networks and the volume of data they
`are exchanging. This growth is, in turn, spurring advances in
`network technologies to handle the increased demand being
`placed on these network infrastructures.
`This is evident on the Internet where each day more and
`more users connect to the Internet adding to the millions of
`existing users already communicating and exchanging data
`via this public infrastructure. Further, new applications for
`the network, Such as streaming video, telephony services,
`real time interactive content, instant messaging, and peer to
`peer communications continue to be developed in addition
`
`SUMMARY
`
`The present invention is defined by the following claims,
`and nothing in this section should be taken as a limitation on
`those claims. By way of introduction, the preferred embodi
`ments described below relate to an interface for coupling a
`processor to a co-processor. The interface includes a
`memory coupled with the processor and the co-processor,
`the memory having at least two read/write interfaces for
`reading and writing data to the memory and control logic
`coupled with the at least two read/write interfaces. Wherein
`the processor writes data intended for the co-processor to the
`
`60
`
`65
`
`Cloudflare - Exhibit 1086, page 20
`
`

`

`US 7,210,022 B2
`
`3
`memory and reads data from the co-processor from the
`memory, the co-processor writes data intended for the pro
`cessor to the memory and reads data from the processor from
`the memory, the control logic operative to facilitate the
`reading of the written data by the processor and the co
`processor.
`The preferred embodiments further relate to a method of
`interfacing a processor with a co-processor. In one embodi
`ment, the method includes receiving first data from the
`processor on a first interface, storing the first data in a
`memory, signaling the co-processor that the first data has
`been received, receiving a read command on a second
`interface from the co-processor, providing the first data to
`the co-processor via the second interface, receiving second
`data from the co-processor on the second interface, storing
`the second data in the memory, signaling the processor that
`the second data has been received, receiving a read com
`mand on the first interface from the processor, and providing
`the second data to the processor via the first interface.
`Further aspects and advantages of the invention are dis
`cussed below in conjunction with the preferred embodi
`mentS.
`
`10
`
`15
`
`4
`FIG. 17 depicts a more detailed diagram of the packet bus
`interface of FIG. 1.
`
`DETAILED DESCRIPTION OF THE
`PRESENTLY PREFERRED EMBODIMENTS
`
`Meeting the universal demand for an Internet that is more
`robust, that is capable of Sustaining its own growth and that
`can adapt to new technologies, requires the migration of the
`current network infrastructure to next generation networking
`technologies. This next generation data network is often
`referred to as the “Optical Internet.”
`The shift to the Optical Internet has created a new set of
`challenges. Chief among these challenges is the need to
`manage an exponentially higher Volume of network traffic at
`much higher rates of speed. In the U.S., the principal
`standard for optical networks is the American National
`Standards Institute (ANSI) standard for synchronous data
`transmission over optical media known as Synchronous
`Optical Network (“SONET). The SONET standard actually
`comprises multiple standards for transmission rates up to
`9.953 gigabits per second (“Gbps') with the capability to go
`up to 20 Gbps. Each transmission rate standard is known as
`an Optical Carrier Level (“OC-X”). Exemplary optical car
`rier levels include OC-12 for communications at 622.08
`Mbps, OC-48 for communications at 2.488 Gbps and
`OC-192 for communications at 10Gbps. Today’s micropro
`cessors face a situation where they cannot support the pace
`of performance increases associated with the deployment of
`fiber-based network bandwidth of OC-48 and higher. Simply
`put, the move to fiber-optic networks has pushed the physi
`cal limits of microprocessors and the I/O bus beyond their
`current technical capabilities. The platform described herein
`is designed to address many issues associated with Optical
`Internet services that cannot be addressed by the current
`software based firewall servers.
`FIG. 1 shows an exemplary device 100 for intercepting
`and processing packets at wire speed from an optical based
`network 102, such as the Internet, compatible with the
`OC-48 standard or faster. For a more detailed explanation of
`the operation of devices which intercept and process pack
`ets, refer to U.S. Patent Application entitled “EDGE
`ADAPTERAPPARATUS AND METHOD and U.S. Patent
`Application Serial entitled “EDGEADAPTER ARCHITEC
`TURE APPARATUS AND METHOD, both of which are
`captioned above. The exemplary device 100 may include the
`Rapid Intelligent Processing Platform manufactured by
`Cloudshield Technologies, Inc., located in San Jose, Calif.
`For clarity, some components of the device 100 are not
`shown.
`The device 100 shown in FIG. 1 is coupled with the
`network 102 (consisting of an upstream network portion
`102A and a downstream network portion 102B) via a
`network connection 110 so as to be able to intercept and
`process packets communicated between the upstream net
`work portion 102A and the downstream network portion
`102B of the network 102. Herein, the phrase “coupled with
`is defined to mean directly connected to or indirectly con
`nected through one or more intermediate components. Such
`intermediate components may include both hardware and
`Software based components. In one embodiment, the net
`work connection 110 is an optical network connection. In an
`alternate embodiment, the network connection 110 is an
`electrical network connection.
`In one embodiment, not shown in the figure, the device
`100 is configured as a rac