United States Patent (19)
`Halfacre et al.
`
`4,574,467
`[11] Patent Number:
`45) Date of Patent: Mar. 11, 1986
`
`54 N. WELL CMOS PROCESS ON AP
`SUBSTRATE WITH DOUBLE FIELD GUARD
`RINGS AND A PMOS BURED CHANNEL
`(75) Inventors:
`Mark A. Halfacre, Horsham; David
`S. Pan, Doylestown; Wing K. Huie,
`North Wales, all of Pa.
`Solid State Scientific, Inc., Willow
`Grove, Pa.
`Appl. No.: 528,095
`Filed:
`Aug. 31, 1983
`Int, Cl." .................... H01L 21/265; H01L 21/76
`U.S. C. .................................... 29/571; 29/576 B;
`29/578; 148/1.5; 357/42; 357/52
`Field of Search ..................... 29/571, 576B, 578,
`29/590,591; 148/15, 175, 187, DIG. 85;
`357/52, 42, 44
`
`73) Assignee:
`(21)
`22)
`(51)
`(52)
`58)
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,983,620 10/1976 Spadea .................................. 29/571
`4,013,484 3/1977 Boleky et al. .
`. 148/187X
`4,075,754 2/1978 Cook, Jr. .............................. 29/571
`
`4,135,955 1/1979 Gasner et al. ....................... 148/187
`4,277,291 7/1981 Cerofolini et al. .
`, 29/571 X
`4,299,024 11/1981 Piotrowski.........
`... 29/577 C
`4,385,947 5/1983 Halfacre et al.
`... 29/571 X
`4,391,650 7/1983 Pfeifer et al...
`29/576 B X
`4,435,895 3/1984 Parrillo et al. ........................ 29/571
`4,470,191 9/1984 Cottrell et al. .
`... 29/571 X
`4,474,624 10/1984. Matthews .......
`... 29/571 X
`4,480,375 11/1984 Cottrell et al. ................... 29/571 X
`Primary Examiner-Brian E. Hearn
`Assistant Examiner-David A. Hey
`57
`ABSTRACT
`CMOS transistors are fabricated in a P substrate using
`N- well regions. These wells are positioned to prevent
`aluminum spiking in the N channel devices. After P
`guard rings are formed for both P and N channel de
`vices, additional masking and implantation are per
`formed to produce N guard rings in the P channel de
`vices. Before the transistors are formed, an implantation
`of P type impurities is performed causing the P channel
`devices, when they are formed, to have a PMOS buried
`channel.
`
`3 Claims, 15 Drawing Figures
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 1 of 9
`
`

`

`U.S. Patent Mar. 11, 1986
`,U.S.Patent Mar. 11,1986;
`
`Sheet 1 of 5
`S-heetl‘ofS
`
`4,574.467
`4,574,467
`
`
`
`“'2
`
`l0
`
`FIG..|
`
`
`
`Petitioner SVTMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`, PageZ 0f9
`
`’
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 2 of 9
`
`

`

`U.S. Patent Mar. 11, 1986
`US. Patent Mar. 11,1986
`
`Sheet 2 of 5
`Sheet20f5
`
`4,574.467
`4,574,467'
`
`
`
`
`
`1‘
`
`" FIG. 8
`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1030,1PR2021-00704
`
`Page 3 of 9
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 3 of 9
`
`

`

`U.S. Patent Mar 11, 1986
`‘ U.S. Pateht Mg; 11,1986
`
`Sheet 3 of 5
`Sheet3of5
`
`4,574.467
`4,574,467.
`
`
`
`
`26a ,
`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1030,1PR2021—00704
`Page 4 of 9 '
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 4 of 9
`
`

`

`U.S. Patent Mar 11, 1986
`US. Patent Mar. 11,1986
`
`she 4ofs
`‘Sheet4of5
`
`4,574,467
`4,574,467
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`
`
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`
`54
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`
`Petitioner STMICROELECTRONICS, INC.‘,
`
`Ex. 1030, IPR2021-00704
`Page 5 of 9
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 5 of 9
`
`

`

`U.S. Patent Mar. 11, 1986
`U. S. Patent Mar. 1-1, 1986,
`
`Sheet 5 of 5
`Sheet 5 of 5
`
`4,574.467
`4,574,467
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`
`Petitioner STMICROELECTRONICS, _INC.,
`Ex. 1030, IPR2021-00704
`
`Page 6 of 9
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 6 of 9
`
`

`

`1.
`
`N. WELL CMOS PROCESS ON A PSUBSTRATE
`WITH DOUBLE FIELD GUARD RINGS AND A
`PMOS BURED CHANNEL
`
`4,574,467
`2
`third mask layer over the wells. P type impurities are
`introduced into the surface of the substrate to form P
`guard rings except in the masked portions of the N- well
`regions. A further masking layer is formed except over
`the regions in which the P channel MOS transistors are
`to be formed and N type impurities are introduced to
`form Nguard rings in these unmasked regions, resulting
`in double field guard rings. The substrate is oxidized to
`form a thick oxide layer and Ptype impurities are intro
`duced in the channel region of the CMOS transistors
`causing buried PMOS channels to be formed in the P
`channel transistors.
`DESCRIPTION OF DRAWINGS
`FIGS. 1 through 14 are cross-sectional views of a
`substrate illustrating formation of CMOS devices at
`various stages according to the methods of the present
`invention.
`FIG. 15 is a cross-sectional view of a substrate illus
`trating the resulting CMOS devices, having double field
`guard rings, a PMOS buried channel and N conductiv
`ity type well regions fabricated therein in accordance
`with the principles of the present invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`The method of fabricating CMOS devices according
`to the present invention starts as illustrated in FIG. 1 in
`which a P-type substrate 10 has a relatively thin oxide
`layer 12 formed thereon. Substrate 10 may have a crys
`talline orientation of 100), a resistivity of 2.5-80 ohm
`centimeters and an impurity concentration in the range
`of 1x1014 to 5x1015 carriers per cubic centimeter,
`Oxide layer 12 may be silicon dioxide having a thickness
`of approximately 1,000 angstroms. First masking layer
`14, is applied and openings 16a-c are formed in first
`mask 14 and oxide layer 12 to expose respective surface
`regions 18a-c of substrate 10. N type wells will be
`formed at surface regions 18a-c, Masking layer 14 is
`preferably a photosensitive resist material which is ap
`plied, exposed to the desired pattern and then etched.
`N conductivity type impurities, for example phospho
`rus, are ion implanted into the surface regions 18a-c of
`substrate 10 as illustrated in FIG. 2. The N type impuri
`ties are diffused to form N- wells 20a-cas illustrated in
`FIG.3. The region above well 20a is used to form a P
`channel transistor and the region above wells 20b,c is
`used to form an N channel transistor. N- well 20a has a
`depth of approximately 2-6 microns. N- wells 20b,c are
`more shallow because openings 16b,c have a smaller
`surface area allowing less diffusion of ions. During the
`diffusion of N- wells 20a-c, very thin regions of oxide
`19a-c are formed over the well surfaces 18a-c respec
`tively. Oxide regions 19a-c join with oxide layer 12 to
`form a continuous layer. In conventional manner prior
`to the diffusion process, photo resist layer 14 is re
`moved.
`The surface concentration of the N type impurities in
`N- wells 20a-c should be in the range of 1 x 1015 to
`3x1016 carriers per cubic centimeter. This range is
`important to prevent punchthrough in P channel MOS
`devices having short channels.
`A second masking layer of oxide inhibiting material
`22 is applied to the substrate to form a mask over the
`regions in which CMOS transistors are to be formed. As
`illustrated in FIG. 3 second mask oxide inhibiting layer
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to improved methods of
`fabrication of CMOS read only memories. Particularly,
`it relates to a method of forming double field guard 10
`rings, a method of forming a PMOS buried channel, and
`a method of preventing aluminum spiking.
`2. Background Art
`Methods of fabricating CMOS devices with guard
`rings are well-known in the art. See, for example,
`Gasner, et al., U.S. Pat. No. 4,135,955. In Gasner, et al.,
`a P- well is formed in an N type and through the succes
`sive application of masking layers and diffusion steps
`guard rings are created. The presence of the guard rings
`results in higher performance. However, this method is
`not applicable to an N- well in a P substrate.
`A problem common to PMOS devices is the mobility
`of carriers in the channel region between the source and
`the drain. In the past the electric field created during
`operation of a field effect transistor would pull holes up
`25
`to this channel creating a very shallow surface inversion
`layer which provided low carrier mobility. In this 7
`method N type starting material was used and a low
`dose P type implant into the channel was performed,
`creating an N-layer. Another method used is forming 30
`the region out of N-material. However, a method of
`performing an ion implant in this channel region, which
`would create a permanent P type high mobility channel
`with more depth would allow the CMOS device to be
`driven faster.
`35
`A cause of failure in NMOS devices is aluminum
`spiking. In this problem the aluminum of the metalliza
`tion combines through the contact with the material of
`the N-- source and drain of field effect transistors,
`causing them to be driven through to the substrate un
`40
`derneath. As a result there is created a short circuit
`between the metallization and contact layer and the
`substrate beneath the source and drain.
`It is therefore an object of this invention to achieve an
`N- well process in a P substrate with higher perfor
`45
`3C.
`Another object of this invention is to provide a
`method for producing N- well CMOS process substrate
`with double field guard rings in order to permit the
`operation of higher performance CMOS devices reli- 50
`ably in the 10 to 20 volt range.
`A further object of this invention is to provide a
`method for producing a permanent high mobility
`PMOS buried channel between the source and drains of
`field effect transistors.
`55
`It is an additional object of this invention to provide
`a method for preventing aluminum spiking between the
`metallization and contact layer of CMOS devices and
`the substrate beneath the source and drains.
`SUMMARY OF THE INVENTION
`CMOS transistors are fabricated in a P substrate by
`applying a first mask with openings for introducing N
`type impurities to form N- well regions. The wells used
`for the N channel devices are positioned so as to pre
`65
`vent aluminum spiking. A second mask layer of oxida
`tion inhibiting material is applied over the region in
`which the transistors are to be formed, followed by a
`
`15
`
`20
`
`60
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 7 of 9
`
`

`

`20
`
`4,574,467
`3
`4.
`22, which may be silicon nitride, is deposited over the
`per cubic centimeter and the resultant impurity concen
`entire surface of oxide layer 12.
`tration of the P type region 36 is in the range of 5x 1015
`Layer 22 is delineated into regions 22a, b using a pho
`to 1x1017 carriers per centimeter. If the threshold volt
`tosensitive resist material 24 and a plasma nitride etch
`age of the two MOS devices cannot be achieved by a
`although other methods of delineating second masking
`single channel-adjust doping step P conductivity type
`layer 22 may be used. As shown in FIG. 4 mask region
`impurities may be introduced using two doping steps,
`22a is formed above N- well 20a and mask region 22b is
`one for the P channel MOS device to be formed in
`formed above N- wells 20b,c, P type impurities are then
`surface region 34 and one for the N channel MOS tran
`ion implanted to form P guard rings 32a, b at the surface
`sistor to be formed in surface region 36.
`of substrate 10 except where masked by resist material
`CMOS transistors are then formed in the surface
`10
`24 and silicon nitride regions 22a,b. This combination of
`region 34 and 36 using a self-aligning technique similar
`masking regions 22a, b, resist material 24, and N- wells
`to that described in U.S. Pat. No. 4,075,754 to Cook.
`effectively forms a complete guard ring structure for all
`The Cook patent is incorporated herein by reference.
`surface regions of the substrate except those regions in
`Gate oxide layer 38 is formed where layers 19a-c had
`which transistors are to be formed. Resist material 24 is
`been on surfaces 34 and 36 in FIG. 8, followed by the
`then removed.
`application of gate material which is applied and delin
`A third masking layer 25 is applied to the substrate
`eated as seen in FIG. 9, forming gates 40a,b. Preferably
`and delineated above the entire substrate except above
`the gate material is a polycrystalline silicon having a
`N- well 20a. As with the first masking layer, the third
`thickness of approximately 3,000 to 6,000 angstroms.
`masking layer 25 may be a photosensitive resist material
`The gate oxide preferably has a thickness of approxi
`which is applied, exposed and etched. The resultant
`mately 100 to 500 angstroms. The thickness of polycrys
`structure, including second mask regions 22a,b is shown
`talline layer gates 40a,b is selected to be an effective
`in FIG. 5, N type impurities are then ion implanted to
`mask against the impurities to be implanted to form the
`form Nguard rings 32b at the surface of substrate 10
`source and drain regions of the MOS transistors. It
`except where masked by photo resist layer 25 and sec
`should be noted that the polycrystalline layer gates
`25
`ond mask region 22a. This combination of masking
`40a, b may be doped with N type impurites to reduce
`layers and N- well 20a forms N guard ring structures
`their resistance prior to delineation.
`32b in the area where P guard rings 32b had been
`Following the formation of polycrystalline silicon
`formed previously. Thus, substrate 10 contains double
`oxide layers 43 on gates 40a, b a masking layer 42 is
`field guard rings, including both the remaining P guard
`provided over surface region 36 to protect the N- chan
`30
`rings and the newly formed Nguard rings. The forma
`nel MOS device from ion implantation. This ion implan
`tion of N guard rings permits circuit performance at
`tation is performed to develop the source and drain of
`higher yoltage levels. The third masking layer 25,
`the P channel transistor. P type impurities, for example
`which protected P guard rings 32a from the N type ion
`boron, are ion implanted into surface 34 using the field
`implants, is then removed.
`oxide 26a-c and the gate material of gates 40a, b as align
`35
`The substrate is then exposed to an oxidizing atmo
`ment masks. This is followed by removal of mask 42
`sphere to grow a field oxide at all the surfaces of sub
`using conventional techniques. The ion implantation
`strate 10 except those masked by silicon nitride regions
`causes the P-- source and drain regions 44 to be formed
`22a, b, Regions 22a, b block diffusion of the oxidizing
`in alignment with the gate and the field oxide as illus
`species to the underlying substrate, thereby preventing
`trated in FIG. 10. This reduces the gate-to-source drain
`40
`oxidation of device areas. Some of the steam used in the
`capacitance. What remains of P type region 34 between
`oxidation penetrates below the edges of 22a, b, causing
`P-- source and drain regions 44 constitutes a PMOS
`the "bird's beak' effect which results in the shapes of
`buried channel device. The creation of this channel
`22a, b seen in FIG. 9. As illustrated in FIG. 6, field oxide
`removes the problem of low carrier mobility in the
`layers 26a-c are grown into substrate 10 as well as
`more shallow inversion layer which would be created
`above the substrate to partially planarize the surface and
`during operation of the transistor and allows the speed
`to vertically isolate transistor surface regions 28 and 30
`necessary for very large scale integration.
`from substrate 10, N-well regions 20a-c, and guard
`In manner similar to that shown in FIG. 10, a masking
`rings 32a and 32b. This allows better step coverage and
`layer 46 is provided over the PMOS device surface area
`improved definition of subsequent levels. Field oxide
`34, source and drain regions 44, and field oxide regions
`50
`layers 26a-c are formed to be sufficiently thick to mask
`26a-c. N type impurities such as phosphorus or arsenic
`the subsequent implants forming the source and drain
`are introduced to surface region 36 to form source and
`regions in the surface areas 28 and 30. At this stage of
`drain regions 48 for the N channel devices as illustrated
`the process field oxide 26a-c has an approximate depth
`in FIG. 11.
`of about 8000 angstroms,
`In FIG. 12 masking layer 47 is removed and reflow
`Silicon nitride regions 22a, b are stripped in boiling
`glass deposition is performed. In this deposition the
`phosphoric acid to expose oxide layers 19a-c as seen in
`substrate is covered with a dielectric layer 50 of silox.
`FIG. 7. P type impurities, for example Boron, are ion
`Dielectric layer 50 provides insulation between the
`implanted through surface regions 28 and 30. This im
`metal interconnect layer and the other layers. Apertures
`plantation is a channel-adjust doping operation used to
`are provided in the silox and the metal interconnect
`60
`determine the threshold voltage of the P channel MOS
`deposition is performed to form contact and intercon
`transistor and the N channel MOS transistor to be
`nect layer 52. As illustrated in FIG. 13 contact and
`formed in surface regions 28 and 30 respectively. The
`interconnect layer 52 may be silicon doped aluminum.
`resulting ion implantation regions are a P region 34 in
`A small amount of copper may also be added to allevi
`N- well 20a and a P region 36 in the P. substrate 10 and
`ate stress in layer 52.
`N- wells 20b,c,
`FIG. 13 also shows the improvement offered by the
`The resultant impurity concentration of the P type
`formation of N- wells 20b,c, These wells lie beneath the
`region 34 is in the range of 5X1015 to 1x1017 carriers
`regions where interconnect layer 52 makes contact with
`
`65
`
`15
`
`45
`
`55
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 8 of 9
`
`

`

`5
`
`10
`
`15
`
`35
`
`
`
`4,574,467
`5
`6
`source and drain region 48. Wells 20b and 20c are thus
`of forming CMOS devices of any channel length even
`between contact layer 52 and P- substrate 10, giving
`in the submicron range. This process requires no addi
`protection from aluminum spiking. The problem of
`tional steps and only requires modification of the impu
`aluminum spiking could arise in NMOS devices when
`rity levels of the N- wells 20a-c and the P impurity
`the aluminum of an interconnect consumes the silicon of
`levels introduced during the channel-adjust doping is
`shallow N-- source or drain 48 and makes contact with
`step.
`P-substrate 10. By interposing N- wells 20b,c this prob
`We claim:
`lem is prevented. FIG. 14 shows the final passivation
`1. A method of fabricating complimentary P-channel
`layer 54. The function of this layer is to provide scratch
`and N-channel insulated gate field effect transistors in a
`protection for the finished substrate.
`P-conductivity type substrate which comprises the
`The above described process may be used for fabri
`steps of:
`cating N and P channel devices with channel lengths
`(a) forming a first masking layer over said substrate
`down to the micron and submicron range by proper
`with a first opening to define the surface of said
`adjustment of the N- well impurity implant and the
`P-channel transistor, and a second and third open
`channel adjust doping implant. In the operation of the
`ing at the surface areas at which a source and drain
`MOS transistor, the biasing causes the surface region of
`of said N-channel transistor is to be formed;
`the channel to invert creating a conductive path be
`(b) simultaneously introducing impurities into said
`tween the source and drain regions. In addition to the
`substrate through said first, second and third open- i.
`inverted channel regions, a reverse bias depletion re
`ings to form a deep N-conductivity type well re
`gion forms about the source, drain and channel. Punch
`gion in which said P-channel transistor is to be
`20
`through occurs when the lowest corners of the source
`formed and to form deep N-conductivity type well
`and drain depletion regions touch. This results in a flow
`regions in which respectively said source and drain
`between these corners. To prevent punchthrough, the
`of said N-channel transistor is to be formed;
`impurity concentration of the channel region must be
`(c) removing said first masking layer;
`increased.
`(d) growing a gate oxide layer over the substrate
`25
`For the P channel device, the impurity concentration
`region at which said N-channel transistor is to be
`of the N- well 20a is increased in order to prevent
`formed;
`punchthrough. The impurity concentration for the sur
`(e) forming a conductive gate over a central portion
`face region of the N- well 20a should be in the range of
`of said N-channel transistor region; and
`1x1015 to 3x1016 carriers per cubic centimeter. Since
`(f) implanating N-type impurities through said gate
`30
`- the impurity concentration of the N- well 20a is in
`oxide on either side of said gate into said source and
`creased, the dose of the ion implant for the channel
`drain areas to form said source and drain of said
`adjust step which creates the PMOS buried channel 34
`N-type transistor which are substantially more
`must also be increased to produce the desired threshold
`heavily doped and shallower than said correspond
`voltage for the P channel MOS device.
`ing underlying N-type wells.
`For the N channel device, the channel adjusting ion
`2. The method of claim 1 additionally comprising
`implant not only determines the threshold voltage of
`depositing one and another aluminum conductors over
`the N channel MOS device, but also prevents punch
`said substrate selectively contacting central portions
`through since it increases the impurity concentration of
`respectively of said source and said drain, so that any
`the P-substrate. Likewise, Pregion 36 prevents punch
`penetration of said aluminum conductors through said
`40
`through as well as determining the threshold value of
`shallow source and/or said shallow drain will be pre
`the N channel MOS device. As discussed previously,
`vented by said underlying N-wells from contacting and
`the boron or P impurity implant illustrated in FIG. 7
`shorting to said P-type substrate.
`may be a single implant to modify the channel regions
`3. The method of claim 1 wherein said forming and
`thereby determining the threshold value of the P chan
`said gate is accomplished by depositing a layer of poly
`45
`nel and N channel MOS devices to prevent punch
`crystalline silicon material over said oxide layer and
`through of the P channel device. Alternately, two sepa
`removing portions of said silicon layer to define said
`rate Pimpurity implant steps may be used, one for the N
`gate that is formed of said polycrystalline silicon mate
`channel device and one for the P channel device. Thus,
`rial.
`it is evident that the process described above is capable
`
`k
`
`k
`
`k
`
`sk
`
`50
`
`55
`
`60
`
`65
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1030, IPR2021-00704
`Page 9 of 9
`
`