United States Patent (19)
`Yilmaz et al.
`
`11) Patent Number:
`45) Date of Patent:
`
`4,795,716
`Jan. 3, 1989
`
`54
`
`(75)
`
`(73)
`
`(21)
`22)
`(51)
`(52)
`58)
`
`METHOD OF MAKING A POWER C
`STRUCTURE WITH ENHANCEMENT
`AND/OR CMOS LOGIC
`Inventors: Hamza Yilmaz, Raleigh; Robert S.
`Wrathall, Durham; Mike F. Chang,
`Cary; Robert G. Hodgins, Raleigh, all
`of N.C.
`Assignee: General Electric Company, Fairfield,
`Conn.
`Appl. No.: 64,133
`Filed:
`Jun. 19, 1987
`Int. Cl." ................... H01L 21/22; H01L 21/306;
`HOL 21/265
`U.S. C. ........................................ 437/27; 437/29;
`437/34; 437/54; 437/56; 437/74
`Field of Search ....................... 437/34, 29, 54, 56,
`437/74, 27
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,346,512 8/1982 Liang et al. ........................... 437/34
`4,376,286 3/i983 Lidow et al. ......................... 357/23
`
`4,403,395 9/1983
`Curran .................................. 437/74
`4,409,725 10/1983
`Hotta et al. ........................... 437/74
`4,443,931 4/1984
`Baliga et al. .......................... 437/29
`4,616,405 10/1986
`Yasuoka ................................ 437/54
`4,633,572 1/1987
`Rusch et al. .......................... 437/45
`4,637,125 1/1987
`Iwasan et al. ......................... 437/34
`Primary Examiner-Upendra Roy
`Attorney, Agent, or Firm-Stanley C. Corwin; Birgit E.
`Morris; Kenneth R. Glick
`57
`ABSTRACT
`A process for fabricating a power IC structure which
`includes the following masking steps:
`1. CMOS P well mask
`2. JFET (short-channel implant) mask
`3. Field oxide growth mask
`4. . Deep P-- mask
`. Polysilicon mask
`5
`6
`. DMOS P well mask
`7. n-/n-- mask
`. Contact window mask
`8
`Metalization mask
`9
`1. 0. Overglass mask,
`
`25 Claims, 6 Drawing Sheets
`
`A
`
`
`
`B
`
`C
`
`D
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 1 of 13
`
`

`

`U.S. Patent Jan. 3, 1989
`
`Sheet 1 of 6
`
`4,795,716
`
`A
`
`B
`
`C
`
`D
`
`
`
`8 SN
`5 NYZ222ZZ22222222222222222222222
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`
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`
`a v.
`
`2
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 2 of 13
`
`

`

`U.S. Patent
`
`Jan. 3,
`1989
`
`Sheet 2 of 6
`
`716
`795
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 3 of 13
`
`

`

`U.S. Patent Jan. 3, 1989
`US. Patent
`Jan. 3, 1989
`
`Sheet 3 of 6
`Sheet 3 of 6
`
`4,795,716
`4,795,716
`
`
`
`A
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`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1029, IPR2021-00704
`
`Page 4 of 13
`
`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 4 of 13
`
`

`

`U.S. Patent Jan. 3, 1989
`
`Sheet 4 of 6
`
`4,795,716
`
`
`
`--6
`28
`Z zzzzzzzz Ezzzzzzzzz
`% \P /
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 5 of 13
`
`

`

`U.S. Patent Jan. 3, 1989
`
`Sheet S of 6
`
`4,795,716
`
`
`
`F-Z21222,3
`20f
`30B
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 6 of 13
`
`

`

`U.S. Patent Jan. 3, 1989
`
`Sheet 6 of 6
`
`4,795.716
`
`NSN
`
`
`
`
`
`
`
`
`
`2
`
`38A
`
`34:::::::::::::
`
`M
`
`38A
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`30A
`
`A/6 Mt.
`
`2 M ZZz
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 7 of 13
`
`

`

`1.
`
`METHOD OF MAKINGAPOWERICSTRUCTURE
`WITH ENHANCEMENT AND/OR CMOS LOGIC
`
`5
`
`10
`
`BACKGROUND OF THE INVENTION
`I. Field of the Invention
`The present invention relates in general to the fabri
`cation of a semiconductor device, and more particularly
`to the fabrication of a power IC semiconductor struc
`ture.
`II. Description of Related Art
`Fabrication processes have recently been developed
`that retain the standard steps used for the fabrication of
`discrete power devices but expand these steps to in
`15
`clude the fabrication of IC control devices. Several
`high-powered technologies can be used in these IC
`fabrication processes that take advantage of vertical
`power device fabrication steps to form standard CMOS
`devices at the same time that the power device is made.
`20
`This combination of wafer fabrication steps retains the
`desired features of both technologies and offers a cost
`effective, space saving alternative, as well as bringing
`new performance features to the system design.
`Heretofore, the combination of the power device
`25
`with the control circuitry required a relatively lengthy
`fabrication process. Typically, more than ten mask lay
`ers have been required to fabricate a device combining
`power circuitry and control circuitry.
`It is therefore an object of the present invention to
`30
`provide an improved method of fabricating a semicon
`ductor device which is not subject to the foregoing
`problems and disadvantages.
`It is an additional object of the present invention to
`provide an improved method of manufacturing a simple
`power IC structure which may include self-aligned
`CMOS.
`It is another object of the present invention to pro
`vide an improved method of manufacturing a semicon
`ductor device in which a high-density DMOSFET may
`be integrated with a 20-volt or 5-volt CMOS IC.
`It is a further object of the present invention to pro
`vide an improved method of fabricating a power IC
`structure which may have relatively high density and
`/or low "on' resistance.
`45
`It is another object of the present invention to pro
`vide an improved method of fabricating a power IC
`structure in which a 50V lightly doped chain N channel
`MOSFET may be integrated with a 20-volt depletion
`Inode N channel MOSFET.
`50
`It is a further object of the present invention to pro
`vide an improved method of fabricating a basic struc
`ture for a power IC with high density digital IC capabil
`ity.
`
`2
`
`4,795,716
`9. Metalization mask
`10. Overglass mask.
`A nonself-aligned P channel MOSFET may also be
`fabricated in accordance with one embodiment of the
`process of the present invention by eliminating masking
`step 7 from the above process sequence.
`DESCRIPTION OF THE DRAWINGS
`A detailed description of the invention will be made
`with reference to the accompanying drawings, wherein
`like numerals designate corresponding parts in the sev
`eral figures.
`FIG. 1 is a side-sectional view of an exemplary power
`IC structure manufactured by a process in accordance
`with one embodiment of the present invention.
`FIGS. 2-13 are side-sectional views illustrating as
`pects of a process sequence in accordance with one
`embodiment of the present invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`The following detailed description is of the best pres
`ently contemplated mode of carrying out the invention.
`This description is not to be taken in a limiting sense, but
`is made merely for the purpose of illustrating the gen
`eral principles of the invention. The scope of the inven
`tion is defined by the appended claims.
`Referring to FIG. 1, there is illustrated a side-sec
`tional view of an exemplary power IC structure manu
`factured by a process in accordance with one embodi
`ment of the present invention. The power IC structure
`illustrated in FIG. 1 includes the following devices
`(reading from left to right): a vertical DMOS power
`device A; a relatively high voltage N channel MOS
`FET B; a relatively high voltage P channel MOSFET
`C (which, together with the adjacent high voltage N
`channel MOSFET B, forms a CMOS device); a rela
`tively high voltage lateral N channel MOSFET D; a
`relatively low voltage P channel MOSFET E; a rela
`tively low voltage depletion mode MOSFET F; and a
`relatively high voltage P channel MOSFET G.
`It should be recognized that the process of the pres
`ent invention may be utilized to manufacture a wide
`variety of other structures. Such other structures may
`include, for example, bipolar devices or zener diodes.
`FIG. 1 therefore illustrates just one of a variety of struc
`tures which may be fabricated using the process of the
`present invention.
`Referring now to FIGS. 2-13, a preferred embodi
`ment of the present invention, including a process and a
`resulting device, will be described. As shown in FIG. 2,
`a wafer 10 is initially provided, preferably of silicon
`semiconductor material, comprising, for example, an
`N-- layer 12 having an N- epitaxial layer 14 thereon.
`The N- layer 14 includes a major surface 15 of the
`wafer 10.
`In the preferred embodiment, the N-- layer 12 may
`comprise a commercially available material doped with
`antimony or arsenic to a relatively high impurity con
`centration level of about 5x 1018 atoms per cubic centi
`meter. The N- layer 14 may typically be epitaxially
`grown on the N-- layer 12, and will have a thickness
`which may vary depending upon the application for
`which the device is intended. In the preferred embodi
`ment, the N- layer 14 has a thickness of approximately
`six microns, with a dopant concentration of about
`5X101 atoms per cubic centimeter.
`
`35
`
`55
`SUMMARY OF THE INVENTION
`In accordance with the present invention, these and
`other objectives are achieved by providing a process for
`fabricating a power IC structure which includes the
`following masking steps:
`1. CMOS P well mask
`2. JFET (short-channel implant) mask
`3. Field oxide growth mask
`4. Deep P--mask
`5. Polysilicon mask
`6. DMOS P well mask
`7. n-/n--mask
`8. Contact window mask
`
`60
`
`65
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 8 of 13
`
`

`

`10
`
`15
`
`4,795,716
`4.
`3
`product, the process sequence of the present invention
`In accordance with a preferred embodiment of the
`present invention, an oxide layer 16 (e.g., silicon diox
`may also be arranged to produce a semiconductor de
`ide), preferably having a thickness of about five hun
`vice in which all devices are fully self-aligned.
`dred angstroms, may be formed on the major surface 15
`2. JFET Mask
`Referring now to FIG. 4, the CMOSP well photore
`of the wafer 10. The oxide layer 16 may be formed by 5
`thermal growth which results when wafer 10 is placed
`sist 18 is removed and a "JFET' photoresist 22 is next
`in a heated furnace together with an oxidizing gas. The
`deposited on top of at least a portion of the oxide layer
`oxide layer 16 may also be formed by other processes,
`16. The JFET photoresist 22 is used to pattern the N
`such as deposition on wafer 10. Further, other insulat
`substrate 14, leaving exposed those regions of the N
`ing layers may be used in lieu of the oxide layer 16.
`substrate 14 where subsequent JFET ion implantation is
`While the oxide layer 6 acts primarily as an ion implant
`desired and serving as a mask or barrier to prevent
`damage screen, its placement on the major surface 15 is
`JFET ion implantation in those regions of the N
`optional and the formation of the oxide layer 16 does
`substrate 14 where JFET formation is not desired.
`not comprise an essential part of the present invention.
`N type dopantions, such as phosphorous and arsenic,
`1. CMOS P well mask
`are then implanted into those regions of the N- layer
`Referring now to FIG. 3, a "CMOSP well' photore
`14 which are not masked by the JFET mask layer 22.
`sist 18 is next deposited on top of at least a portion of the
`The phosphorous ions which are used for this implanta
`oxide layer 16. The CMOSP well photoresist 18 is used
`tion preferably have an energy of between approxi
`as a P well mask, leaving exposed those regions of the
`mately 60 KeV and 150 KeV, while the arsenic ions
`N- layer 14 where subsequent P well formation is
`20
`used for this implantation preferably have an energy of
`desired and serving as a mask or barrier to prevent
`between approximately 60 KeV and 150 KeV, depend
`implantation in those regions of the N-layer 14 where
`ing upon the depth desired for the JFET ion implant
`P well formation is not desired.
`regions. The phosphorous implantation dose is approxi
`AP-type dopantion, such as boron, is next implanted
`mately 5E11cm-2 to 5E12cm-2 and the arsenic implan
`into those regions of the N- layer 14 which are ex
`25
`tation dose is approximately 5E11cm-2 to 5E12cm2.
`posed by the CMOSP well photoresist 18. The single
`Implantation of phosphorous and arsenic ions through
`charged boron ions which are used for this implantation
`openings in the JFET mask layer 22 results in an N
`preferably have an energy of between approximately 30
`substrate 14 having a profile as shown in FIG. 4.
`KeV and 150 KeV, depending upon the depth desired
`In FIG. 4, the labels 'n', 'n-' and "n--' are used
`for the P wells. The boron implantation dose is approxi
`30
`to designate the relative concentrations of the arsenic
`mately 1013/cm2.
`and phosphorous dopant ions in the JFET implant re
`After implantation of the boron ions, the wafer 10 is
`gions 24. The implanted arsenic ions do not diffuse as
`heated to a relatively high temperature to thereby drive
`rapidly as the implanted phosphorous ions. Therefore,
`the boron dopant ions deeper into the substrate 14,
`the implanted arsenic ions tend to "pile up' near the
`providing one or more P wells 20 having profiles such 35
`major surface 15. The implanted phosphorous ions, on
`as illustrated in FIG. 3 by the P well 20B of the high
`the other hand, tend to diffuse into a larger area. As a
`voltage N channel MOSFET B. The CMOS P well
`consequence, the charge per unit area of the phospho
`masking step of the present invention may also be uti
`rous ion regions within the JFET implant regions 24
`lized in the formation of similar P wells 20 in, for exam
`will be relatively smaller than the charge per unit area
`ple, the high voltage lateral Nchannel MOSFETD and
`40
`of the arsenic ion regions within the JFET implant
`the low voltage depletion mode MOSFET F, as illus
`regions 24. The phosphorous ion regions are therefore
`trated in FIGS. 1 and 4.
`designated with the label "n-' or "n--' (depending
`It should be noted that, in the preferred embodiment
`upon the background doping of the JFET implant re
`of the present invention, the P wells 20B of the high
`gion 24) and the corresponding arsenic ion regions are
`voltage P channel MOSFET G are also formed by the 45
`designated with the label "n' or "n-', respectively.
`CMOS P well masking step, prior to the formation of
`As illustrated in FIG. 4, the JFET masking step may
`the polysilicon gate. Therefore, the polysilicon gate
`be used, for example, in the formation of N type dopant
`cannot be used to define the edges of the source and
`regions 24F, 24D and 24A in the depletion mode
`drain regions of the high voltage P channel MOSFET
`NMOS deviceF, the high voltage lateral NMOS device
`G, and there will consequently be a certain degree of 50
`D, as well as the DMOS power device A, respectively.
`nonalignment between the gate and the source and
`In the depletion mode NMOS device F, the JFET
`drain regions. The high voltage P channel MOSFET G.
`implant region 24F comprises a thin n- - layer inside
`of the final semiconductor device may therefore be
`the previously formed Pwell 20F and a highly concen
`described as "nonself-aligned'.
`trated n- epitaxial surface layer. In the high voltage
`In other devices, such as the high voltage N channel 55
`lateral NMOS device D, the JFET implant region 24D
`MOSFET B, the source and drain regions are formed
`comprises an n-yn-- region which will lie under
`after the formation of the polysilicon gate. The polysili
`neath a subsequently deposited thick oxide layer.
`con gate may therefore be used to define the edges of
`In the DMOS power device A, a subsequent implant
`the source and drain regions of the high voltage N
`of P-- ions during the deep P-- masking step will com
`channel MOSFET B, and there will consequently be a 60
`pensate the negative dopant ions in the JFET implant
`greater degree of alignment between the gate and the
`region 24A. The effect of the JFET masking step in the
`source and drain regions. Such devices may therefore
`DMOS power device A will therefore be seen only
`be referred to as "self-aligned'.
`outside of the subsequently formed Pregion, under the
`The process of the present invention therefore ena
`polysilicon gate (as will be explained in greater detail
`bles the creation of a single semiconductor device
`65
`below). The JFET masking step thereby shortens the
`which may include various combinations of both self
`aligned and nonself-aligned devices. Depending upon
`channel of the DMOS power device A and therefore
`the specific requirements of the final semiconductor
`gives low “on” resistance of the DMOS power device.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 9 of 13
`
`

`

`15
`
`40
`
`5
`
`10
`
`4,795,716
`5
`6
`The JFET masking step may also be utilized in the
`the Pwells 20 of the N channel MOSFET devices, such
`formation of N type dopant regions between devices,
`as the deep P-- well 30B of the high voltage N channel
`as, for example, the JFET region 24 between the high
`MOSFET B, the deep P-- well 30D of the high voltage
`voltage N channel MOSFET B and the high voltage P
`lateral N channel MOSFET D, and the deep P-- well
`channel MOSFET C. These inter-device dopant re
`30F of the depletion mode N channel MOSFET F. The
`gions created by the JFET masking step act as high
`deep P-- masking step of the present invention may also
`field threshold regions, serving as a barrier to isolate the
`be utilized to optionally form deep P-- wells 30 on both
`active devices from one another and to prevent the
`sides of the P wells 20 of the N channel MOSFET
`formation of parasitic effect.
`devices, as shown in FIG. 6, thereby further enhancing
`conductivity.
`3. Field Oxide Growth Mask
`Referring now to FIGS. 5 and 6, the JFET photore
`At this stage, the process sequence has produced a
`sist 22 is removed and a relatively thin layer 26 of silicon
`wafer 10 having an active area consisting of nitride 26
`nitride (Si3N4) is next deposited atop the entire wafer
`atop a thin oxide 16, with other regions consisting of a
`10, preferably by a LPCVD technique. The silicon
`relatively thick field oxide 28 having JFET regions 24
`nitride layer 26 preferably has a thickness of approxi
`implanted underneath and still other regions consisting
`mately 1,200 angstroms. One or more openings are then
`of a relatively thinner oxide with deep P-- wells 30
`formed in the silicon nitride layer 26, preferably using
`implanted underneath.
`photolithographic etching techniques.
`It should be noted that the above-described deep P+
`The silicon nitride layer 26 is used as a field oxide
`masking step may be done prior to the above-described
`growth mask, leaving silicon nitride over most of those
`field oxide growth masking step, so that the deep P
`20
`regions of the substrate 14 which are intended to be
`wells are formed prior to the formation of the thick
`come the active areas of the semiconductor circuit, and
`oxide layer. In either embodiment, only a single silicon
`exposing those regions of the substrate 14 where thick
`nitride layer 26 is required to create both deep P--
`field oxide is subsequently intended to be formed.
`regions and LOCOS regions. Therefore, the silicon
`The wafer 10 is then exposed to an oxidizing ambient,
`nitride layer need be deposited only once for both mask
`25
`causing a thick (i.e., approximately one micron) oxide
`ing steps.
`layer 28 to grow on those surface areas of the wafer 10
`from which the silicon nitride layer 26 has been re
`moved.
`The field oxide growth masking step may be utilized
`30
`to create all of the thick oxide regions 28 of the final
`semiconductor product (i.e., all oxide regions having a
`thickness greater than approximately one micron).
`These thickoxide regions 28 include the region between
`the high voltage N channel MOSFET B and the high
`35
`voltage P channel MOSFET C, as well as the oxide
`regions underneath the gates of the high voltage lateral
`Nchannel MOSFET D and the high voltage P channel
`MOSFET G.
`4. Deep P-- Mask
`Referring now to FIG. 6, after formation of the thick
`oxide region 28, one or more openings may be cut in the
`remaining portions of the silicon nitride layer 26. The
`same silicon nitride layer 26 which had been used for
`the field oxide growth masking step now functions as a
`45
`deep P-- mask, leaving exposed those regions of the
`substrate 14 where subsequent deep P-- well formation
`is desired and serving as a mask or barrier to prevention
`implantation in those regions of the substrate 14 where
`deep P-- well formation is not desired.
`50
`AP type dopant, such as boron, is implanted into the
`substrate 14 directly through the removed regions of
`the silicon nitride layer 26. The single charged boron
`ions which are used for this implantation preferably
`have an energy of between approximately 30 KeV and
`55
`150 KeV, depending upon the desired junction depth.
`The boron implantation dose is approximately
`5X101/cm2. After implantation of the boron ions, the
`wafer 10 is heated to a relatively high temperature to
`thereby drive the boron dopant ions deeper into the
`60
`substrate, providing a deep P-- well profile such as that
`of the deep P-- well 30A of the vertical DMOS power
`device A as illustrated in FIG. 6.
`Formation of deep P-- wells 30 is also generally
`desirable wherever a high latch-up resistance is re
`quired, such as in the N channel MOSFET B of the
`CMOS region. As shown in FIGS. 1 and 6, the deep
`P-- wells 30 are generally formed on the source side of
`
`5. Polysilicon Mask
`Referring now to FIG. 7, the remaining nitride layer
`26 and thin oxide layer underneath the nitride are re
`moved, and another layer 32 of high quality gate oxide
`is grown atop the wafer 10, preferably by a dry oxida
`tion process.
`A polysilicon layer 34 is then deposited atop the
`entire exposed surface of the wafer 10 and doped with
`an N-type dopant. A photoresist is used to pattern the
`polysilicon layer 34, leaving polysilicon over those
`regions where formation of the gates of both the
`DMOSFET and then channel and P channel MOSFET
`devices are desired.
`The process of the present invention thereby allows
`the JFET regions 24 and the deep P-- regions 30 to be
`placed underneath the field oxide, enabling a very high
`field oxide threshold voltage and connection of polysili
`con freely over the surface of the wafer without con
`cern about parasistic MOSFET's and leakage current
`paths.
`Y
`6. DMOS P well Mask
`Referring now to FIG. 8, a “DMOSP well” photore
`sist is next deposited on top of at least a portion of the
`substrate 14. The DMOS P well photoresist is used to
`pattern the N- region of the substrate 14, leaving ex
`posed those regions of the substrate 14 where subse
`quent DMOSP well formation is desired and serving as
`a mask or barrier to prevention implantation in those
`regions of the substrate 14 where DMOSP well forma
`tion is not desired.
`A Ptype dopantion, such as boron, is next implanted
`into those regions of the substrate 14 left exposed by the
`DMOS P well mask. The single-charged boron ions
`which are used for this implantation preferably have an
`energy of between approximately 30 KeV and 150
`KeV, depending upon the desired depth of the DMOS
`P well regions. The boron implantation dose is between
`approximately 5x1013/cm2 and 5x 101/cm2.
`As illustrated in FIG. 8, the DMOS P well mask 36 is
`used to form the P well regions 38A of the vertical
`DMOS power device A. The DMOSP well mask may
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 10 of 13
`
`

`

`4,795,716
`8
`7
`The implanted phosphorous ions form regions desig
`also be used to form the P well region 38C on the drain
`nated n- in the vertical DMOS power device A, the
`side of the high voltage P channel MOSFET C.
`high voltage in channel MOSFET B, and the high volt
`It should be noted that, in th vertical DMOS power
`age lateral Nchannel MOSFET D. During the drive in
`device A, a heavy concentration of 'n' arsenic ions
`of the implanted phosphorous ions, a layer of oxide
`exists near the surface 15 as a result of the previous
`having a thickness of between 200 angstrons and 300
`arsenic ion implantation which occured during the
`angstroms may be grown.
`JFET masking step. This heavy concentration of n ions
`Referring now to FIG. 10, following the phospho
`at the surface 15 produces a "pull back' effect in the
`rous ion implant, arsenic ions having an implant dosage
`subsequently created Pwells 38A of the vertical DMOS
`of approximately 5E15/cm2 are implanted. A relatively
`power device A, "pulling” the border regions of the P
`10
`low implant energy is selected for the arsenic ions so
`wells 38A adjacent the surface 15 toward the deep P
`that the thin silicon nitride layer 42 may serve as a mask
`region 30A, as illustrated in FIG. 8.
`to prevent the arsenic ions from being implanted in the
`7. n-vn-- Mask
`Referring now to FIG.9, a layer of silicon dioxide 40
`P channel MOSFET regions C, E and G.
`is next deposited atop the wafer 10, and a layer of silicon
`In a manner similar to that described above with
`15
`respect to the JFET masking step, the labels “n” and
`nitride 42 is formed atop the silicon dioxide layer 40. A
`“n-' have been used in FIG. 10 to designate the rela
`portion of the silicon nitride layer 42 is removed from
`tive concentrations of the implanted arsenic and phos
`the vertical DMOS power device A, the high voltage N
`phorous dopant ions, respectively. Because the im
`channel MOSFET B and the high voltage lateral N
`planted phosphorous ions tend to diffuse more rapidly,
`channel MOSFET D. The silicon dioxide layer 40 is
`they will diffuse into a larger area than the arsenic ions.
`then etched with Reactive Ion Etching (RIE).
`The charge per unit area of the phosphorous ion regions
`The silicon dioxide layer 40 and the silicon nitride
`will therefore be relatively smaller than the charge per
`layer 42 are used as an n-vn-- mask, leaving exposed
`unit area of the arsenic ion regions. The phosphorous
`those regions of the substrate 14 where subsequent
`ion regions are therefore designated with the label
`n-/n-- region formation is desired and serving as a
`25
`"n-' and the arsenic ion regions are designated with
`mask or barrier to prevent ion implantation in those
`the label "n-'. The n-vn- masking step may be
`regions of the substrate 14 where n-/n- formation is
`utilized, for example, to create the n-source region in
`not desired. One of the primary functions of the silicon
`the vertical DMOS power device A and the n--/n-
`dioxide layer 40 and the silicon nitride layer 42 is to
`source/drain region in the high voltage N channel
`block the implantation of N type dopant ions into re
`30
`gions of the substrate 14 where P type dopant ions are
`MOSFET device B.
`subsequently to be implanted (as will be explained in
`Referring now to FIG. 11, after the implantation of
`greater detail below).
`the arsenic ions, the arsenic ions are driven in and a
`An N type dopant ion, such as phosphorous, is next
`layer of silicon dioxide 46 is grown. The silicon nitride
`layer 42 is then removed. A P type dopant ion, such as
`implanted into those regions of the substrate 14 exposed
`35
`boron, is next implanted into the exposed regions of the
`by the silicon dioxide layer 40 and the silicon nitride
`layer 42. The phosphorous ion implantation dose is
`substrate 14. The energy of the boron ions which are
`used for this implantation may be varied depending
`between approximately 5E12/cm2 and 1E13/cm2.
`upon the desired depth of the shallow p-- region. The
`It should be noted that during this stage of the pro
`cess sequence, the implantation of the phosphorous ions
`boron ions preferably have an implant dosage of be
`40
`tween approximately 1E14/cm2 and 1E15/cm2.
`is also blocked by the polysilicon regions 34 which have
`The thickness of the silicon dioxide layer 46 is primar
`been formed on the wafer surface as a consequence of
`the previously completed polysilicon masking step, as
`ily dependent upon the duration of the drive in of the
`implanted arsenic ions. Since it is generally desirable to
`well as the thick oxide regions 28 which have been
`keep the implanted arsenic ion regions relatively shal
`formed on the wafer surface as a result of the previously
`45
`completed field oxide growth masking step. As a conse
`low, a drive in of extended duration is generally unde
`quence, phosphorous ions will be implanted only in
`sirable. As a consequence, the silicon dioxide layer 46
`will be relatively thin, and may not be able to fully mask
`those regions of the substrate 14 which are not masked
`some regions of the substrate 14 from the subsequent
`by the silicon dioxide layer 40, the silicon nitride layer
`implantation of boron ions.
`42, the polysilicon regions 34 and the thick oxide re
`50
`gions 28.
`This thin oxide layer problem is solved in the present
`invention by carefully selecting the implant energy of
`The phosphorous ion implant dosage and drive in
`time are preselected so that the phosphorous ion con
`the boron ions to be approximately one-tenth that of the
`implant energy of the arsenic ions. Therefore, even
`centration is less than the concentration of boron ions
`though boronions may be implanted into the previously
`previously implanted in the DMOS P well 38A during
`55
`the preceding DMOS P well masking step. Thus, even
`formed arsenic ion regions, they will have little or no
`though phosphorous ions are implanted in the DMOSP
`effect due to their relatively low ion implant energy.
`well region 38A during the n-/n- masking step, the
`Shallow p-- regions are thereby formed only at ex
`implanted phosphorous ions will have virtually no af.
`posed areas of the substrate 14 at which a previous nion
`implant has not occurred, even though boron ions are
`fect on the DMOSP well region 38A, since the charge
`60
`per volume of the implanted phosphorous ions will be
`implanted throughout the unmasked regions of the sub
`balanced or compensated for by the larger charge per
`strate 14. The implanted boron ions will have virtually
`volume of the previously implanted boron ions. By this
`no effect on the previously implanted arsenic ion re
`gions, since the charge per volume of the implanted
`careful selection of boron and phosphorous ion dosages
`and drive in times (to control junction depth), the need
`boron ions will be balanced or compensated for by the
`65
`larger charge per volume of the previously implanted
`for a separate, additional mask to block implantation of
`phosphorous ions in the DMOSP well 38A of the verti
`arsenic ions. By this careful selection of boron and ar
`senic ion dosages and drive in times (to control junction
`cal DMOS power device A is eliminated.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1029, IPR2021-00704
`Page 11 of 13
`
`

`

`O
`
`4,795,716
`10
`depth) an additional masking step for the creation of the
`opening one or more windows in said first photoresist
`layer to selectively expose said wafer layer;
`shallow p-- regions is eliminated by the process of the
`introducing a dopant of second conductivity type
`present invention. Therefore, rather than defining the
`shallow p-- regions by a separate mask, the present
`through said one or more windows in said first
`invention permits these regions to be defined by the
`photoresist layer to form one or more first regions
`effects of the previous masking steps.
`of predetermined depth in said wafer layer;
`removing said first photoresist layer from said wafer
`8. Contact Window Mask
`layer;
`Next, as illustrated in FIG. 12 with respect to the
`(b) forming a second photoresist layer on said wafer
`vertical DMOS power device A, a layer of glass 50 may
`layer;
`be deposited atop the entire wafer. Using a photolitho
`graphic mask 52, one or more contact windows 54a may
`opening one or more windows in said second photo
`be opened through the glass layer 50 to the surface of
`resist layer to selectively expose said wafer layer;
`introducing a dopant of first conductivity type
`the wafer. This procedure may be suitably accom
`plished by a number of known techniques, such as im
`through said one or more windows in said second
`15
`mersing wafer 10 in a hydrofluoric acid based solution
`photoresist layer to form one or more second re
`gions of predetermined depth in said wafer layer;
`for an interval sufficient to remove the layers exposed
`removing said second photoresist layer from said
`by the contact window mask.
`wafer layer;
`9. Metalization Mask
`As illustrated in FIG. 13 with respect to the low
`(c) for