United States Patent (19)
`Metz, Jr. et al.
`
`54 TWIN WELL SINGLE MASK CMOS
`PROCESS
`
`75) Inventors:
`
`Werner A. Metz, Jr.; Hubert O.
`Hayworth, both of Fort Collins,
`Colo.
`
`73) Assignee: NCR Corporation, Dayton, Ohio
`
`21 Appl. No.: 669,275
`
`(22
`
`Filed:
`
`Nov. 7, 1984
`
`51) Int. Cl. ...................... H01L 7/54; H01L 21/265
`52 U.S. C. ....................................... 148/15; 29/571;
`29/576 B; 29/578; 148/187; 148/DIG. 82;
`357/42; 357/91
`58 Field of Search ............... 148/1.5, 187; 29/576 B,
`29/578,571; 357/42, 91
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,376,658 3/1983 Sigusch ................................ 48/5
`4,399,605 8/1983 Dash et al
`... 29/571
`4,411,058 10/1983 Chen ...
`... 29/571
`4,442,591 4/1984 Haken ................................... 29/571
`4,470,191 9/1984 Cottrell et al...
`... 29/576 B
`4,509,991 4/1985 Taur ..................................... 148/1.5
`4,516,316 5/1985 Haskell .............................. 29/576 B
`
`Patent Number:
`11
`45) Date of Patent:
`
`4,584,027
`Apr. 22, 1986
`
`OTHER PUBLICATIONS
`Terman IBM-TDB, 23 (1984) 427.
`Ogura et al., IBM-TDB, 27 (1984) 722.
`Yachi et al., “A New Field Isolation Technology Em
`ploying Lift-Off Patterning of Sputtered SiO2 Films',
`IEEE Transactions on Electron Devices, vol. ED-31, No.
`12, Dec. 1984, pp. 1748-1752.
`Harper, "A Procedure for Field Implanting a CMOS
`Isoplanar Integrated Circuit', IEEE Transactions on
`Electron Devices, vol. ED-32, No. 3, Mar. 1985, pp.
`720-722.
`Primary Examiner-Upendra Roy
`Attorney, Agent, or Firm-Wilbert Hawk, Jr.; Casimer
`K. Salys
`ABSTRACT
`57
`A twin-well process is formed using a single mask and
`lift-off techniques. The single implant mask is formed
`and the first well implanted followed by the deposition
`of a low temperature CVD film and the application of
`lift-off techniques to remove the mask and the overlying
`CVD film. The remaining portions of the CVD film
`provide a second mask which is self-aligned with and is
`the complement of the original mask. A second implan
`tation then forms the second well. Alternative ap
`proaches using a photoresist mask and a composite
`nitride-photoresist mask structure are disclosed.
`
`13 Claims, 9 Drawing Figures
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 1 of 8
`
`

`

`U.S. Patent Apr. 22, 1986
`N -n
`O
`
`
`
`4,584,027
`Sheet 1 of 3
`--"
`FIG.
`
`FIRST MASK-12
`
`
`
`
`
`
`
`I5Y
`
`SUBSTRATE
`
`SECOND MASK-14)
`
`FIG.2
`7 FIRST MASK-12
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 2 of 8
`
`

`

`U.S. Patent Apr. 22, 1986
`
`Sheet 2 of 3
`
`4,584,027
`
`
`
`SUBSTRATE
`SILICON OXDE-14
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 3 of 8
`
`

`

`
`
`U.S. Patent Apr. 22, 1986
`US. Patent Apr. '22, 1986
`
`.
`
`Sheet 3 of 3
`Sheet 3 of 3
`
`4,584,027
`. 4,584,027
`
`
`
`:5
`
`E;
`
`
`,m_-44mgz
`
`.57:“;a
`
`:$25832
`
`o9;
`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1027,1PR2021-00704
`
`'
`
`,
`
`Page 4 of 8
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 4 of 8
`
`

`

`1.
`
`TWN WELL SINGLE MASK CMOS PROCESS
`
`4,584,027
`2
`mask comprises two layers of photoresist. The upper
`layer of photoresist is formed with a lip by over-etching
`the bottom layer.
`BACKGROUND OF THE INVENTION
`In an alternative, preferred embodiment, the bottom
`mask layer is polysilicon. Again, this lower layer is
`This invention relates to a process for forming dou
`ble-well, self-aligned regions in semiconductor sub
`over-etched to form the protruding over-layer of pho
`strates. In particular, the present invention relates to a
`toresist which is necessary for proper lift-off of the
`one-photolithographic-mask process for forming close
`... metal. In addition, the poly is not dissolved by the lift
`packed self-aligned wells which are particularly useful
`off and requires a separate etch and the use of an under
`in CMOS integrated circuits. In addition to the use of O
`lying oxide etch-stop layer.
`only a single photolithographic mask, the process is
`The above referenced Chen article, which was pub
`characterized in that a relatively simple lift-off tech
`lished after the development of the present invention,
`nique is used to remove the single photolithographic
`also describes a process for forming a quadruple-well
`mask to thereby form a doping mask for the second well
`CMOS structure comprising deep n-type and p-type
`which is the complement of the photolithographic
`15
`wells and intervening, shallow well channel stops. The
`mask. The process is further simplified by the use of
`Chen article references the aluminum lift-off step which
`preferential oxide etching as an adjunct to the lift-off.
`uses a "mushroom type' resist. Although the focus of
`Single wells or tubs (either n-type or p-type) are
`the Chen article is directed to the operating characteris
`formed in opposite conductivity-type bulk semiconduc
`tics of the resulting circuit (details of the lift-off process
`tor substrates or epitaxial layers (p-type or n-type), to
`20
`are not included), it is quite apparent that the Chen
`provide the required opposite conductivity-type sub
`article references the same process as the Chen '058
`strate surface-adjacent regions for the p-channel and
`patent and is affected by the same structural and process
`n-channel transistors which are used in CMOS technol
`complexity.
`ogy. The advantages to CMOS IC of using multiple
`It is an object of the present invention to provide a
`well structures are well-known. These include the con
`25
`single-mask double-well fabrication process which is
`trol of substrate conductivity and of doping levels, and
`also characterized by process simplicity.
`the potential for accurate dimensional control and de
`It is another object of the present invention to pro
`creased device size and the resulting increase packing
`vide a double-well fabrication process which permits
`density and speed. These and other advantages are dis
`precise dimensional and doping level control of the
`cussed, for example, in Chen, QUADRUPLE-WELL
`30
`wells.
`FOR VLSI TECHNOLOGY, IEEE Transactions on
`Electron Devices, Vol. ED-31, No. 7, July 1984, pp
`910-919. Accordingly, the advantages need not be dis
`cussed at length here. It is sufficient to note that among
`the issues which are of paramountimportance at present
`35
`are the need to decrease the latch-up phenomenon and
`the need to increase the relatively low CMOS packing
`density (relative to NMOS technology). Packing den
`sity would be increased by decreasing the large lay-out
`space which is required to form the opposite conductiv
`40
`ity regions for the n-channel and p-channel transistors.
`Chen, U.S. Pat. No. 4,411,058, issued Oct. 25, 1983
`describes a process for forming self-aligned CMOS well
`structures. Chen forms a double retrograde, quadruple
`well CMOS structure. Essentially, the structure is a
`45
`two-well structure in which deep n-type and p-type
`wells are separated by shallow n-type and p-type wells
`which form channel stops. The shallow wells are im
`planted through a peripheral field oxide during the deep
`well implantation. Overall, the Chen process involves
`50
`forming deep-well windows in a planar field oxide;
`defining a photoresist mask covering the p-well region
`and implanting phosphorous in the presence of the mask
`to define the deep n-well and the adjacent shallow n
`well under the oxide; depositing aluminum on the exist
`55
`ing structure; and lifting off the aluminum and the un
`derlying masking material from over the p-well region,
`to define the remaining aluminum as a dopant mask for
`the implantation of the deep and shallow p-type wells,
`The resulting boundaries of the deep and shallow wells
`are self-aligned at the edge of the field oxide. In addi
`tion, the two shallow wells are mutually self-aligned by
`the aluminum mask.
`According to Chen '058 patent, photoresist alone
`does not give the requisite lift-off to the overlying
`metal. Thus, a composite mushroom-shaped mask must
`be used. This, however, introduces process and struc
`tural complexities. In one embodiment, the composite
`
`SUMMARY OF THE INVENTION
`In one aspect, the present invention is a twin-well
`substrate process in which an implantation mask struc
`ture is formed; the first well is implanted; a dielectric
`film is deposited using a suitable technique such as sput
`tering, plasma, electron beam, or photodeposition, at a
`deposition temperature which is below the flow point of
`the mask structure; the first mask structure and the
`overlying portions of the dielectric layer are removed
`to form a second mask which is the complement of, and
`is self-aligned with the original mask; then a second
`implantation is made to form the second well, followed
`by thermal drive-in of the wells.
`In an additional aspect, the first well may be partially
`driven-in prior to deposition of the second well.
`In another aspect, the thermal drive-in may be per
`formed in an oxidizing ambient to form an alignment
`step for subsequent masking operations.
`In one specific aspect, the invention is embodied in a
`process for forming a self-aligned twin-well structure
`which comprises: providing a substrate layer of prede
`termined conductivity type; forming a first mask of
`photoresist on a substrate which is a complement of a
`first well region; depositing selected impurities in the
`first well region in the presence of the mask; depositing
`an oxide layer on the resulting structure, including the
`mask and first well regions, using a deposition tempera
`ture which is below the flow point of the first mask;
`etching the oxide layer to accentuate the etching of the
`stressed oxide over outside corners of the first mask,
`then removing the first mask and the overlying regions
`of the oxide layer using a mask solvent so as to pattern
`the remaining oxide into a second mask which defines a
`self-aligned second well region; and depositing impuri
`ties in the second well in the presence of the second
`
`65
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 5 of 8
`
`

`

`25
`
`30
`
`20
`
`4,584,027
`3
`4
`mask, using impurities of the opposite conductivity type
`Next, an implantation mask 12 is formed which is the
`to the first well.
`complement of the subsequently-formed first well. The
`In another specific aspect, the invention is embodied
`mask 12 can be formed using conventional ultraviolet
`in a process for forming a self-aligned twin-well struc
`photolithographic techniques. Typical steps include the
`ture which comprises: providing a substrate layer of 5
`application of photoresist, exposure to ultraviolet radia
`predetermined conductivity type; forming a first mask
`tion in the presence of a mask, followed by developing
`of a nitride layer and an outer photoresist layer on the
`of the photoresist. Alternatively, other masking tech
`substrate, which mask is the complement of a first well
`niques such as electron beam or X-ray techniques may
`region; depositing selected impurities in the first well
`be used.
`region in the presence of the mask; removing the photo- 10
`Referring further to FIG. 1, next the first-well region
`resist layer and depositing an oxide layer on the result
`13 is formed by depositing impurities 18 through open
`ing structure, including the mask and first well regions,
`ings in mask 12. Preferably, this predeposition step is
`using a deposition temperature which is below the flow
`done using ion implantation. However, furnace diffu
`point of the existing nitride layer mask structure; etch
`sion can be used if mask 12 is of the appropriate material
`ing the oxide layer to accentuate the etching of the 15
`for the temperature. A typical ion implantation se
`stressed oxide over outside corners of the nitride layer,
`quence for forming an in phosphorus well implant
`then removing the nitride layer and the overlying re
`region 13 in a p substrate 11 involves ion implantation
`gions of the oxide layer so as to pattern the remaining
`of phosphorus at 125 KeV and a dose of 2.5x1012 ions
`oxide into a second mask which defines a self-aligned
`per cm2. Of course, other n-type impurities such as
`second well region; and depositing impurities in the
`arsenic and antimony can be used.
`second well in the presence of the second mask, using
`Next, and referring to FIG. 2, a second masking layer
`impurities of the opposite conductivity type to the first
`14 is formed on the integrated circuit structure 10 of
`well. Alternatively, the photoresist can be removed
`FIG. 1, over both first mask 12 and the well implant
`prior to the first impurity deposition step so that the
`region 13. The deposition temperature for the mask 14
`nitride alone serves as the deposition mask.
`must be below the flow point of the first mask 12. The
`flow point of photoresist is about 160 to 180° C. Conse
`BRIEF DESCRIPTION OF THE DRAWINGS
`quently, when photoresist is used as the first mask 12, a
`The above and other aspects of the present invention
`low temperature CVD dielectric film is conveniently
`are discussed in detail with respect to the attached
`used to form second masking layer 14. In the presently
`drawings in which:
`preferred embodiment, a low temperature, conformally
`FIGS. 1 through 5 are cross-sectional views of a
`deposited, plasma oxide is used for layer 14. In one
`portion of a semiconductor substrate taken sequentially
`example, the silicon oxide mask 14 is formed to a thick
`during the course of forming the self-aligned twin-well
`ness of 300 to 500 nanometers using SiH4/N2/O/O2 and
`structures of the present invention;
`a temperature of about 50 to 125° C. The resulting
`FIGS. 1A through 3A are cross-sectional views in
`35
`overlapping two-mask-layer structure 15 is shown in
`the manner of FIGS. 1 through 3 illustrating corre
`FIG. 2.
`sponding steps of an alternative embodiment of the
`Next, lift-off techniques are applied to the structure
`present invention; and
`15 of FIG. 2 to remove the first mask 12 and the por
`FIG. 6 is a cross-sectional view in the manner of
`tions of the second masking layer 14 which overlie mask
`FIGS. 1 through 5 illustrating a portion of a completed 40
`12. Initially advantage is taken of the preferential etch
`CMOS integrated circuit formed in the twin-wells of
`rate of stressed plasma oxide over outside corners and
`FIG. 5.
`vertical sidewalls of the mask 12 when using a wet
`DETAILED DESCRIPTION OF THE
`buffered HF etchant. One approach for preferential
`INVENTION
`etching is disclosed in Kurosawa et al, A NEW BIRD'S
`45
`BEAK-FREE FIELD ISOLATION TECHNOLOGY
`The present invention uses lift-off techniques to form
`FOR VLSI DEVICES, IEDM-81, pp. 384-387. Essen
`a pair of self-aligned wells or tubs for CMOS or other
`tially, Kurosawa discloses the cutting of grooves in the
`integrated circuit structures. The critical aspects of the
`oxide along the sidewalls of a trench structure using a
`invention relate to the process itself and to the comple
`buffered HF solution. In the present preferential etch
`mentary processing characteristics which are required
`50
`technique, the HF etchant has very good selectivity for
`in order to (1) apply a first mask which is the comple
`the vertical sidewall portions/sections of the oxide
`ment of the initial well and which is removable from the
`substrate using lift-off techniques, and then (2) apply a
`layer 14, about (10-100):1 relative to the horizontal
`second, overlying mask and cleanly remove the second
`oxide sections, such as 14H, FIG. 3. Thus, the vertical
`sidewall oxide sections are grooved and removed, leav
`mask by lift-off of the first mask, to thereby define the
`ing the horizontal sections 14H intact.
`second well as the complement of the first. The associ
`In the present process, after application of the prefer
`ated single photolithographic mask process is character
`ized by relative process simplicity, as described below.
`ential oxide etch to remove the oxide 14 along the verti
`Referring now to FIG. 1, the starting structure typi
`cal walls of mask 12, the photoresist 12 is removed with
`cally is an unpatterned in bulk silicon substrate 11 or an
`a solvent, such as being dissolved by the application of
`60
`ultrasonically agitated acetone. The portions of the
`n epitaxial layer of <100d orientation which has a
`resistivity of one to 20 ohm-centimeters. Initially, an
`plasma layer 14 overlying the photoresist 12 are lifted
`optionally, a protective layer 9 of silicon dioxide is
`off along with the photoresist, thereby forming the
`grown on the substrate. The layer 9 prevents substrate
`layer 14 into a second mask 14H which is the self
`contamination during subsequent processing. The layer
`aligned complement of the first mask 12. That is, and
`9 can be formed about 35 to 60 nanometers thick, using
`referring to FIG. 4, the second mask 14H and well
`thermal oxidation in an oxidizing ambient at between
`opening 17 are automatically aligned with well regions
`about 900'-1 100° C.
`13.
`
`55
`
`65
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 6 of 8
`
`

`

`O
`
`15
`
`20
`
`4,584,027
`5
`6
`Next, impurities which are the opposite conductivity
`at a temperature within the approximate range 350 to
`type to the first well 13 are introduced. Typically, this
`450° C.
`is done using ion implantation. Again, however, furnace
`Thereafter, a wet buffered HF etchant is used, as
`diffusion can be used if the integrity of mask 14H can be
`discussed previously, to preferentially etch oxide over
`maintained at the furnace temperature. One suitable ion
`nitride outside corners and vertical sidewalls and
`implant action procedure uses boron, energy of 60 KeV
`thereby expose the vertical sidewall portions of nitride
`and a dose of 2.5x1012 ions per cm2. As shown in FIG.
`layer 12A, as shown in FIG. 3A. Lift-off of the nitride
`4, the resulting structure 20 includes a first n-well im
`12A and the overlying photoresist 14H is then accom
`plant region 13 and a second p-well implant region 19.
`plished by dissolving the nitride in a hot phosphoric
`The implants are next driven in sufficiently to form
`acid solution at an exemplary temperature of about
`wells using a single heating cycle. For example, a fur
`150-160 C.
`nace diffusion cycle of 1,000 to 1,200 C. is applied for
`After lift-off, the resulting structure is that shown in
`a sufficient time, typically 10 to 15 hours, to drive in the
`FIG. 4. That is, the remaining horizontal oxide sections
`n- and p-type regions to junction depths of approxi
`14H form the complementary mask which is the self.
`mately 5 micrometers. FIG. 5 illustrates the resulting
`aligned complement of the first mask structure 12. The
`structure 25 containing n-well 13' and p-well 19'.
`second mask 14H and the well opening 17 are formed in
`In an alternative version of the above-described pro
`automatic alignment with the first mask openings asso
`cess, an underlying nitride layer is used in combination
`ciated with well regions 13. Thus, after lift-off, process
`with the photoresist layer as the well implant mask for
`ing is continued as in the first-disclosed embodiment.
`the first impurity species. The nitride is then used to
`In other alternative aspects of the process sequence, a
`form the second, complementary implant mask from the
`preliminary (partial) drive-in of the impurities of the
`silicon oxide layer. This alternative form of the process
`first well region 13 may be used prior to the deposition
`allows the use of a higher temperature silicon oxide
`of the second well region, that is, between the first-mask
`process, for example a plasma oxide formed at about
`lift-off step and the second well deposition step. This
`380° C. which is well above the flow point of the resist.
`preliminary drive-in can be used to compensate for
`25
`This relatively higher temperature silicon oxide has the
`differences in doping or diffusion depth levels. This
`advantage relative to the above-described lower tem
`optional step is particularly useful where the first
`perature oxide of more uniform etch rate, fewer pin
`formed well uses relatively slow diffusing n-type dop
`ants such as arsenic or antimony, to compensate for the
`holes and defects, and increased diffusion.
`-
`Referring to FIG. 1A, the alternative processing
`slower diffusion rates of the n-type species. In still an
`30
`sequence commences as before, with the formation of
`other alternative, the drive-in may be in an oxidizing
`the silicon oxide layer 9 about 35 to 60 nanometers thick.
`ambient such as steam to preferentially oxidize the sur
`on the substrate 11. As before, the silicon oxide 9 pre
`face of the second well region 19 to provide a stepped
`vents contamination of the underlying substrate 11,
`alignment layer 21, as shown in phantom in FIG. 4. As
`principally from the photoresist chemicals, and implant
`an alternative, this well drive-in step may be used as
`ion created silicon surface damage. In addition, the
`part of the internal gettering process.
`oxide 9 functions to provide stress relief between the
`FIG. 6 illustrates a cross-section of a CMOS inte
`substrate and the silicon nitride layer 12A. In an exem
`grated circuit structure which is formed in the dual-well
`plary embodiment, silicon nitride layer 12A is a CVD
`of FIG. 5. The illustrated CMOS structure includes a
`plasma nitride formed about 300 to 500 nanometers
`NMOSFET 26 and a PMOSFET 27 which are config
`40
`thick on the oxide using an NH3/SiH4 gas system. Next,
`ured (connected) as an inverter and have respective
`and referring further to FIG. 1A, photoresist layer 12B
`source and drain diffusions 28 and 29 which are self
`is formed on the nitride to the same thickness used be
`aligned with the polysilicon gates 31, an interlevel oxide
`fore, approximately one micrometer, and is defined into
`dielectric layer 32 and aluminum interconnects 33.
`a mask as described previously. Then, using the photo
`Quite obviously, this is only one possible application
`45
`resist 12B as an etch mask, the nitride is etched to com
`among the various NMOS, PMOS, CMOS, bipolar and
`plete masking structure 12. Preferably the etch involves
`other applications of the present dual-well structure and
`the use of a dry nitride etch technique such as a mixture
`process.
`of SF6 (90%) and O2 (10%) in a parallel plate RIE sys
`Having this described preferred and alternative em
`tem. The first-well layer 13 is then formed as shown in
`bodiments of the present invention, what is claimed is:
`50
`FIG. 1A by depositing n-type impurities, as described
`1. A process for forming a self-aligned twin-well
`relative to FIG. 1, using the photoresist 12B and the
`structure comprising: providing a substrate layer of
`nitride 12A as a composite mask.
`predetermined conductivity type; forming a first mask
`Referring to FIG. 2A, the photoresist layer 12B is
`structure on the substrate which is the complement of a
`removed by any one of various techniques, such as an
`first well region; depositing selected impurities in the
`oxygen plasma, or a "piranha' wet chemical resist strip
`first region in the presence of the mask structure; depos
`using concentrated sulfuric acid and ammonium persul
`iting a relatively conformal dielectric layer on the re
`fate at about 120° C., or an ultrasonic acetone bath.
`sulting structure including the mask, a stressed dielec
`Alternatively, the photoresist 12B can be removed prior
`tric layer over the mask sidewall, and first well region
`to the first well 13 deposition. In this case, the silicon
`using a deposition temperature which is below the flow
`60
`nitride 12A along serves as the deposition mask. The
`point of the existing first mask structure; selectively
`thickness of the nitride, of course, can be increased if
`removing the stressed dielectric layer on the mask side
`necessary to accommodate particular deposition pro
`wall; removing the existing first mask structure and the
`cess parameters.
`overlying regions of the dielectric layer to form the
`Next, the second mask layer 14 of silicon dioxide is
`dielectric layer into a second mask which defines a
`65
`formed to about the same thickness, approximately 300
`second well region self-aligned with and the comple
`to 500 nanometers, as used previously, employing in an
`ment of the first well; and depositing impurities in the
`exemplary approach a SiH4/N2O/O2 plasma gas system
`second well in the presence of the second mask, using
`
`35
`
`55
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 7 of 8
`
`

`

`4,584,027
`7
`8
`impurities of the opposite conductivity type to the first
`hot phosphoric acid to remove the nitride and overlying
`photoresist from the second well regions.
`well.
`2. The self-aligned twin-well process of claim 1
`10. The self-aligned twin-well process of claim 1, 2, 3
`wherein the first mask is photoresist.
`or 4 wherein the secohd well is formed by ion implanta
`3. The self-aligned twin-well process of claim 1 5
`tion.
`11. The self-aligned twin-well process of claim 7
`wherein the first mask structure includes an outer layer
`wherein prior to the step of depositing the second well
`of photoresist which is removed after the step of depos
`impurities, the structure is heated to drive in the first
`iting impurities for the first well.
`well impurities.
`4. The self-aligned twin-well process of claim 1
`12. The self-aligned twin-well process of claim 8 or 9
`wherein the first mask structure includes an inner, sili- 10
`wherein prior to the step of depositing the second well
`con nitride layer, and an outer, photoresist layer which
`impurities, the structure is heated to drive in the first
`is removed prior to the step of depositing impurities for
`well impurities.
`the first well.
`13. A process for forming a self-aligned twin-well
`5. The self-aligned twin-well process of claim 1, 2, 3
`structure comprising: providing a substrate layer of
`or 4 wherein the first well is formed by ion implanta
`predetermined conductivity type; forming a first mask
`tion.
`structure on the substrate comprising a first silicon ni
`6. The self-aligned twin-well process of claim 1, 2, 3
`tride layer and an outer photoresist layer, which struc
`or 4 wherein the dielectric layer is silicon oxide.
`ture is the complement of a first well region; depositing
`7. The process of claim 6 wherein selectively remov
`selected impurities in the first well region in the pres
`20
`ing the oxide layer on the mask sidewall comprises
`ence of the mask; removing the photoresist layer; de
`etching the stressed sidewall oxide layer in buffered HF
`positing a relatively conformal dielectric layer on the
`etchant, and is followed by a removal of the photoresist
`resulting structure including the silicon nitride, a
`using ultrasonically agitated acetone to simultaneously
`stressed dielectric layer over the silicon nitride sidewall,
`25
`remove the overlying oxide.
`and the first well regions using a deposition temperature
`8. The self-aligned twin-well process of claim 3
`which is below the flow point of the silicon nitride;
`wherein the first mask is formed by growing a stress
`selectively removing the stressed dielectric layer on the
`relief oxide layer on the substrate, forming a layer of
`silicon nitride sidewall; removing the silicon nitride and
`silicon nitride which serves as the first mask on the
`the overlying regions of the dielectric layer to form the
`oxide layer, forming a photoresist layer on the silicon 30
`dielectric into a second mask which defines a second
`nitride and selectively removing corresponding por
`well region self-aligned with the complement of the first
`tions of the layers.
`well; depositing impurities in the second well in the
`9. The self-aligned twin-well process of claim 8
`presence of the second mask, using impurities of the
`wherein the first mask removal step comprises etching
`opposite conductivity type to the first well; and heating
`the dielectric layer from the vertical sidewall sections of 35
`the structure to drive-in the well region impurities.
`the silicon nitride using an HF etchant, then applying
`
`15
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`sk
`
`k
`
`k
`
`sk
`
`k
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1027, IPR2021-00704
`Page 8 of 8
`
`