(12) United States Patent
`Tang et al.
`
`USOO6399511B2
`(10) Patent No.:
`US 6,399,511 B2
`(45) Date of Patent:
`*Jun. 4, 2002
`
`(54) PLASMA ETCH PROCESS IN A SINGLE
`INTER-LEVEL DIELECTRIC ETCH
`(75) Inventors: Betty Tang; Jian Ding, both of San
`Jose, CA (US)
`
`(73) Assignee: Applied Materials, Inc., Santa Clara,
`CA (US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by Od
`a --
`(b) by 0 days.
`This patent is Subject to a terminal dis-
`claimer.
`
`(21) Appl. No.: 09/728,294
`(22) Filed:
`Dec. 1, 2000
`
`Related U.S. Application Data
`
`6,043,164 A 3/2000 Nguyen et al. ............. 438/736
`6,211,092 B1 * 4/2001 Tang et al. ................. 438/719
`FOREIGN PATENT DOCUMENTS
`797 242 A2 9/1997 ......... HO1 L/21/306
`EP
`840,365 A2
`5/1998 ......... HO1 L/21/311
`EP
`849 789 A2
`6/1998 ......... HO1 L/21/768
`EP
`* cited by examiner
`Primary Examiner Benjamin L. Utech
`ASSistant Examiner Binh X. Tran
`(74) Attorney, Agent, or Firm-Charles Guenzer; Joseph
`Bach
`ABSTRACT
`(57)
`A dielectric etch process applicable etching a dielectric layer
`with an underlying Stop layer. It is particularly though not
`necessarily applicable to forming a dual-damascene inter
`connect Structure by a counterbore process, in which a deep
`via is etched prior to the formation of a trench connecting
`two of more Vias. A Single metallization fills the dual
`damascene Structure. The Substrate is formed with a lower
`(62) Division of application No. 09/112,864, filed on Jul. 9, 1998,
`Stop layer, a lower dielectric layer, an upper Stop layer, and
`now Pat. No. 6,211,092.
`an upper dielectric layer. For example, the dielectric layers
`(51) Int. Cl. ............................................ H01L 21/3065
`may be silicon dioxide, and the stop layers, silicon nitride.
`(52) U.S. Cl. ....................... 438/714; 438/719, 438/723;
`The initial deep via etch includes at least two Substeps. A
`438/724; 438/725; 438/736
`first Substep includes a non-Selective etch through the upper
`(58) Field of Search
`438/714, 715
`438/70s, 723,734. 725 736 76 Stop layer followed by a Second Substep of Selectively
`s
`a--s
`a- is
`a- as - s/s
`etching through the lower dielectric layer and Stopping on
`References Cited
`the lower stop layer. The first Substep may be preceded by
`yet another Substep including a Selective etch part ways
`through the upper dielectric layer. For the oxide/nitride
`compositions, the Selective etch is based on a fluorocarbon
`and argon chemistry, preferably with a lean etchant of CHF
`combined with a polymer former, Such as CF, CFs, or
`CHF, and the non-Selective etch includes a fluorocarbon or
`hydrocarbon, argon and an OXygen-containing gas, Such as
`CO. The counterbore etch is preferably performed in a
`high-density plasma reactor which allows the plasma Source
`region to be powered Separately from a sheath bias located
`adjacent to the wafer pedestal.
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`5,356,515 A 10/1994 Tahara et al. ............... 156/643
`5,374,332 A 12/1994 Koyama et al. .....
`... 156/643
`5,399.237 A
`3/1995 Keswick et al. ............ 156/643
`5,503.901 A 4/1996 Sakai et al. ................. 428/161
`5,578,523 A 11/1996 Fiordalice et al. .......... 437/190
`5,589,041 A 12/1996 Lantsman .............. 204/192.33
`5,595,627 A
`1/1997 Inazawa et al. .......... 156/643.1
`5,612.254. A
`3/1997 Mu et al. .................... 437/195
`5,635,423 A 6/1997 Huang et al. .....
`... 437/195
`5,683,548 A 11/1997 Hartig et al. ..... ... 156/643.1
`5,741,626. A
`4/1998 Jain et al. ................... 430/314
`5,877.075 A * 3/1999 Dai et al. ................... 438/597
`
`
`
`39 Claims, 7 Drawing Sheets
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 1 of 17
`
`

`

`U.S. Patent
`
`Jun. 4, 2002
`
`Sheet 1 of 7
`
`US 6,399,511 B2
`
`(PRIOR ART)
`FIG. 1
`
`FIG 2
`
`
`
`GROW AL UNPATTERNED
`DUAL-DAMASCENE LAYERS
`
`PHOTOMASK VA HOLES
`
`PHOTOMASK TRENCH
`
`ETCH TO UPPER STOP LAYER
`
`ETCH EXPOSED LOWER STOP
`LAYER TO SUBSTRATE
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 2 of 17
`
`

`

`U.S. Patent
`US. Patent
`
`Jun. 4, 2002
`Jun. 4, 2002
`
`Sheet 2 of 7
`Sheet 2 0f 7
`
`US 6,399,511 B2
`US 6,399,511 B2
`
`
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1025,1PR2021-00704
`
`Page 3 of 17
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 3 of 17
`
`

`

`U.S. Patent
`US. Patent
`
`Jun. 4, 2002
`Jun. 4, 2002
`
`Sheet 3 of 7
`Sheet 3 0f 7
`
`US 6,399,511 B2
`US 6,399,511 B2
`
`
`
`
`
`
`
`
`
`74
`
`72
`
`20
`
`14'
`
`14
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`SN
`
`16
`16
`
`
`
`A 12
`
`
`
`
`
`—12
`
`FIG 8
`FIG. 8
`
`76 68
`75
`68
`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1025, IPR2021-00704
`
`Page 4 of 17
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 4 of 17
`
`

`

`US. Patent
`
`Jun. 4, 2002
`
`Sheet 4 0f 7
`
`US 6,399,511 B2
`
`
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`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1025,1PR2021-00704
`
`Page 5 of 17
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 5 of 17
`
`

`

`U.S. Patent
`
`Jun. 4, 2002
`
`Sheet 5 of 7
`
`US 6,399,511 B2
`
`
`
`
`
`
`
`NON-SELECTIVE TIMED ETCH
`THROUGH UPPER OXDE,
`UPPER NITRDE AND
`SOME LOWER OXDE
`
`
`
`
`
`
`
`ETCH LOWER
`OXIDE
`STOP ON
`LOWER NITRIDE
`
`124
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 6 of 17
`
`

`

`U.S. Patent
`
`Jun. 4, 2002
`
`Sheet 6 of 7
`
`US 6,399,511 B2
`
`- SUB-STEP 1
`
`SUB-STEP 2
`
`124
`PUNCH THROUGH
`-1SNEER
`
`
`
`
`
`
`
`70
`
`SIGNAL
`%
`
`50
`
`30
`O
`
`60
`
`FIG. 13
`
`TIME (sec)
`
`120
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 7 of 17
`
`

`

`U.S. Patent
`
`Jun. 4, 2002
`
`Sheet 7 of 7
`
`US 6,399,511 B2
`
`NON-SELECTIVE TIMED ECH
`THROUGH UPPER NITRDE AND
`SOME LOWER OXDE
`
`
`
`
`
`
`
`
`
`
`
`ETCH LOWER
`OXDE
`STOP ON
`LOWER NITRIDE
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 8 of 17
`
`

`

`US 6,399,511 B2
`
`1
`PLASMA ETCH PROCESS IN A SINGLE
`INTER-LEVEL, DELECTRIC ETCH
`
`RELATED APPLICATION
`This application is a division of Ser. No. 09/112,864, filed
`Jul. 9, 1998, now issued as U.S. Pat. No. 6,211,092. This
`application is also related to Ser. No. 09/112,092, filed Jul.
`9, 1998.
`
`FIELD OF THE INVENTION
`The invention relates generally to plasma etch processes.
`In particular, the invention relates to the highly Selective
`etching of insulating materials, particularly Silicon oxide,
`forming part of a complex integrated-circuit structure.
`
`15
`
`2
`dielectric layer 14, having a thickness of, for example, 1 um
`or Somewhat less, and a thin upper Stop layer 16. The Stop
`layers 12, 16 have compositions relative to the dielectric
`material Such that a carefully chosen etch process that is
`Selective to the material of the Stop layer etches through the
`overlying dielectric but stops on the Stop layer. Although
`copper metallization and low-k dielectric would more fully
`utilize the advantage of the dual-damascene Structure, the
`present description will use Silicon dioxide as the principal
`inter-level dielectric. Silicon dioxide is preferably grown by
`plasma-enhanced chemical vapor deposition (PECVD)
`using tetraethylorthosilicate (TEOS) as the main precursor
`gas. Silicon nitride (SiN) is a common material for stop
`layers when the dielectric is an oxide. Silicon nitride is
`preferably also grown by PECVD to reduce the thermal
`budget, and its general composition is given by SiN, where
`X may vary Somewhat over a range of, for example 1 to 1.5.
`A dielectric photolithographic Step is then performed to
`create circular holes 18 in the upper stop layer 16. The
`diameters of the circular holes 18 determine the diameters of
`the via holes, which usually represent the Smallest dimen
`Sion defined in the dielectric etch. The Smallest defined
`lateral dimension in a level is often referred to as the critical
`dimension (CD). The dual-damascene structure can be used
`both at the power level, which is the uppermost metal layer,
`and at the Signal levels, for example, metal-1 and metal-2
`levels for a moderately complex logic chip. The power level
`typically has a larger via size, for example, 0.6 um, while the
`Signal levels typically have Smaller via sizes, for example,
`0.3 um. This diameter is being reduced to 0.25 um and to yet
`lower sizes in advanced Structures. Total dielectric thickneSS
`also varies between the power and Signal levels. The etching
`in this photolithographic step is preferably Selective to the
`principal dielectric material so that at this point the holes 18
`do not significantly extend into the lower dielectric layer 14.
`Then, in the continuation of the Self-aligned dual
`damascene process, an upper dielectric layer 20 is deposited
`to a thickness of, for example, 1.4 um over the partially
`etched Structure, including deposition into the etched
`depressions in the patterned nitride layer 16. A photoresist
`mask is deposited and defined into the shape of a trench 22
`having a width of, for example, 1.2 um and a much longer
`length. A Self-aligned dual-damascene dielectric etch is then
`performed both to form the trench 22 in the upper oxide
`layer 20 and to extend the lower via holes 18 through the
`lower oxide layer 14 and down to the lower stop layer 12.
`The upper nitride stop layer 16 serves both as a stop for
`forming the trench 22 and as a hard mask for etching the Via
`hole 18. The combined etch must not significantly etch the
`upper stop layer 16 at the floor 24 of the trench 22, and it
`must stop at the lower stop layer 12 at the bottom 26 of the
`via holes 18. In a further step, not illustrated here because it
`is generally considered to be non-crucial, a further non
`selective etch removes the portion of the lower stop layer 12
`at the bottom of the via hole 18 so as to expose the substrate
`10 to contacting when metal is filled into the trench 22 and
`via hole 18.
`In the Self-aligned dual-damascene etch process, the
`selectivity of the oxide etch to nitride or other stop material
`in both the relatively open trench floor 24 and particularly at
`the shoulders 28 of the via holes 18 is especially crucial
`Since these areas are exposed to the etching plasma while the
`via holes 18 are being etched. Generally, the shoulders 28
`etch faster than the trench floor 24 because of the exposed
`geometry. The upper nitride layer 16 and its shoulder 28 are
`further exposed during a long over-etch of the lower oxide
`layer 14, typically greater than 100% to reliably open the via
`
`BACKGROUND ART
`The technology of fabricating Semiconductor integrated
`circuits continues to advance in the number of transistors,
`capacitors, or other electronic devices which can be fabri
`cated on a Single integrated circuit chip. This increasing
`level of integration is being accomplished in large part by
`decreasing the minimum feature sizes. Even as the number
`of layers in the integrated circuit continues to increase,
`advanced processes are being used which allow for a reduc
`tion in the number of processing Steps for a functional layer.
`However, these advanced processes often make extraordi
`nary demands upon the chemistry of the etching process.
`Dielectric etching has presented Some of the most difficult
`demands.
`In the past the common materials for inter-level dielectric
`have been based upon Silicon, Such as Silicon dioxide, Silica
`glass Such as BPSG, and related Silicon-based oxide mate
`rials that Serve as electrical insulators. Recently, interest has
`developed in insulating materials with low dielectric con
`Stants (low-k dielectrics), Some of which are based upon
`Silicon but others are based upon carbon.
`Advanced integrated circuits contain multiple wiring lay
`erS Separated from the Silicon Substrate and from each other
`by respective dielectric layers. Particularly logic circuitry,
`Such as microprocessors, require Several layers of metalli
`Zation with intervening inter-level dielectric layers. Small
`contact or via holes need to be etched through each of the
`dielectric layers. The contact or via holes are then filled with
`a conductor, composed typically of aluminum in the past but
`more recently composed of copper. A horizontal wiring layer
`is formed over one dielectric layer and then covered by
`another dielectric layer. The horizontal wiring and the under
`lying Vias are often referred to as a single wiring layer. The
`conventional proceSS not only fills the contact or via holes
`but also overfills them to form a thick planar layer over both
`the filled holes and the dielectric. Conventionally, a metal
`lithographic Step then photographically defines a photoresist
`layer over the planar metal layer and etches the exposed
`metal into a network of conductive interconnects.
`In contrast, a recently developed damascene process Sub
`Stitutes chemical mechanical polishing for metal etching. A
`dual-damascene Structure, as illustrated in Sectioned isomet
`ric view in FIG. 1, has been proposed for advanced chips
`which avoids the metal etching and combines the metalli
`Zation of the via and horizontal interconnect. There are two
`general types of dual-damascene processes, Self-aligned and
`counterbore. The more conventional Self-aligned dual
`damascene process will be described first.
`Over a substrate 10 is formed a thin lower stop layer 12
`having a minimal thick of, for example 100 nm, a lower
`
`25
`
`35
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`40
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`45
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`50
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`60
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`65
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 9 of 17
`
`

`

`3
`in the presence of proceSS and other non-uniformities. Such
`Selectivity can be achieved by use of a highly polymerizing
`chemistry which deposits a protective polymeric coating on
`the non-oxide Surfaces and vertical oxide Surfaces but gen
`erally not on the horizontal oxide surfaces. However, the
`extensive polymerization impacts the etching of the narrow
`and deep via holes 18 and may cause etch Stop. Etch Stop
`occurs when the Side walls are So heavily polymerized that
`the polymer closes the hole and prevents further etching of
`the bottom of the hole. Of course, etch stop in the via holes
`18 must be avoided. As a result, the process window for the
`Self-aligned process is often limited by the conflicting
`requirements of the oxide etch to maintain the nitride
`shoulders 28 while continuing to open the oxide in the via
`hole 18. The etch must maintain the bottom critical dimen
`sion (CD) associated with the via hole 18 in order to
`maintain tight control of the via resistance. The top critical
`dimension associated with the trench 22 is less critical, but
`depending upon the pitch of via holes 18, it may determine
`the margin for Shorting between Vias associated with differ
`ent trenches. The trench profile needs to be vertical to
`maintain consistent line widths.
`Following the etching of the dual-damascene Structure by
`either the Self-aligned or counterbore process, a Single
`metallization operation fills both the via holes 18 and the
`trench 22. The metallization operation may require that the
`trench 22 and via hole 18 be coated with barrier layers and
`wetting layers, as has become well known in metallization
`of Small features in advanced integrated circuits. The metal
`deposition, usually performed at least partially by physical
`Vapor deposition, is continued to the extent that the metal
`completely fills the via holes 18 and trench 22 and somewhat
`overlies the top 30 of the upper oxide layer 20. Chemical
`mechanical polishing is then performed, and because Silica
`is much harder than metal the polishing Stops when it
`encounters the upper oxide layer 20. Thereby, the metalli
`zation is restricted on the top of the wafer to the trench 22.
`The metallization may either serve both as a horizontal
`interconnect between two or more locations in the Substrate
`through the via holes 18 and as an inter-level vertical
`interconnect in the via holes 18. The dual-damascene pro
`ceSS is particularly useful for copper metallization because
`no copper etching is required.
`In the Self-aligned dual-damascene process, the lower
`Stop layer 12 is photolithographically patterned before the
`upper dielectric layer 20 is deposited, and the trench and the
`via are etched in a Single proceSS Step. Such a proceSS
`requires balancing nitride Selectivity against etch Stop
`margin, and achieving a wide process window for an accept
`able process poses a great challenge in developing an oxide
`etch recipe.
`An alternative dual-damascene process, referred to as a
`counterbore dual-damascene process for reasons which will
`become apparent, Separates the via and trench etch StepS.
`Thereby, the nitride shoulder need not be exposed for such
`long times to the oxide etch So that the balance between
`Selectivity and etch Stop is eased. The counterbore process is
`thus advantageous for Smaller via sizes.
`The counterbore process is illustrated in the flow diagram
`of FIG. 2 with reference to the cross-sectional structures of
`FIGS. 3–8, which show the sequential development of the
`dual-damascene Structure. In Step 40, an unpatterned, planar
`dual-damascene Structure is grown comprising, as illustrated
`in the cross-sectional view of FIG. 3, the Substrate 10, the
`lower Stop layer 12, the lower dielectric layer 14, the upper
`stop layer 16, and the upper dielectric layer 20. No photo
`lithography is performed between the layers 12, 14, 16, and
`
`15
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`40
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`45
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`50
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`US 6,399,511 B2
`
`4
`20, and their compositions may be such to allow their
`growth by chemical vapor deposition (CVD) in a single
`plasma reaction chamber by varying the composition of the
`feed gas and the operating conditions between the layers.
`In Step 42, a first photoresist layer 44 is deposited and
`photographically patterned to form mask apertures 46 cor
`responding to the via or contact holes, only one of which is
`illustrated. It will be assumed that the underlying substrate
`10 includes a metal Surface in the area of the hole So it is
`properly called a via hole. Although the metal is preferably
`copper, the examples of the invention use an aluminum
`metallization. The composition of the metallization has very
`little effect upon the dielectric etch.
`In a first etch step 48, an extended via hole 50, as
`illustrated in FIG. 4, is etched through the upper dielectric
`layer 20, the upper stop layer 16, and the lower dielectric
`layer 14 down to the lower stop layer 12. The etch chemistry
`is chosen to be selective to the material of the lower stop
`layer 12 so that the etch stops at the top surface 52 of the
`bottom stop layer 12.
`In an unillustrated Step, the first photoresist layer 44 is
`Stripped. In Step 54, a Second photoresist layer 56, as
`illustrated in FIG. 5, is deposited and photographically
`patterned to form a mask aperture 58 corresponding to the
`trench. In a second etch step 60, a trench 62, illustrated in
`FIG. 6, is etched through the upper dielectric layer 20 down
`to the top surface 64 of the upper stop layer 16 without
`Significantly eroding the top Surface 52 of the bottom Stop
`layer 12. The depth of the extended via hole 50 is thereby
`reduced to form a via hole 50'.
`In a third etch step 66, the exposed portion of lower stop
`layer 12 at the bottom of the via hole 50' is etched, as
`illustrated in FIG. 7, through the lower stop layer 12 and
`down to an upper surface 68 of the substrate 10, which is
`typically a metal for a via. Depending upon the compositions
`of the two stop layers 12, 16, the third etch step 66 may
`remove portions of the upper Stop layer 16 exposed at the
`bottom of the trench 62 to form a shelf 70 in the upper oxide
`layer 14, but this thin portion is not critical. In another
`unillustrated step, performed either before or after the third
`etch step 66, the second photoresist layer 56 is stripped
`along with any Sidewall polymer forming in the dielectric
`etch.
`Thereafter, as illustrated in FIG. 8, a metal 72 is filled into
`the trench 62 and underlying via hole 50' to contact the upper
`surface 68 of the substrate 10. Subsequent chemical
`mechanical polishing (CMP) removes any metal overflow
`ing the trench 62. The metal 72 forms both a horizontal
`interconnect 74 and a via 76 contacting the underlying layer
`10. As mentioned before, the metal 72 may be the conven
`tional aluminum or the more advanced copper.
`However, the counterbore etch proceSS is very demand
`ing. The first, via etch 48 of the extended via hole 50 is deep
`and narrow, the width usually representing the critical
`dimension of the process. The via etch 48 must etch through
`the upper Stop layer 16 but stop on the lower Stop layer 12.
`The deep via etch 48 thus requires a vertical profile and high
`selectivity to the bottom stop layer 12. Not only must the
`interconnect (trench) etch 60 stop on the upper Stop layer 16,
`it must not significantly etch the lower Stop layer 12, which
`is exposed during the entire interconnect etch. The intercon
`nect etch 60 thus requires a vertical profile and high Selec
`tivity to the upper stop layer 16. If the lower stop layer 12
`is inadvertently etched through during the long over-etch, an
`effect called punch through, the underlying metal is
`Sputtered, and as a result device reliability is Severely
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 10 of 17
`
`

`

`US 6,399,511 B2
`
`15
`
`25
`
`35
`
`40
`
`S
`impacted, particularly if copper is used as the underlying
`metallization. All etch Steps, but particularly those etching
`through the thicker dielectric layers, should be highly
`isotropic, producing nearly vertical Side walls. To achieve
`the vertical profile, the etching of the Stop layers should not
`Significantly Side etch the dielectric layers located above.
`The first, via etch step 48 must selectively etch the upper
`stop layer 16 relative to the lower stop layer 12. This can be
`accomplished in a single etch Step with the choice of
`significantly different materials for the two stop layer 12, 16.
`However, the choice is limited and not attractive. The
`growth of the planar structure of FIG. 3 is preferably
`performed in a single CVD reactor, which may be difficult
`to accomplish for materials of vastly different chemistries.
`Also, it is desired to form both stop layers 12, 16 out of
`materials having fairly good insulating properties. Use of
`conductive metals for either Stop layer would form a ground
`ing plane, thus introducing electrical coupling between
`interconnects on the Same level. For Similar reasons, the
`Vertical extent of the Stop layers formed of only fair insu
`lators should be kept thin So as to reduce the lateral electrical
`conductance. Silicon nitride and related compounds Such as
`Some low-k Silicon-based dielectrics have reasonably high
`resistivities, can be grown in the same chamber as oxides,
`and nitride-Selective oxide etches are known, but it is not
`seen how to form two layers of such materials with vastly
`different etching characteristics while Simultaneously main
`taining high dielectric-to-stopper Selectivity.
`It is thus desired to find a etching process Satisfying these
`difficult and conflicting requirements without unduly com
`plicating and lengthening the dielectric etch Step.
`SUMMARY OF THE INVENTION
`The invention may be Summarized as a plasma etch
`method, preferably performed in a single inductively
`coupled high-density plasma (HDP) reactor, of etching
`through a multi-layer dielectric Stack including an interme
`diate and lower Stop layer. The etch continues through the
`intermediate Stop layer but stops on the lower Stop layer. The
`etch includes at least two Substeps, a earlier one of which is
`non-Selective to the intermediate Stop layer, a later one being
`Selective to the lower Stop layer.
`In a first preferred 2-Substep Sequence: a first, non
`Selective etch extends to below the upper Stop layer; and a
`Second, Selective etch extends to and stops on the lower Stop
`layer. In a Second preferred 3-SubStep Sequence: a first,
`Selective etch on average does not quite reach the upper Stop
`layer; a Second, non-Selective etch punches through the
`upper Stop layer, and a third, Selective etch extends to and
`Stops on the lower Stop layer.
`The invention may be applied to a dielectric Stack Struc
`ture in which the dielectric layers are composed of Silicon
`dioxide or related Silicon oxide materials and the Stop layers
`are composed of Silicon nitride. With these compositions,
`the Stack may be grown in a Single plasma reactor. For a
`Stack of oxide and nitride, the Selective etch may be a
`polymerizing fluorocarbon reactive ion etch and the non
`Selective etch is accomplished by adding an oxygen
`containing gas, Such as CO, to the etching gas mixture.
`In a multi-step etching process, preferably only the gas
`components are changed between the Steps. More
`preferably, the principal etching gas remains Substantially
`the same with only the selective addition of polymer formers
`and oxygen-containing gases, thus providing a Smoother
`transition between the Steps with no fear of extinguishing the
`plasma. The changes in total active gas flow can be easily
`kept below 30%.
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`The etching process is advantageously performed at a
`relatively high pressure in the range of 40 to 150 milliTorr
`or more advantageously in the range of 60 to 100 milliTorr
`in the presence of diluent gas Such as argon having a fraction
`at least twice that of the etching gases.
`Preferably, the selective etch uses both a lean
`hydrofluorocarbon, such as trifluoromethane (CHF), and a
`polymer-forming fluorocarbon or hydrofluorocarbon. The
`Strength of polymerization depends upon the aspect ratio of
`the feature being etched and whether the photoresist needs
`to be protected. The ratio of trifluoromethane to the polymer
`former is preferably in the range of 5 to 20. Preferred
`polymer formers are hexafluoroethane (CF), cyclic
`octafluorobutane (CF), and difluoromethane (CHF),
`dependent upon the geometry of the feature being currently
`etched.
`A hot Silicon Surface may be used to Scavenge fluorine
`from the Selective etching gas to provide yet higher Selec
`tivity to both nitride and photoresist.
`Etching in a high-density plasma enhances polymeriza
`tion to thereby increase Selectivity and crackS CO into
`elemental oxygen, which provides better Selectivity to pho
`toresist than gaseous oxygen.
`The invention is particularly applicable to a counterbore
`dual-damascene etch having two dielectric layers underlaid
`with respective Stop layer. This etch proceSS requires an
`initial very deep via etch through the upper Stop layer and
`both dielectric layers down to the lower stop layer.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is an isometric view of the etched hole required for
`a dual-damascene Via Structure for interconnecting two
`levels of metallization.
`FIG. 2 is a process flow diagram for the counterbore
`dual-damascene etch of the invention.
`FIGS. 3 through 7 are cross-sectional views of the sequen
`tially developed Structure in the counterbore dual
`damascene etch process of FIG. 2.
`FIG. 8 is a cross-sectional view of the metallization
`formed in the dual-damascene etch structure of FIG. 8.
`FIG. 9 is a schematic illustration, partially in cross
`Sectional view, of an inductively coupled high-density
`plasma reactor on which the invention may be practiced.
`FIG. 10 is a process flow diagram for an inventive
`2-Substep form of the via etching Step of the counterbore
`dual-damascene etch process of FIG. 2.
`FIGS. 11 and 12 are cross-sectional views of the sequen
`tially developed Structure in the 2-Substep via etching Step of
`FIG 10.
`FIG. 13 is an optical emission profile for monitoring the
`endpoint of the etching process of FIG. 10.
`FIG. 14 is a process flow diagram for an inventive
`3-substep form of the via etching step of the counterbore
`dual-damascene etch process of FIG. 2.
`FIG. 15 is cross-sectional view of one intermediate struc
`ture in the 3-substep via etch step of FIG. 14.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`We have found that the counterbore process can be
`effectively applied to a dual-damascene Structure by using a
`multi-SubStep etch for the deep via etch Step. The process
`window is improved by the addition of certain gas Species to
`control Selectivity to the Stop layers. In one embodiment of
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1025, IPR2021-00704
`Page 11 of 17
`
`

`

`US 6,399,511 B2
`
`7
`the invention, the damascene Structure incorporates only
`Silicon oxide and Silicon nitride layers, and the deep via etch
`can include features associated with a conventional deep
`contact etch.
`From the View of an integrated process, the counterbore
`damascene method helps to maintain consistent via Sizes.
`The critical dimension at the bottom of the via hole is
`defined during the deep via etch, and any misalignment of
`the trench mask will not affect the via contact area with the
`underlying metal. This insensitivity to misalignment is cru
`cial for via resistance, especially as the Via Size shrinks to
`0.25 um and below. In contrast, the Self-aligned damascene
`proceSS is Susceptible to this misalignment problem, which
`affects the distribution of the via resistance.
`An exemplary unpatterned Structure, as illustrated in FIG.
`3, is tabulated in TABLE 1. This structure was used in an
`example to be described later for a 0.3 um-diameter via.
`
`TABLE 1.
`
`Composition
`
`Thickness
`(nm)
`
`Upper Dielectric
`Upper Stopper
`Lower Dielectric
`Lower Stopper
`
`Oxide
`Nitride
`Oxide
`Nitride
`
`500
`150
`1OOO
`1OO
`
`15
`
`25
`
`8
`supplied with RF power from a first RF power supply 84. A
`silicon ring 86 surrounds the pedestal 82 and is controllably
`heated by an array of heater lamps 88. A grounded silicon
`wall 90 Surrounds the plasma processing area. A Silicon roof
`92 overlies the plasma processing area, and lamps 94 and
`water cooling channels 96 control its temperature. The
`temperature-controlled Silicon ring 86 and to a lesser extent
`the silicon roof 92 can be used to scavenge fluorine from the
`fluorocarbon or other fluorine-based plasma. Processing gas
`is Supplied from one or more bottom gas feeds 94 through
`a bank of mass flow controllers 96. Alternatively, a top gas
`feed may be formed as a small showerhead in the center of
`the Silicon roof 92. An unillustrated vacuum pumping Sys
`tem connected to a pumping channel 98 around the lower
`portion of the chamber maintains the interior of the chamber
`at a preselected pressure. A system controller 100 controls
`the operation of the reactor and its auxiliary equipment.
`In the used configuration, the Silicon roof 92 is grounded,
`but its Semiconductor resistivity and thickneSS are chosen to
`pass generally axial RF magnetic fields produced by an inner
`inductive coil stack 106 and an outer inductive coil stack 108
`powered by respective RF power supplies 110, 112.
`Alternatively, a single RF power Supply may be used in
`conjunction with a Selectable power Splitter. Other coil
`configurations are possible, for example, as in the TCP
`reactor having a flat, Spiral inductive coil overlying the roof
`92.
`The system controller 100 controls the mass flow con
`trollers 96, the heater lamps 88, 94, the supply of chilled
`water to the cooling channels 96, the throttle valve to the
`vacuum pumps, and the power supplies 84, 110, 112. All
`these regulated functions control the etching chemistry in
`conformance to a process recipe of the Sort to be described
`in the examples below. The process recipe is Stored in the
`controller 100 in magnetic, optical, or Semiconductor
`memory, as is well known in the art, and the controller 100
`reads the recipe from a recording medium inserted into it. It
`is typical for the equipment Supplier to provide recipes on
`magnetic media Such as floppy disks or optical media Such
`as CDROMs, which are then read into controller 100.
`A principal advantage of the inductively coupled plasma
`reactor is that different amounts of power can be Supplied to
`the inductive coils 106, 108 and to the capacitive pedestal
`82. The inductive power creates a plasma Source region
`located in large part remotely from the wafer 30 while the
`capacitive power controls the plasma sheath adjacent to the
`wafer 30 and thus determines the DC bias across the sheath
`at the wafer 30. The source power can be raised to increase
`the etching rat