United States Patent (19)
`Hara et al.
`
`USOO5930163A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,930,163
`Jul. 27, 1999
`
`54 SEMICONDUCTOR MEMORY DEVICE
`HAVING TWO P-WELL LAYOUT
`STRUCTURE
`
`75 Inventors: Hiroyuki Hara, Fujisawa, Japan;
`Masataka Matsui, San Jose, Calif.
`Y
`73 Assignee: Kabushiki Kaisha Toshiba, Tokyo,
`Japan
`p
`21 Appl. No.: 08/993,180
`22 Filed:
`Dec. 18, 1997
`9
`30
`Foreign Application Priority Data
`Dec. 19, 1996
`JP
`Japan .................................... 8-339345
`51
`Int. Cl." ..................................................... G11C 11/00
`51
`52 U.S. Cl. ............................................. 365/154; 257/903
`58 Field of Search ..................................... 365/154, 156;
`257/903, 904
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`5,754,468 5/1998 Hobson ................................... 365/154
`Primary Examiner David Nelms
`ASSistant Examiner David Lam
`Attorney, Agent, or Firm-Loeb & Loeb LLP
`57
`ABSTRACT
`This invention relates to P- and N-well regions where
`inverters constituting an SRAM cell are formed. The P-well
`region is divided into two parts, which are laid out on the
`two sides of the N-well region. Boundaries (BL11, BL12)
`are formed to run parallel to bit lines (BL, /BL). With this
`layout, diffusion layers (ND1, ND2) within the P-well
`regions can be formed into simple shapes free from any bent
`portion, reducing the cell area.
`
`13 Claims, 17 Drawing Sheets
`
`-BL2
`BL1 N.
`P - WELL
`P-WELL
`N-WEL
`N4
`: D1
`f
`2xit
`2Y
`s23.5%
`%2% 2.Ée
`(6%Ph3N
`ND1 N
`EY EYE)
`D1N-
`22 N2
`
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`
`
`
`
`
`
`SY
`
`
`
`ha By g
`
`
`
`
`
`Vodd
`
`Vodd
`
`/B
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 1 of 23
`
`

`

`US. Patent
`
`Jul. 27, 1999
`
`Sheet 1 0f 17
`
`5,930,163
`
`
`
`
`
`
`: 714%]
`,
`=W/[f‘flg ND2
`
`
`
`
`_..
`5314?...m 9;?
`
`7/4."_'/// N2-
`
`///I////:: '
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`
`GND m\\
`&\\\\\\
`
`
`
`
`\\\\‘\Vfl
`
`:9«2
`
`
`FIG. 2
`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1023, IPR2021-00704
`
`Page 2 of 23
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 2 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 2 of 17
`
`5,930,163
`
`F7G. 3.(O) " CELL BOUNDARY
`XCONTACT
`
`XCONTACT + v IA 1 + v A 2
`
`FIG. 3(b)ZDiffusion LAYER
`POLYSI L ICON WIRING LAYER
`METAL WIRING LAYER 1
`
`META- WIRING LAYER 2
`FIG. 3(c)
`NMETAL W RING LAYER 3
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 3 of 23
`
`

`

`U.S. Patent
`US. Patent
`
`Jul. 27, 1999
`Jul. 27, 1999
`
`Sheet 3 of 17
`Sheet 3 0f 17
`
`5,930,163
`5,930,163
`
`
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1023, IPR2021-00704
`
`Page 4 of 23
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 4 of 23
`
`

`

`U.S. Patent
`US. Patent
`
`Jul. 27, 1999
`Jul. 27, 1999
`
`Sheet 4 0f 17
`
`Sheet 4 of 17
`
`5,930,163
`5,930,163
`
`EZ-S
`2
`020
`N 2
`-//
`2
`| N. % N 21
`z.
`
`
`
`N
`
`z—.....IN,.....mm7
`rz///////
`.....i
`2 y %
`/'."r/z/fla
`Illill-II_
`2 N.
`71/]!
`Wm
`N---4----
`2
`020
`
`mGR
`
`-
`3.
`
`Petitioner
`
`STMICROELECTRONICS, INC.,
`
`Ex. 1023 , IPR2021-00704
`
`Page 5 of 23
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 5 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 5 of 17
`
`5,930,163
`
`FIG. 6(a)
`
`CELL BOUNDARY
`XCONTACT
`21 v A 1
`NVA 2
`CONTACT -- VIA 1
`XVIA 1 + v A 2
`XCONTACT + v A 1 + v A 2
`
`FIG. 6(b) 2D FFUS ON LAYER
`POLYSI L ICON WIRING LAYER
`METAL WIRING LAYER 1
`
`METAL WIRING LAYER 2
`FIG. 6(c) NMETAL WIRING LAYER 3
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 6 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 6 of 17
`
`5,930,163
`
`BL1 N.
`P-WELL :
`
`
`
`
`
`
`
`
`
`
`
`-BL2
`N-WELL -
`P -WELL
`X 2,
`26N
`Z2
`sé %
`1564
`€
`E. E. E. E.
`%2?
`:
`ck 2 2
`traf2.É.
`P2 2 : ZZ
`
`
`
`
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`
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`
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`
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`
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`
`
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`
`SNNSNN:
`N
`N
`MX1 2S
`Telele
`WL2 xNNNNNN
`"elderlee
`NNNNS
`
`
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`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`BL
`
`Vold
`
`/BL
`
`FIG. 3
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 7 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 7 of 17
`
`5,930,163
`
`cell BouNDARY
`FIG. 9(a)
`XCONTACT
`Zvi A 1
`NVA 2
`CONTACT + v A 1
`bXVIA 1 + VA 2
`XCONTACT + v A 1 + VA 2
`
`FIG. 9(b) 2DIFFUSION LAYER
`POLYSI L CON WIRING LAYER
`METAL WIRING LAYER 1
`
`METAL WIRING LAYER 2
`FIG. 9(c)
`NMETAL WIRING LAYER 3
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 8 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 8 of 17
`
`5,930,163
`
`×N
`
`
`|-N-K) (SDS)()()() ------------------ÈYÈ
`
`
`
`§§
`S?N?S
`N
`
`FIG.
`10
`ARIOR ART
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 9 of 23
`
`

`

`
`
`F76.
`
`77
`
`PRIOR ART
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 10 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 10 Of 17
`
`5,930,163
`
`FIG. 12(a) PRIOR ART
`XCONTACT
`21VIA 1
`NVA 2
`S&Y. CONTACT + v A 1
`XVA 1 + VA 2
`X contact + v A 1 + VA 2
`
`FIG. 12(b) PRIOR ART
`2DIFFUSION LAYER
`POLYSI L I CON WIRING LAYER
`METAL WIRING LAYER 1
`FIG. 12(c) PRIOR ART
`METAL WIRING LAYER 2
`NMETAL W RING LAYER 3
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 11 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 11 of 17
`
`5,930,163
`
`P2
`
`Né:
`
`
`
`CN 2
`
`F/G, 13
`PRIOR ART
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 12 of 23
`
`

`

`U.S. Patent
`US. Patent
`
`Jul. 27,
`
`1999
`
`Sheet 12 0f 17
`
`5,930,163
`
`5,930,163
`
`| Ø
`
`?N
`
`§ZØØØØ% Ø Ø
`\\\\\\\\\A\\\\\wm_'1-__
`
`_VIA-_
`
`_§W\\\\\\\\\\\\\Wm
`\\\\\\\\\\\\\\ww\\\\\\\\\
`
`\\\\\\\\\\\\\\\wV\\\\\\
`
`GND
`
`?º. },
`
`BL
`
`2S |
`/BL
`
`F/G, 14
`FIG. 74
`ARIOR ART
`PRIOR ART
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 13 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 13 Of 17
`
`5,930,163
`
`FIG. 15(a) PRIOR ART
`XCONTACT
`
`S&Y. CONTACT -- V A 1
`XVIA 1 + v A 2
`XCONTACT + v IA 1 + v A 2
`
`FIG. 15(b) PRIOR ART
`2D IFFUSION LAYER
`POLYSI L ICON WIRING LAYER
`METAL WIRING LAYER 1
`FIG. 15(c) PRIOR ART
`METAL WIRING LAYER 2
`NMETAL WIRING LAYER 3
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 14 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 14 of 17
`
`5,930,163
`
`Vodd
`Vodd
`P1 P2
`
`WL
`
`
`
`/BL
`
`IN1
`
`FIG. 17
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 15 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 15 of 17
`
`5,930,163
`
`
`
`
`
`-BL8
`BL7-
`N - WELL
`N-WELL : - P -WELL -
`XZ. t
`-----
`P4
`7 2 2. Ex
`2 2 KN
`XE. E. E.
`E.
`3DT 33
`x 26
`
`
`
`
`
`
`
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`
`
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`
`5X.
`
`2 x
`SY
`
`
`
`
`
`N
`N
`N
`lean
`
`
`
`GND
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 16 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 16 0f 17
`
`5,930,163
`
`is a a a a
`
`is e s p
`
`e s s s
`
`Sey X contacT + v A 1 + VA 2
`FIG. 200b)
`2DIFFUS ON LAYER
`POLYS
`CON WIRING LAYER
`METAL WIRING LAYER 1
`FIG. 200)
`METAL WIRING LAYER 2
`NMETAL WIRING LAYER 3
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 17 of 23
`
`

`

`U.S. Patent
`
`Jul. 27, 1999
`
`Sheet 17 of 17
`
`5,930,163
`
`Vdd
`Vdd
`P1 P2
`N
`
`WL
`
`P4
`
`/BL
`
`/
`N1 N2
`
`P3
`
`BL
`
`
`
`F/G, 22
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 18 of 23
`
`

`

`5,930,163
`
`1
`SEMCONDUCTOR MEMORY DEVICE
`HAVING TWO P-WELL LAYOUT
`STRUCTURE
`
`2
`layer 2 to be parallel to the bit lines BL and /BL. Therefore,
`the layout shown in FIGS. 10 and 11 can be constituted by
`the polysilicon wiring layers PL11 and PL12 and the metal
`wiring layerS 1 and 2.
`This layout is constituted with the minimum area So as to
`make the design Standards (design rule) limited by process
`techniques Satisfy the following conditions.
`(a1) The number of metal wiring layers is limited to one
`Or tWO.
`(a2) The design rules of the minimum line width and
`minimum interval of the metal wiring layer are larger (about
`two times) than those of the polysilicon layer.
`(a3) A contact hole Serving as an opening portion between
`the diffusion layer or the polysilicon wiring layer and the
`metal wiring layer 1, and the first through hole or first via
`hole Serving as an opening portion between the metal wiring
`layerS 1 and 2 do not directly vertically overlap each other.
`Since the area of the contact hole is as large as about two
`times the minimum line width of a normal metal wiring
`layer, many contact holes or through holes are not formed
`within the cell to prevent an increase in cell area.
`(a4) The boundary between the N- and P-well regions is
`present between the P-channel MOS transistor and the
`N-channel MOS transistor. These well regions having dif
`ferent conductivity types are isolated by element isolation
`using LOCOS. Therefore, the isolation width between the P
`and N-well regions must be set much larger (about four
`times) than the element isolation width between well regions
`having the same conductivity type.
`To Satisfy the above conditions, a wiring layer is made of
`a polysilicon film as much as possible, and a wasteful region
`must be effectively utilized Such that complicated wiring
`cross connection is performed in the isolation region
`between the P- and N-well regions.
`However, with the recent advance in proceSS techniques,
`the design rule is changing as follows.
`Along with practical use of chemical mechanical polish
`ing (CMP), a technique of planarizing a metal wiring layer
`advances.
`(b1) Even if the number of metal wiring layers increases
`to three or four, the yield does not greatly decrease.
`(b2) The design rules of the minimum line width and
`minimum interval of the metal wiring layer are almost equal
`to those of the polysilicon layer.
`(c2) A borderless contact technique is introduced, and the
`contact portion can be formed by the same design rule in
`which its area is equal to the minimum line width of the
`metal wiring layer. Further, a Stacked-Via Structure in which
`a contact hole and a through hole are formed to directly
`Vertically overlap each other can be realized.
`In addition, element isolation advances from LOCOS to
`trench isolation (ST1).
`(c1) The isolation width between the P- and N-well
`regions is almost equal to the element isolation width
`between well regions having the Same conductivity type
`(P-well regions or N-well regions).
`Owing to the advance in process techniques, a layout like
`the one shown in FIGS. 10 and 11 is not optimal. For
`example, the polysilicon wiring layers PL11 and PL12 are
`laid out translationally Symmetrical to each other with a T
`shape, resulting in a large wasteful region. Since the
`N-channel MOS transistors N1 and N3 are laid out to be
`perpendicular to each other, the diffusion layer is bent in an
`L shape, and the cell area is wasted.
`FIGS. 13 and 14 show an improvement of the layout
`shown in FIGS. 10 and 11. The basic layout and geometrical
`
`25
`
`BACKGROUND OF THE INVENTION
`The present invention relates to a Semiconductor memory
`device and, more particularly, to the layout of an SRAM
`(Static Random Access Memory) cell having a CMOS
`Structure.
`An SRAM having a CMOS structure is widely used as a
`memory device integrated in a logical IC. As a memory
`element constituting the memory device, the most basic one
`is a 1-port memory cell (SRAM cell) shown in FIG. 16,
`which is constituted by Six transistors.
`15
`A P-channel MOS transistor P1 and an N-channel MOS
`transistor N1 constitute an inverter IN2 in FIG. 17 showing
`an equivalent circuit, whereas a P-channel MOS transistor
`P2 and an N-channel MOS transistor N2 constitute an
`inverter IN1. The inverters IN1 and IN2 have a relationship
`in which their input and output terminals are croSS
`connected to each other. The output terminal of the inverter
`IN1 and the input terminal of the inverter IN2 are connected
`to a bit line BL via a transfer gate transistor N3. The input
`terminal of the inverter IN1 and the output terminal of the
`inverter IN2 are connected to a bit line /BL via a transfer
`gate transistor N4. The gates of the transistors N3 and N4 are
`connected to a word line WL.
`This 6-transistor memory cell has a layout like the one
`shown in FIGS. 10 and 11 showing the layout of a device
`associated with the present invention. FIG. 10 shows an
`underlying layer including a diffusion layer formed on a
`Substrate Surface to constitute a transistor, a polysilicon
`wiring layer formed on the upper Surface of the diffusion
`layer, and a first metal wiring layer 1 formed on the upper
`surface of the polysilicon wiring layer. FIG. 11 shows an
`overlying layer including Second and third metal wiring
`layerS2 and 3 formed on the upper Surface of the underlying
`layer. FIG. 12(a) shows the marks of a contact and a via hole
`used in FIGS. 10 and 11; FIG. 12(b), those of the diffusion
`layer, the polysilicon film, and the metal wiring layer 1, and
`FIG. 12(c), those of the metal wiring layers 2 and 3.
`A boundary BL11 between an N-well region where the
`P-channel MOS transistors P1 and P2 shown in FIG. 10 are
`formed, and a P-well region where the N-channel MOS
`45
`transistors N1 to N4 are formed is present parallel to the
`word line WL shown in FIG. 11. At an upper portion with
`respect to the line A-A parallel to the boundary BL11, a
`polysilicon wiring layer PL11 connected to the gate of the
`transistor P1 and a polysilicon wiring layer PL12 connected
`to the gate of the transistor P2 are laid out translationally
`Symmetrical to each other.
`At a lower portion with respect to the line A-A, a
`diffusion layer DR11 constituting the transistors N1 and N3
`and a diffusion layer DR12 constituting the transistors N2
`and N4 are laid out mirror-symmetrical about the y-axis
`perpendicular to the word line WL.
`As is apparent from FIG. 10, in this layout, the ground line
`GND and the word line WL are formed of the metal wiring
`layers 3, the bit lines BL and /BL are formed of the metal
`wiring layerS 2, and all the remaining portions are made of
`the polysilicon wiring layers PL11 and PL12 and the metal
`wiring layer 1. The metal wiring layer 3 is functionally
`unnecessary because the word line WL made of the poly
`silicon wiring layers PL11 and PL12 is connected across the
`memory cell to a word line WL of another adjacent memory
`cell. The ground line GND can be made of the metal wiring
`
`50
`
`55
`
`60
`
`65
`
`35
`
`40
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 19 of 23
`
`

`

`5,930,163
`
`15
`
`35
`
`40
`
`25
`
`3
`shapes of the transistors N1 to N4 and P1 and P2 are the
`same as those in FIGS. 10 and 11 except that the metal
`wiring layer 2 replaces the polysilicon wiring layerS PL11
`and PL12 cross-connected in the layout shown in FIGS. 10
`and 11, and along with this change, the metal wiring layer 3
`constitutes the bit lines BL and /BL and the ground line
`GND. With the layout shown in FIGS. 13 and 14, the cell
`area decreases by about 10%, compared to the one shown in
`FIGS. 10 and 11.
`Also in the layout shown in FIGS. 13 and 14, however, the
`diffusion layerS respectively constituting the transistorS N1
`and N3 and the transistors N2 and N4 are inevitably formed
`into an L shape, wasting the cell area.
`As described above, the layout of the SRAM cells shown
`in FIGS. 10 to 15 suffers the problems in which the
`geometrical shape Such as the L shape of the diffusion layer
`is wasteful, and the element area is large.
`SUMMARY OF THE INVENTION
`It is, therefore, an object of the present invention to
`provide a layout Structure for a Semiconductor memory
`device in which the element area can be decreased by a
`metal wiring layer Structure made up of three or more layers
`using the most advanced proceSS techniqueS Such as a trench
`element isolation technique and a Stacked-Via Structure.
`According to the present invention, there is provided a
`Semiconductor memory device comprising a first inverter
`including a first N-channel MOS transistor and a first
`P-channel MOS transistor, a second inverter including a
`Second N-channel MOS transistor and a second P-channel
`MOS transistor, and having an input terminal connected to
`an output terminal of the first inverter and an output terminal
`connected to an input terminal of the first inverter, a third
`N-channel MOS transistor having a source connected to the
`output terminal of the first inverter, a drain connected to a
`first bit line, and a gate connected to a word line, and a fourth
`N-channel MOS transistor having a source connected to an
`output terminal of the Second inverter, a drain connected to
`a Second bit line, and a gate connected to the word line,
`wherein a layout direction of a Source and drain of each of
`the first, second, third, and fourth N-channel MOS transis
`tors and the first and second P-channel MOS transistors is set
`parallel to a boundary between a P-well region where the
`first, second, third, and fourth N-channel MOS transistors
`are formed, and an N-Well region where the first and Second
`P-channel MOS transistors are formed.
`The P-well region may be made up of first and second
`well regions, the first and Second P-well regions may be laid
`out on two sides of the N-well region where the first and
`second P-channel MOS transistors are arranged, the first and
`third N-channel MOS transistors may be formed in the first
`P-well region, and the second and fourth N-channel MOS
`transistors may be formed in the Second P-well region.
`A first polysilicon wiring layer used for the gate of the
`third N-channel MOS transistor, and a second polysilicon
`55
`wiring layer used for gates of the first N-channel MOS
`transistor and the first P-channel MOS transistor may be laid
`out parallel to each other, a third polysilicon wiring layer
`used for the gate of the fourth N-channel MOS transistor,
`and a fourth polysilicon wiring layer used for gates of the
`Second N-channel MOS transistor and the second P-channel
`MOS transistor may be laid out parallel to each other, and
`the first and third polysilicon wiring layerS may be formed
`to be isolated from each other, and electrically connected via
`contacts to a metal wiring layer constituting the word line.
`The layout direction of the source and drain of each of the
`first, second, third, and fourth N-channel MOS transistors
`
`45
`
`50
`
`60
`
`65
`
`4
`and the first and second P-channel MOS transistors may be
`set parallel to the bit line.
`In addition, the Second and third polysilicon wiring layers
`may be laid out to align on one Straight line along a direction
`of the word line, and the first and fourth polysilicon wiring
`layerS may be laid out to align on one Straight line along a
`direction of the word line.
`The first and third N-channel MOS transistors may be
`formed in the same diffusion layer within the first P-well
`region, and the second and fourth N-channel MOS transis
`tors may be formed in the same diffusion layer within the
`Second P-well region.
`The first and third N-channel MOS transistors and the first
`P-channel MOS transistor, and the second and fourth
`N-channel MOS transistors and the first P-channel MOS
`transistor are desirably laid out to be point-Symmetrical
`about a center of a memory cell.
`The first and Second bit lines, and a power Supply line
`connected to the Sources of the first and Second P-channel
`MOS transistors may be made of Second metal wiring layers,
`and the word line, and a ground line connected to the Sources
`of the first and second N-channel MOS transistors may be
`made of third metal wiring layers.
`The Semiconductor memory device can have a layout in
`which the first polysilicon wiring layer used for the gate of
`the third N-channel MOS transistor, and the second poly
`Silicon wiring layer used for the gates of the first N-channel
`MOS transistor and the first P-channel MOS transistor are
`laid out parallel to each other, the third polysilicon wiring
`layer used for the gate of the fourth N-channel MOS
`transistor, and the fourth polysilicon wiring layer used for
`the gates of the second N-channel MOS transistor and the
`second P-channel MOS transistor are laid out parallel to
`each other, the word line is divisionally formed by first and
`Second metal wiring layers, and the first and third polysili
`con wiring layers are formed to be isolated from each other,
`and electrically connected via a metal wiring layer and
`contacts to the first and Second metal wiring layers.
`It is also possible that first and Second Sense amplifiers are
`independently connected to the first and Second bit lines, in
`a write, first and Second word lines within the same cell are
`Simultaneously Selected, and in a read, the first and Second
`word lines independently Select different cells, and data read
`from the cells are output from the first and Second Sense
`amplifiers via the first and Second bit lines.
`In the present invention, although the N-channel MOS
`transistors are used as transistors between the first and
`Second inverters and the first and Second bit lines, these
`transistors may be made up of P-channel MOS transistors.
`According to the Semiconductor memory device of the
`present invention, the boundary between the P- and N-well
`regions where the inverters constituting a memory cell are
`formed is laid out parallel to the bit line. Accordingly, a
`diffusion layer in the P- or N-well region, and a cross
`connection portion between the two inverters can be formed
`into Simple shapes free from any bent portion, reducing the
`cell area.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a plan view showing the layout of an underlying
`layer in a Semiconductor memory device according to the
`first embodiment of the present invention;
`FIG. 2 is a plan view showing the layout of an overlying
`layer in the Semiconductor memory device;
`FIG. 3 is an explanatory view showing various marks of
`a contact, a Via, a diffusion layer, and a wiring layer used in
`FIGS. 1 and 2;
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 20 of 23
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`S
`FIG. 4 is a plan view showing the layout of an underlying
`layer in a Semiconductor memory device according to the
`Second embodiment of the present invention;
`FIG. 5 is a plan view showing the layout of an overlying
`layer in the Semiconductor memory device;
`FIG. 6 is an explanatory view showing various marks of
`the contact, the Via, the diffusion layer, and the wiring layer
`used in FIGS. 4 and 5;
`FIG. 7 is a plan view showing the layout of an underlying
`layer in a Semiconductor memory device according to the
`third embodiment of the present invention;
`FIG. 8 is a plan view showing the layout of an overlying
`layer in the Semiconductor memory device;
`FIG. 9 is an explanatory view showing various marks of
`a contact, a Via, a diffusion layer, and a wiring layer used in
`FIGS. 7 and 8;
`FIG. 10 is a plan view showing the layout of an under
`lying layer in a conventional Semiconductor memory device;
`FIG. 11 is a plan view showing the layout of an overlying
`layer in the Semiconductor memory device;
`FIG. 12 is an explanatory view showing various marks of
`a contact, a Via, a diffusion layer, and a wiring layer used in
`FIGS. 10 and 11;
`FIG. 13 is a plan view showing the layout of an under
`lying layer in a Semiconductor memory device associated
`with the present invention;
`FIG. 14 is a plan view showing the layout of an overlying
`layer in the Semiconductor memory device associated with
`the present invention;
`FIG. 15 is an explanatory view showing various marks of
`a contact, a Via, a diffusion layer, and a wiring layer used in
`FIGS. 13 and 14;
`FIG. 16 is a circuit diagram showing the arrangement of
`a normal SRAM cell;
`FIG. 17 is a circuit diagram showing a circuit arrangement
`electrically equivalent to the SRAM cell;
`FIG. 18 is a plan view showing the layout of an under
`lying layer in a Semiconductor memory device according to
`the fourth embodiment of the present invention;
`FIG. 19 is a plan view showing the layout of an overlying
`layer in the Semiconductor memory device;
`FIG. 20 is an explanatory view showing various marks of
`a contact, a Via, a diffusion layer, and a wiring layer used in
`FIGS. 18 and 19;
`FIG. 21 is a circuit diagram showing the circuit arrange
`ment of an SRAM cell in the semiconductor memory device
`according to the fourth embodiment of the present invention;
`and
`FIG.22 is a circuit diagram showing a circuit arrangement
`electrically equivalent to the SRAM cell.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`An embodiment of the present invention will be described
`below with reference to the accompanying drawings.
`FIGS. 1 and 2 show the layout of an SRAM cell consti
`tuting a Semiconductor memory device according to the first
`embodiment of the present invention. FIG. 1 shows an
`underlying layer including a diffusion layer formed on the
`Surface of a Semiconductor Substrate, a polysilicon film
`formed on the upper Surface of the diffusion layer, and a
`metal wiring layer 1. FIG. 2 shows an overlying layer
`including metal wiring layerS 2 and 3 formed on the upper
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`surface of the underlying layer. Various marks in FIG. 3(a)
`denote a cell boundary, a contact, and ViaS 1 and 2; those in
`FIG.3(b), a diffusion layer, a polysilicon film, and the metal
`wiring layer 1; and those in FIG. 3(c), the metal wiring
`layers 2 and 3.
`As shown in FIG. 1, an N-well region where P-channel
`MOS transistors P1 and P2 are formed is laid out at the
`center. A P-well region where N-channel MOS transistors
`N1 and N3 are formed, and a P-well region where N-channel
`MOS transistors N2 and N4 are formed are laid out on the
`two sides of the N-well region.
`The gate of the word line transistor N3 and the gate of the
`transistor N4 which are connected to a word line WL are
`made of isolated polysilicon wiring layers, and Separately
`connected via stacked vias to the word line WL formed of
`the metal wiring layer 3. As shown in FIG. 2, bit lines BL
`and /BL are individually formed of the metal wiring layers
`2. A power Supply line Vdd is formed of the metal wiring
`layer 2 at a central portion between the bit lines BL and /BL
`to be parallel to the bit line. The word line WL is formed of
`the metal wiring layer 3 in a direction perpendicular to the
`bit lines BL and /BL. A ground line GND is formed of the
`two metal wiring layers 3 on the two sides of the word line
`WL to be parallel to the word line WL. The contact of the
`P-well region to the Substrate electrically connects the
`grounded metal wiring layer 3 to the diffusion layer within
`the P-well region through a Stacked-Via Structure made up of
`“contact--Via 1+via 2.
`In the layout shown in FIGS. 10 and 11 or FIGS. 13 and
`14, the boundary BL11 or BL12 between the N- and P-well
`regions runs perpendicular to the bit lines BL and /BL. In the
`layout of the first embodiment, boundaries BL11 and BL12
`between the N- and P-well regions run parallel to the bit
`lines BL and /BL. With this layout, the P-channel MOS
`transistor P1 and the N-channel MOS transistor N1 which
`constitute an inverter over the boundary between the well
`regions having different conductivity types can be laid out
`parallel to the N-channel MOS transistor N3 serving as a
`transfer gate transistor. As a result, an n-type diffusion layer
`ND1 within the P-well region where the transistors N1 and
`N3 are formed, and an n-type diffusion layer ND2 in the
`P-well region where the transistors N2 and N4 are formed
`can be formed straight parallel to the bit lines BL and /BL
`without being bent, preventing generation of a wasteful
`region.
`In the first embodiment, one inverter made up of the
`transistors P1 and N1 and the transfer gate transistor N3, and
`the other inverter made up of the transistors P2 and N2 and
`the transfer gate transistor N4 are respectively arranged
`point-symmetrically about the center of the SRAM cell.
`With this layout, in cross-connecting the two inverters,
`wiring lines internally connecting the gates and drains of the
`transistors P1, P2, N1, and N2 need not be connected to
`croSS the Space, and the wiring region can be reduced.
`A polysilicon wiring layer PL1 for the transistors N1 and
`P1 and a polysilicon wiring layer PL2 for the transistor N4
`can be arranged on one Straight line parallel to the word line
`WL. Similarly, the polysilicon wiring layer PL2 for the
`transistors N3 and P2 and a polysilicon wiring layer PL4 for
`the transistor N2 can be arranged on one Straight line parallel
`to the word line WL. That is, all the polysilicon wiring layers
`PL1 to PL4 and the metal wiring layers 2 and 3 are parallel
`to each other, and the diffusion layers ND1 and ND2 are laid
`out perpendicularly to them, eliminating formation of the
`bent portion present in the conventional layout.
`In this layout, as shown in FIG. 1, two isolation regions
`are present between the two P-well regions and the N-well
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00704
`Page 21 of 23
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`

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`region. However, Since the element isolation width between
`well regions having different conductivity types can be
`decreased to be almost equal to that between well regions
`having the same conductivity type by using a trench element
`isolation technique, an increase in cell area can be Sup
`pressed. As a result, according to the first embodiment, the
`area can be decreased by about 35%, compared to the
`conventional layout shown in FIGS. 10 and 11.
`According to the first embodiment, not only the cell area
`decreases, but also the noise reduces owing to the following
`reason. In the layout according to this embodiment, the
`length in the lateral direction (X direction) of the cell, i.e., the
`length in the direction of the word line WL is relatively
`larger than the length in the longitudinal direction (y
`direction), i.e., the length in the direction of the bit lines BL
`15
`and /BL. This facilitates the layout of sense amplifiers
`arranged every pitch in the X direction of the cell and
`connected to the bit lines BL and /BL.
`Since the cell shape is relatively longer in the X direction
`than in the y direction, the number of cells connected in the
`direction of the word line WL decreases, compared to the
`conventional layout. AS the number of cells connected to one
`word line is Smaller, the cell current flowing in a read
`decreases. Therefore, according to the first embodiment, the
`power consumption can be reduced.
`In a logical IC, many wiring resources in the direction of
`the bit lines BL and /BL per cell can be obtained due to the
`following reason though a bus line often runs using the
`fourth metal wiring layer on the memory cell. More
`Specifically, when the bus line runs on the memory cell, if
`the bit lines BL and /BL and the bus line are laid out to run
`Vertically parallel to each other over a long distance, a
`change in Signal on the bus line becomes capacitive coupling
`noise, which is superposed on the bit lines BL and /BL to
`cause an operation error. In the first embodiment, Since the
`bus line is laid out parallel to the bit lines BL and /BL except
`for portions immediately above the bit lines BL and /BL,
`such an operation error can be prevented. The bit lines BL
`and /BL are made of the metal wiring layerS 2. The ground
`40
`line GND and the word line WL made of the metal wiring
`layers 3 are present between the bit lines BL and /BL, and
`a bus line made of a metal wiring layer 4 and running on the
`memory cell, and function as a metal blocking layer. For this
`reason, occurrence of an operation error can be reliably
`prevented.
`FIGS. 4 and 5 show the layout of a semiconductor
`memory device according to the Second embodiment of the
`present invention. Marks used are shown in FIGS. 6(a) to
`6(c).
`The second embodiment is different from the first
`embodiment in that a region where a word line WL formed
`of a metal wiring layer 3 contacts a polysilicon wiring layer
`is Set in a P-well region, and a ground line GND and a power
`Supply line Vdd made of metal wiring layerS 2 are arranged
`parallel to bit lines BL and /BL. The layout according to the
`Second embodiment is Suitable for the case wherein the
`isolation width of the well region is relatively larger than the
`element isolation width. In addition to the above effects of
`the first embodiment, the following effects unique to the
`Second embodiment can be obtained.
`When the power supply line Vdd and the ground line
`GND are laid out parallel to the word line WL, a current
`flowing through all cells connected to a Selected word line
`flows into one power Supply line Vdd and one ground line
`GND. To the contrary, if the power supply line Vdd and the
`ground line GND run parallel to the bit lines B