(12) United States Patent
`Nii et al.
`
`USOO6347062B2
`US 6,347,062 B2
`(10) Patent No.:
`Feb. 12, 2002
`(45) Date of Patent:
`
`(54) SEMICONDUCTOR MEMORY DEVICE
`(75) Inventors: Koji Nii; Atsushi Miyanishi, both of
`Tokyo (JP)
`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/824,008
`(22) Filed:
`Apr. 3, 2001
`(30)
`Foreign Application Priority Data
`May 16, 2000 (JP) ....................................... 2000-143861
`Jan. 11, 2001
`(JP) ....................................... 2001-0035OO
`5
`Int. Cl."
`G11C 11/00
`1.
`nt. Cl. ................................................
`(52) U.S. Cl. ..................... 365/230.05; 365/51; 365/154
`(58) Field of Search ............................ 365/230.05, 154,
`365/51, 63, 156
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,561,638 A
`10/1996 Gibson et al. ......... 365/230.05
`5,742,557 A
`4/1998 Gibbins et al. ........ 365/230.05
`5,886,919 A 3/1999 Morikawa .................... 365/51
`6,078,544 A 6/2000 Park ............... ... 365/230.05
`6.288,969 B1 * 9/2001 Gibbins et al. ........ 365/230.05
`FOREIGN PATENT DOCUMENTS
`
`
`
`1/1995
`4/1995
`10/1997
`6/1998
`
`T-7089
`JP
`7-106438
`JP
`9-270468
`JP
`10-178110
`JP
`* cited by examiner
`Primary Examiner Son T. Dinh
`(74) Attorney, Agent, or Firm-Leydig, Voit & Mayer, Ltd.
`(57)
`ABSTRACT
`In the construction of a P-well area including a pair of
`CMOS inverters and a N-well area of a multi-port SRAM
`cell, the P-well area is divided into two P-well areas. These
`two P-well areas are disposed on two sides of the N-well
`area. A layout is provided Such that the boundaries between
`the P-well areas and the N-well area are parallel to bit lines.
`Two access gates are located in one P-well area and two
`acceSS gates are located in the other P-well area. Thus, the
`bit lines can be made shorter, and the amount of wiring can
`be reduced.
`
`5,338.963 A 8/1994 Klassen et al. ............. 257/376
`
`27 Claims, 22 Drawing Sheets
`
`BLOO BL 10
`
`BLO1 BL 11
`
`
`
`WLO
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 1 of 42
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`

`

`U.S. Patent
`US. Patent
`
`Feb. 12, 2002
`Feb. 12, 2002
`
`Sheet 1 of 22
`Sheet 1 0f 22
`
`US 6,347,062 B2
`US 6,347,062 B2
`
`
`
`WLO
`
`BL11
`
`BLO1
`
`BLOOBL1O
`
`FIG.1
`
`:
`
`Petitioner STMICROELECTRONICS, INC.,
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`Ex. 1021, IPR2021-00704
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`Petitioner STMICROELECTRONICS, INC.,
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`U.S. Patent
`US. Patent
`
`Feb. 12, 2002
`Feb. 12, 2002
`
`Sheet 2 of 22
`Sheet2 0f22
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`US 6,347,062 132
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`
`Petitioner STMICROELECTRONICS, INC.,
`
`Ex. 1021, IPR2021-00704
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`Page 3 of 42
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
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`U.S. Patent
`US. Patent
`
`Feb. 12, 2002
`Feb. 12, 2002
`
`Sheet 3 of 22
`Sheet 3 0f 22
`
`US 6,347,062 B2
`US 6,347,062 B2
`
`
`
`AL18
`
`FIG.3
`
`Petitioner STMICROELECTRONICS, INC.,
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`Ex. 1021, IPR2021-00704
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`Page 4 of 42
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`Petitioner STMICROELECTRONICS, INC.,
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`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 4 of 22
`
`US 6,347,062 B2
`
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 5 of 42
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`U.S. Patent
`US. Patent
`
`Feb. 12, 2002
`Feb. 12, 2002
`
`Sheet 5 0f 22
`Sheet 5 of 22
`
`US 6,347,062 B2
`US 6,347,062 B2
`
`
`
`FIG.5
`
`Petitioner STMICROELECTRONICS, INC.,
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`Ex. 1021, IPR2021-00704
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`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 6 of 22
`
`US 6,347,062 B2
`
`FIG.6
`
`CONTACT HOLE
`X FIRST VIA HOLE
`KX SECOND VIA HOLE
`X CONTACT HOLE PLUS FIRST VIA HOLE
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 7 of 42
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`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 7 of 22
`
`US 6,347,062 B2
`
`
`
`WAN
`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 8 of 42
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`

`

`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 8 of 22
`
`US 6,347,062 B2
`
`WW
`
`VDD
`ZY
`\
`
`VDD
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`
`RBL
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 9 of 42
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`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 9 of 22
`
`US 6,347,062 B2
`
`
`
`[55]
`
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`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 10 of 42
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`

`

`U.S. Patent
`US. Patent
`
`Feb. 12, 2002
`Feb. 12, 2002
`
`Sheet 10 of 22
`Sheet10 0f22
`
`US 6,347,062 B2
`US 6,347,062 132
`
`
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
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`Ex. 1021, IPR2021-00704
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`Page 11 0f 42
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`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 11 of 22
`
`US 6,347,062 B2
`
`ZZTIV
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 12 of 42
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`

`

`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 12 of 22
`
`US 6,347,062 B2
`
`
`
`Z£TV
`
`(TNAH)
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 13 of 42
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`

`

`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 13 of 22
`
`US 6,347,062 B2
`
`FIG.13
`
`
`
`WWL
`
`WBL1
`
`WBL2
`
`N1
`
`N2
`
`RWL2
`- 1
`
`RBL2
`
`N11
`
`RWL
`- r.
`
`N9
`
`RBL 1
`
`N1 O-
`
`N8
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 14 of 42
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`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 14 of 22
`
`US 6,347,062 B2
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`TITE NA NTT|E|WA CH
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 15 of 42
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`

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`U.S. Patent
`US. Patent
`
`Feb. 12, 2002
`Feb. 12, 2002
`
`Sheet 15 of 22
`SheetlS 0f22
`
`US 6,347,062 B2
`US 6,347,062 132
`
`
`
`
`
`/ | TV/
`
`Petitioner STMICROELECTRONICS, INC.,
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`Ex. 1021, IPR2021-00704
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`Page 16 0f 42
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`U.S. Patent
`US. Patent
`
`b.eF
`
`US 6,347,062 B2
`US 6,347,062 132
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`Petitioner STMICROELECTRONICS, INC.,
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`Ex. 1021, IPR2021-00704
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`Page 17 of 42
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`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 17 of 22
`
`US 6,347,062 B2
`
`(ZTWAH)99TIV
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 18 of 42
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`

`

`U.S. Patent
`
`Feb. 12, 2002
`
`Sheet 18 of 22
`
`US 6,347,062 B2
`
`F.G. 18
`
`
`
`WWL
`
`WBL1
`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 19 of 42
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`US. Patent
`
`2
`
`US 6,347,062 132
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`Petitioner STMICROELECTRONICS, INC.,
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`U.S. Patent
`US. Patent
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`Feb. 12, 2002
`Feb. 12, 2002
`
`Sheet 20 0f 22
`Sheet 20 of 22
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`US 6,347,062 B2
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`Ex. 1021, IPR2021-00704
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`U.S. Patent
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`Feb. 12, 2002
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`Sheet 21 of 22
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`US 6,347,062 B2
`
`FIG21
`
`P WELL
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`N WELL
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
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`U.S. Patent
`US. Patent
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`Feb. 12, 2002
`Feb. 12, 2002
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`Sheet 22 of 22
`Sheet 22 0f 22
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`US 6,347,062 B2
`US 6,347,062 B2
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`
`
`
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`Petitioner STMICROELECTRONICS, INC.,
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`Ex. 1021, IPR2021-00704
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`

`1
`SEMCONDUCTOR MEMORY DEVICE
`
`FIELD OF THE INVENTION
`The present invention relates to a Semiconductor memory
`device. More particularly this invention relates to a layout of
`a multi-port SRAM (Static Random Access Memory) cell
`having CMOS construction.
`BACKGROUND OF THE INVENTION
`In recent years, there has been an increasing demand for
`a high-Speed processing of electronic devices along with a
`reduction in weigh and sizes of these devices. The mounting
`of microcomputers on these electronic devices is now
`unavoidable. It is also essential to install large-capacity and
`high-Speed processing memories on these microcomputers.
`Further, along with a rapid distribution of high-performance
`personal computers, there has also been an increasing
`demand for large-capacity cache memories. In other words,
`RAMs that are used by the CPU to execute control programs
`are required to have a large capacity with high-Speed pro
`cessing.
`DRAM (Dynamic RAM) and SRAM are generally used
`as a RAM. Particularly, SRAM is generally used for cache
`memories and the like that require high-Speed processing.
`The SRAM is known to have a high-resistance load type
`memory cell and a CMOS type memory cell. The high
`resistance load type is constructed of four transistors and
`two high-resistance elements. The CMOS type is con
`Structed of Six transistors. Because of very Small leakage
`current during data holding, the CMOS type SRAM has high
`reliability and is used as the main kind of SRAM at present.
`Generally, a reduction in the area of the memory cell
`means not only a reduction in the size of the memory cell
`array but also a realization of high-Speed processing. In
`order to achieve a higher-speed operation of the SRAM than
`in the past, various layout proposals have been made So far.
`For example, according to the Semiconductor memory
`device disclosed in Japanese Patent Application Laid-Open
`(JP-A) No. 10-178110, P-well areas and N-well area formed
`with inverters that constitute a memory cell are disposed So
`that their boundary lines are parallel with bit lines. Based on
`this arrangement, diffusion areas within the P-well areas and
`the N-well area and a cross-connected portion of two
`inverters are formed in Simple shapes respectively having no
`bending. As a result, the cell area is reduced.
`FIG. 21 and FIG.22 are layout diagrams of the semicon
`ductor memory device disclosed in Japanese Patent Appli
`cation Laid-Open (JP-A) No. 10-178110. FIG. 21 shows
`diffusion areas formed on the Surface of a Semiconductor
`Substrate, a polycrystalline Silicon film formed on the dif
`fusion areas, and a ground including a first metal-wiring
`layer. FIG.22 shows an upper ground including Second and
`third metal-wiring layers formed on the upper layer.
`As shown in FIG. 21, in the center of the memory cell,
`there is disposed the N-well area in which P-channel type
`MOS transistors P101 and P102 are formed. On both sides
`of this N-well area, there are formed P-well areas in which
`N-channel type MOS transistors N101 and N103, and N102
`and N104 are formed respectively.
`The P-channel type MOS transistors P101 and P102 and
`the N-channel type MOS transistors N101 and N102 are
`mutually cross connected to form a CMOS inverter, that is,
`a flip-flop circuit. The N-channel type MOS transistors N103
`and N104 correspond to an access gate (a transfer gate).
`As shown in FIG. 22, bit lines BL and /BL are separately
`formed as second metal-wiring layers. The bit lines BL and
`
`15
`
`25
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`35
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`40
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`45
`
`50
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`55
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`60
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`65
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`US 6,347,062 B2
`
`2
`/BL are connected to one end of Semiconductor terminals of
`the lower-layer access gate MOS transistors N103 and N104
`respectively. A power Source line Vdd is formed as a Second
`metal-wiring layer in the center between the bit lines BL and
`/BL in parallel with these bit lines. The power source line
`Vdd is connected to one of Semiconductor terminals of the
`lower-layer P-channel type MOS transistors P101 and P102.
`A word line WL is formed as a third metal-wiring layer in
`a direction orthogonal with the bit lines BL and /BL. The
`word line WL is connected to gates of the lower-layer
`N-channel type MOS transistor N103 and N104. Two
`ground lines GND are formed as third metal-wiring layers
`on both sides of the word line WL in parallel with this word
`line.
`AS a result of forming the memory cell in this layout, an
`N-type diffusion area within the P-well area in which the
`MOS transistors N103 and N103 are located and an N-type
`diffusion area in which the MOS transistors N102 and N104
`are located can be linear and parallel to the bit lines BL and
`/BL. This construction can prevent occupation of an unnec
`eSSary area.
`The length of the cell in a lateral direction, that is, the
`length of the word line WL, is larger than the length of the
`cell in a longitudinal direction, that is, the length of the bit
`lines BL and /BL. Therefore, it becomes easy to provide a
`layout of a Sense amplifier connected to the bit lines BL and
`/BL. At the same time, the number of cells to be connected
`to one word line can be reduced. As a result, it is possible to
`reduce a cell current that flows during the reading. In other
`words, it is possible to reduce power consumption.
`The above-described SRAM memory cell is an example
`of what is called one-port SRAM. In recent years, there has
`been introduced a multi-processor technique for achieving
`high-Speed processing of computers. Based on this
`technique, a plurality of CPUs are required to share one
`memory area. In this aspect, various layouts have been
`proposed for a multi-port SRAM that makes it possible to
`have access to CPUs from two ports to the one memory cell.
`For example, according to the memory cell disclosed in
`Japanese Patent Application Laid-Open (JP-A) No. 07-7089,
`a multi-port SRAM construction is realized by disposing a
`Second port in Symmetry with a first port on the Same layer
`and by having the two ports formed at the same time. FIG.
`23 shows the layout of the memory cell disclosed in Japa
`nese Patent Application Laid-Open (JP-A) No. 07-7089.
`As shown in FIG. 23, P-channel type MOS transistors
`P201 and P202 and N-channel type MOS transistors N201",
`N202', N201" and N202" are mutually cross connected to
`form a CMOS inverter, that is, a flip-flop. N-channel type
`MOS transistors NA, NB, NA2 and NB2 correspond to
`access gates (transfer gates).
`In other words, N-channel type MOS transistors NA and
`NB make it possible to have an acceSS from one gate via a
`word line WL1, and N-channel type MOS transistors NA2
`and NB2 make it possible to have an access from the other
`gate via a word line WL2.
`Conventional memory cells have a disadvantage that the
`amount of wiring of the bit lines is large and a delay
`increases, as the memory cell has a larger length in the
`direction of the bit lines. The semiconductor memory device
`disclosed in Japanese Patent Application Laid-Open (JP-A)
`No. 10-178110 solves this problem for one-port SRAM.
`However, this Semiconductor memory device does not
`solve the above problem for a multi-port SRAM generally
`having two Sets of acceSS gates and a drive-type MOS
`transistor. The memory cell disclosed in Japanese Patent
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 24 of 42
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`

`3
`Application Laid-Open (JP-A) No. 07-7089 shows a layout
`of a multi-port SRAM cell. However, this provides the
`layout for making it easy to add a Second port without
`generating a large change in the layout of the one-port
`SRAM cell. This layout does not reduce the size of the
`multi-port SRAM cell in the direction of the bit lines.
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide a
`Semiconductor memory device having a memory cell with a
`Short length in the direction of bit lines, in the construction
`of a P-well area formed with a pair of CMOS inverters and
`a N-well area that constitute a multi-port SRAM cell. In the
`Semiconductor memory device of the present invention, the
`P-well area is divided into two P-well areas. The two P-well
`areas are disposed on the two sides of the N-well area. The
`boundaries between P and N-well areas are parallel to the bit
`lines, and a pair of access gates are formed in each of the two
`P-well areas.
`In the Semiconductor memory device according to one
`aspect of the present invention, two P-well areas are pro
`vided on the two sides of the N-well area, three (first, third
`and fifth) N-channel type MOS transistors are electrically
`connected to the positive-phase bit line and are formed in
`one P-well area, and three (Second, fourth and Sixth)
`N-channel type MOS transistors are connected to the
`negative-phase bit line and are formed in the other P-well
`area. The P-well areas and the N-well area are disposed in
`a direction perpendicular to the positive-phase and negative
`phase bit lines. Therefore, it is possible to provide a layout
`that requires shorter bit lines.
`Further, the first and second P-well areas are formed on
`both sides of the N-well area. According, it is possible to
`make uniform the distances of wiring connection between
`the N-channel type MOS transistors formed in the first and
`second P-well areas respectively and the P-channel type
`MOS transistors formed in the N-well area.
`Further, the first positive-phase bit line, first negative
`phase bit line, the Second positive-phase bit line, and the
`Second negative-phase bit line extend parallel to boundary
`lines between the first and second P-well areas and the
`N-Well area respectively. According, it is possible to provide
`a layout having each bit line formed in a shortest length by
`taking into consideration a reduction in the length of each
`word line.
`Further, the boundary lines between the first and second
`P-well areas and the N-well area are perpendicular to the
`direction in which the first and second word lines extend.
`Accordingly, it is possible to provide a layout having each
`word line formed in a shortest length by taking into con
`sideration a reduction in the length of each bit line with
`priority.
`Further, the first P-channel type MOS transistor and the
`first, third and fourth N-channel type MOS transistors are
`formed So that respective gate areas are parallel with the
`extension direction of the first word line and are positioned
`on the Same Straight line, and the Second P-channel type
`MOS transistor and the second, fifth and sixth N-channel
`type MOS transistors are formed So that respective gate
`areas are parallel with the extension direction of the Second
`word line and are positioned on the same Straight line.
`Accordingly, it is possible to form wires for connecting
`between the gates in a Straight-line shape. Further, as the
`second P-channel type MOS transistor and the gate areas of
`the second, fifth and sixth N-channel type MOS transistors
`are positioned on the same Straight line, it is possible to form
`wires for connecting between the gates in a Straight-line
`shape.
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`Further, the third and fifth N-channel type MOS transis
`tors are formed in Such a manner that respective Source
`diffusion areas and drain diffusion areas are positioned on
`the same Straight line, and are also disposed in parallel with
`the directions of the extension of the first and second
`positive-phase bit lines. In addition, the fourth and Sixth
`N-channel type MOS transistors are formed in such a
`manner that respective Source diffusion areas and drain
`diffusion areas are positioned on the same Straight line, and
`are also disposed in parallel with the directions of the
`extension of the first and Second negative-phase bit lines.
`Further, drain diffusion areas of the third and fifth
`N-channel type MOS transistors are formed in a common
`first n diffusion area, and drain diffusion areas of the fourth
`and sixth N-channel type MOS transistors are formed in a
`common Second n diffusion area. Accordingly, it is possible
`to reduce the size of the n" diffusion areas.
`Further, drain diffusion area of the first N-channel type
`MOS transistor and drain diffusion areas of the third and
`fifth N-channel type MOS transistors are connected to each
`other by an upper-layer first metal-wiring layer via contact
`holes, and a drain diffusion area of the Second N-channel
`type MOS transistor and drain diffusion areas of the fourth
`and sixth N-channel type MOS transistors are connected to
`each other by an upper-layer Second metal-wiring layer via
`contact holes. Accordingly, it is possible to form the first and
`Second metal-wiring layers in a Straight-line shape according
`to the positions of the drain diffusion areas.
`Further, the extension direction of the first and second
`metal-wiring layerS is parallel with the extension direction
`of the first and Second word lines. Accordingly, it is possible
`to optimize the length of the metal-wiring layers like the
`word lines.
`Further, extension directions of the first and Second
`positive-phase bit line, the first and Second negative-phase
`bit lines, the power source line and the GND line respec
`tively are perpendicular to the first and Second word lines.
`Accordingly, it is possible to minimize the respective length
`of these lines.
`Further, drain diffusion areas of the first, third and fifth
`N-channel type MOS transistors are formed in a common
`first n diffusion area, and drain diffusion areas of the
`second, fourth and sixth N-channel type MOS transistors are
`formed in a common Second n diffusion area. Accordingly,
`it is possible to omit the metal-wiring layers between these
`drain diffusion areas.
`Further, the first n diffusion area and a drain diffusion
`area of the first P-channel type MOS transistor are connected
`to each other by an upper-layer first metal-wiring layer via
`contact holes, and the Second n diffusion area and a drain
`diffusion area of the second P-channel type MOS transistor
`are connected to each other by an upper-layer Second
`metal-wiring layer via contact holes. Accordingly, it is
`possible to form the metal-wiring layers in a Straight-line
`shape according to the positions of the drain diffusion areas
`and the n diffusion areas.
`The Semiconductor memory device according to another
`aspect of the present invention comprises a first word line,
`a Second word line, a first positive-phase bit line, a first
`negative-phase bit line, and a Second positive-phase bit line;
`a first CMOS inverter that structures a CMOS inverter by
`including a first N-channel type MOS transistor and a first
`P-channel type MOS transistor; a second CMOS inverter
`that structures a CMOS inverter by including a second
`N-channel type MOS transistor and a second P-channel type
`MOS transistor, and that has an input terminal of the CMOS
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 25 of 42
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`US 6,347,062 B2
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`inverter connected to an output terminal of the first CMOS
`inverter as a first memory node, and has an output terminal
`of the CMOS inverter connected to an input terminal of the
`first CMOS inverter as a second memory node; a third
`N-channel type MOS transistor that has a gate connected to
`the first word line, has a drain connected to the first
`positive-phase bit line, and has a Source connected to the
`first memory node; a fourth N-channel type MOS transistor
`that has a gate connected to the first word line, has a drain
`connected to the first negative-phase bit line, and has a
`Source connected to the Second memory node, a fifth
`N-channel type MOS transistor that has a gate connected to
`the first memory node; and a sixth N-channel type MOS
`transistor that has a gate connected to the Second word line,
`has a drain connected to the Second positive-phase bit line,
`and has a Source connected to a drain of the fifth N-channel
`type MOS transistor. In addition, first and second P-channel
`type MOS transistors are formed in an N-well area, the first
`and third N-channel type MOS transistors are formed in a
`first P-well area, and the second, fourth, fifth and sixth
`N-channel type MOS transistors are formed in a second
`P-well area.
`Further, the Semiconductor memory device further com
`prises a third word line, a first positive-phase line, and a
`Second negative-phase bit line; a Seventh N-channel type
`MOS transistor that has a gate connected to the Second
`memory node; and an eighth N-channel type MOS transistor
`that has a gate connected to the third word line, has a drain
`connected to the Second negative-phase bit line, and has a
`Source connected to a drain of the Seventh N-channel type
`MOS transistor. The seventh and eighth N-channel type
`MOS transistors are formed in the first P-well area.
`Further, the second and third word lines are formed as one
`common word line.
`Further, the first and second P-well areas are formed at
`both sides of the N-well area.
`Further, the respective directions of the extensions of the
`first positive-phase bit line, the first negative-phase bit line,
`and the Second positive-phase bit line are parallel with a
`boundary line between the first and second P-well areas and
`the N-well area.
`Further, a boundary line between the first and second
`P-well areas and the N-well area is orthogonal with direc
`tions of respective extensions of the first and Second word
`lines.
`Further, the first P-channel type MOS transistor, and the
`first, fourth and sixth N-channel type MOS transistors are
`formed Such that their respective gate areas are positioned
`on the same Straight line, and are also disposed in parallel
`with the direction of the extension of the first word line.
`Further, the second P-channel type MOS transistor, and the
`second, third and fifth N-channel type MOS transistors are
`formed Such that their respective gate areas are positioned
`on the same Straight line, and are also disposed in parallel
`with the direction of the extension of the second word line.
`Further, the first and third N-channel type MOS transis
`tors are formed Such that a drain diffusion area of the first
`N-channel type MOS transistor and a source diffusion area
`of the third N-channel type MOS transistor are positioned on
`the same Straight line, and also disposed in parallel with the
`direction of the extension of the first positive-phase bit line.
`Further, the second and fourth N-channel type MOS tran
`Sistors are formed Such that a drain diffusion area of the
`second N-channel type MOS transistor and a source diffu
`sion area of the fourth N-channel type MOS transistor are
`positioned on the same Straight line, and also disposed in
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`parallel with the direction of the extension of the first
`negative-phase bit line. Further, the fifth and sixth N-channel
`type MOS transistors are formed such that a drain diffusion
`area of the fifth N-channel type MOS transistor and a source
`diffusion area of the sixth N-channel type MOS transistor are
`positioned on the same Straight line, and also disposed in
`parallel with the direction of the extension of the second
`positive-phase bit line.
`Further, a drain diffusion area of the first N-channel type
`MOS transistor and a source diffusion area of the third
`N-channel type MOS transistor are formed in a common first
`n" diffusion area. Further, a drain diffusion area of the
`second N-channel type MOS transistor and a source diffu
`sion area of the fourth N-channel type MOS transistor are
`formed in a common Second n diffusion area. Further, a
`drain diffusion area of the fifth N-channel type MOS tran
`Sistor and a Source diffusion area of the Sixth N-channel type
`MOS transistor are formed in a common third n diffusion
`aca.
`Further, the second P-channel type MOS transistor, and
`the second and fifth N-channel type MOS transistors have
`their respective gate areas connected by a Straight line
`shaped common polysilicon wiring.
`Further, the directions of the extensions of the first and
`Second positive-phase bit lines, the first negative-phase bit
`line, a power Source line, and a GND line respectively are
`perpendicular to the first and Second word lines.
`Further, the first P-channel type MOS transistor, and the
`first, fourth, sixth and seventh N-channel type MOS tran
`Sistors are formed Such that their respective gate areas are in
`parallel with the direction of the extension of the first word
`line, and are also positioned on the same Straight line.
`Further, the second P-channel type MOS transistor, and the
`second, third, fifth and eighth N-channel type MOS transis
`tors are formed Such that their respective gate areas are in
`parallel with the direction of the extension of the second
`word line, and are also positioned on the same Straight line.
`Further, the first and third N-channel type MOS transis
`tors are formed Such that a drain diffusion area of the first
`N-channel type MOS transistor and a source diffusion area
`of the third N-channel type MOS transistor are in parallel
`with the direction of the extension of the first positive-phase
`bit line, and are also positioned on the Same Straight line.
`Further, the second and fourth N-channel type MOS tran
`Sistors are formed Such that a drain diffusion area of the
`second N-channel type MOS transistor and a source diffu
`sion area of the fourth N-channel type MOS transistor are in
`parallel with the direction of the extension of the first
`negative-phase bit line, and are also positioned on the same
`straight line. Further, the fifth and sixth N-channel type
`MOS transistors are formed Such that a drain diffusion area
`of the fifth N-channel type MOS transistor and a source
`diffusion area of the sixth N-channel type MOS transistor are
`in parallel with the direction of the extension of the second
`positive-phase bit line, and are also positioned on the same
`Straight line. Further, the Seventh and eighth N-channel type
`MOS transistors are formed Such that a drain diffusion area
`of the seventh N-channel type MOS transistor and a source
`diffusion area of the eighth N-channel type MOS transistor
`are in parallel with the direction of the extension of the
`Second negative-phase bit line, and are also positioned on
`the same Straight line.
`Further, a drain diffusion area of the first N-channel type
`MOS transistor and a source diffusion area of the third
`N-channel type MOS transistor are formed in a common first
`n" diffusion area. Further, a drain diffusion area of the
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1021, IPR2021-00704
`Page 26 of 42
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`second N-channel type MOS transistor and a source diffu
`sion area of the fourth N-channel type MOS transistor are
`formed in a common Second n diffusion area. Further, a
`drain diffusion area of the fifth N-channel type MOS tran
`Sistor and a Source diffusion area of the Sixth N-channel type
`MOS transistor are formed in a common third n diffusion
`area. Further, a drain diffusion area of the seventh N-channel
`type MOS transistor and a source diffusion area of the eighth
`N-channel type MOS transistor are formed in a common
`fourth n diffusion area.
`Further, the second P-channel type MOS transistor, and
`the second and fifth N-channel type MOS transistors have
`their respective gate areas connected by a Straight line
`shaped common first polysilicon wiring. Further, the first
`P-channel type MOS transistor, and the first and seventh
`N-channel type MOS transistors have their respective gate
`areas connected by a Straight line-shaped common Second
`polysilicon wiring.
`Other objects and features of this invention will become
`apparent from the following description with reference to
`the accompanying drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a diagram showing an equivalent circuit of a
`Semiconductor memory device according to a first embodi
`ment of the present invention.
`FIG. 2 is a diagram showing an example of the layout of
`a memory cell of the Semiconductor memory device accord
`ing to the first embodiment.
`FIG. 3 is a diagram Showing an another example of the
`layout of the memor