Trials@uspto.gov Paper 7
`571-272-7822
`Entered: August 2, 2021
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`STMICROELECTRONICS, INC.,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2021-00704
`Patent 6,534,805 C1
`
`
`
`
`
`
`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`HORVATH, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`Granting Motion for Joinder
`35 U.S.C. § 315(c); 37 C.F.R. § 42.122
`
`
`
`
`
`
`
`
`571-272-7822
`Entered: August 2, 2021
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`STMICROELECTRONICS, INC.,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2021-00704
`Patent 6,534,805 C1
`
`
`
`
`
`
`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`HORVATH, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`Granting Motion for Joinder
`35 U.S.C. § 315(c); 37 C.F.R. § 42.122
`
`
`
`
`
`
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`
`I.
`
`INTRODUCTION
`A. Background
`STMicroelectronics, Inc., (“Petitioner”) filed a Petition requesting
`inter partes review of claims 7–29, 30–32, and 53–61 (“the challenged
`claims”) of U.S. Patent No. 6,534,805 C1 (Ex. 1001, “the ’805 patent”).
`Paper 1 (“Pet.”) 5–6. Concurrently, Petitioner filed a Motion for Joinder
`seeking to be joined as a party to Qualcomm, Inc. v. Monterey Research,
`LLC, IPR2020-01491 (PTAB Mar. 8, 2021) (“the QCOM IPR”). Paper 3
`(“Mot.”). Monterey Research, LLC (“Patent Owner”) elected not to file a
`Preliminary Response to the Petition and did not oppose the Motion for
`Joinder. We have authority and jurisdiction under 35 U.S.C. §§ 6, 314 and
`37 C.F.R. § 42.4.
`For the reasons discussed below, we determine institution inter partes
`review is warranted on the same grounds instituted in the QCOM IPR, and
`grant Petitioner’s Motion for Joinder.
`B. Real Parties-in-Interest
`Petitioner identifies itself, STMicroelectronics N.V., and
`STMicroelectronics International N.V. as the real parties-in-interest. Pet. 3.
`Patent Owner identifies itself and IPValue Management as real parties-in-
`interest. Paper 4, 1.
`
`C. Related Matters
`The parties identify the following as matters that can affect or be
`affected by this proceeding: Monterey Research, LLC v. Advanced Micro
`Devices, Inc., No. 1:19-cv-02149 (D. Del. 2019); Monterey Research, LLC
`v. Marvell Tech. Grp. Ltd., No. 1:20-cv-00158 (D. Del. 2020); Monterey
`Research, LLC v. Qualcomm, Inc., No. 1:19-cv02083 (D. Del. 2019);
`Marvell Semiconductor, Inc. v. Monterey Research, LLC, No. 3:20-cv-03296
`
`2
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`(N.D. Cal. 2020); Monterey Research, LLC v. STMicroelectronics, Inc.,
`No. 1:20-cv-00089 (D. Del. 2020); Advanced Micro Devices, Inc. v.
`Monterey Research, LLC, IPR2020-00990 (PTAB Dec. 2, 2020); and
`Qualcomm, Inc. v. Monterey Research, LLC, IPR2020-01491 (PTAB Mar.
`8, 2021). Pet. 2–3; Paper 4, 1–2.
`D. The ’805 Patent
`The ’805 patent is directed to “an improved Static Random Access
`Memory (SRAM) cell design and method of manufacture.” Ex. 1001, 1:7–
`10. Figure 1 of the ’805 patent illustrates “the transistor configuration of an
`embodiment of an improved SRAM memory cell.” Id. at 4:61–62. The cell
`includes circuit components formed in silicon, an interconnection layer, a
`first metallization layer containing bitlines, and a second metallization layer
`containing a wordline. Id. at 6:17–19, 11:50–51, 13:19–30.
`Figure 2 of the ’805 patent illustrates “a layout 20 that may be used to
`form in silicon the memory cell 10 represented in FIG. 1.” Id. at 6:17–19.
`A modified version of Figure 2, colorized by Petitioner, is reproduced
`below. Pet. 9.
`
`
`
`3
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`The figure is a Petitioner-colorized version of Figure 2 of the ’805 patent,
`illustrating the layout of SRAM memory cell 10. Illustrated in the layout are
`“NMOS1 transistors 1–4 . . . formed within [outer] active regions 21 and 24,
`and PMOS2 transistors 5 and 6 . . . formed within [inner] active regions 22
`and 23. Ex. 1001, 6:26–29.
`Active regions 21–24 (yellow) “are arranged side-by-side and
`substantially parallel to each other.” Id. at 6:38–40. They are “substantially
`oblong, and . . . may be substantially rectangular as well.” Id. at 6:65–67.
`For example, “PMOS active regions . . . 22 or 23 . . . may have a length that
`is substantially constant across the width of the region, as well as a width
`that is substantially constant along the length of the region.” Id. at 6:67–7:4.
`NMOS active regions 21 and 24 may be “substantially oblong if the length
`of the region is substantially constant and the width of the region . . . varies
`only with the respective widths of the access and latch transistors.” Id. at
`7:24–28. Because “the width of the access transistor is approximately 2/3 the
`width of the latch transistor,” NMOS active regions 21 and 24 may be
`“substantially oblong if the length of the region is substantially constant and
`if the width of the region varies by approximately 1/3 or less along the length
`of the region.” Id. at 7:18–24. More generally, active regions are
`“substantially oblong” when they have “a length that is greater than or equal
`to approximately three times [their] maximum width.” Id. at 7:28–31.
`Polysilicon structures 25–28 (purple) are formed above and
`substantially perpendicular to active regions 21–24 (yellow). Id., Fig. 2.
`
`
`1 N-type metal-oxide-semiconductor.
`2 P-type metal-oxide-semiconductor.
`
`4
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`Polysilicon structures 25 and 27 “are arranged above active region 21 to
`form gates of pass transistor 1 and latch transistor 2, respectively.” Id. at
`6:55–57. Polysilicon structures 26 and 28 are arranged above active region
`24 “to form gates of pass transistor 4 and latch transistor 3, respectively.”
`Id. at 6:58–60. “[P]olysilicon structures 26 and 27 each include two gates.”
`Id. at 11:37–38. For example, polysilicon structure 26 “form[s] gates of
`PMOS latch transistor 6 and NMOS latch transistor 3,” and polysilicon
`structure 27 “form[s] gates of NMOS latch transistor 2 and PMOS latch
`transistor 5.” Id. at 11:32–37. Thus, “polysilicon structures 26 and 27 . . .
`each perform a local interconnecting function because they each connect two
`separate gate conductors together.” Id. at 11:38–41.
`Figure 3 of the ’805 patent “illustrates a local interconnect layer
`which may be used in conjunction with the layout shown in FIG. 2.” Id. at
`11:50–51. A modified version of Figure 3, colorized by Petitioner, is
`reproduced below. Pet. 11.
`
`The figure is a Petitioner-colorized version of Figure 3 of the ’805 patent,
`illustrating the layout of the interconnection layer of SRAM memory cell 10.
`“Interconnect structures 38 and 39 correspond to bitlines . . . and contacts
`16c and 15c, respectively.” Ex. 1001, 13:12–14. That is, interconnects 38
`
`
`
`5
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`and 39 couple the drains of transistors 1 and 4 of memory cell 10 via
`contacts 15c and 16c (see Fig. 2) to bitlines in a first metal layer (not shown)
`deposited over a dielectric layer (not shown) deposited over the layer
`containing interconnects 38 and 39. Id. at 10:30–32, 10:37–43, 13:12–14,
`13:19–27, Figs. 2, 3. “[I]nterconnect structures 37 and 40 correspond to
`[common ground] VSS and contacts 14c3 and 14c2, respectively.” Id. at
`13:16–17. That is, interconnects 37 and 40 couple the sources of transistors
`3 and 2 of memory cell 10 via contacts 14c3 and 14c2 (see Fig. 2) to VSS in a
`first metal layer (not shown) deposited over a dielectric layer (not shown)
`deposited over the layer containing interconnects 37 and 40. Id. at 10:32–
`34, 10:37–43, 13:16–17, 13:19–27, Figs. 2, 3. “[I]nterconnect structures 41
`and 42 correspond to [common power] VCC and contacts 13c6 and 13c5,
`respectively.” Id. at 13:18–19. That is, interconnects 41 and 42 couple the
`sources of transistors 6 and 5 in memory cell 10 via contacts 13c6 and 13c5
`(see Fig. 2) to VCC in a first metal layer (not shown) deposited over a
`dielectric layer (not shown) deposited over the layer containing
`interconnects 41 and 42. Id. at 10:34–43, 13:18–27, Figs. 2, 3. Finally,
`“interconnect structures 43 and 44 correspond to global wordline 17 and
`contacts 17c1 and 17c4.” Id. at 13:31–32. That is, interconnects 43 and 44
`couple the polysilicon gates 25 and 28 of transistors 1 and 4 in memory cell
`10 via contacts 17c1 and 17c4 (see Fig. 2) to a global wordline in a second
`metal layer (not shown) deposited over a dielectric layer (not shown)
`deposited over a first metal layer (not shown) deposited over a dielectric
`layer (not shown) deposited over the layer containing interconnects 43 and
`44. Id. at 8:50–9:14, 13:27–32, Figs. 2, 3.
`
`6
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`
`E. Illustrative Claim
`Claims 8, 16, 27, 29, 30, 53, and 59 are independent claims.
`Ex. 1001, Reexam. Cert. 1:25–35, 1:64–2:9, 2:61–3:11, 3:15–56, 5:60–6:10,
`6:36–52. Claims 9–15 depend directly or indirectly from claim 8. Id. at
`14:36–45; Reexam. Cert. 1:19–20, 1:36–63. Claims 17–26 depend directly
`or indirectly from claim 16. Id. at Reexam. Cert. 2:10–60. Claim 28
`depends directly from claim 27. Id. at Reexam. Cert. 3:12–14. Claims 31
`and 32 depend directly from claim 30. Id. at Reexam. Cert. 3:57–67.
`Claims 54–58 depend directly or indirectly from claim 53. Id. at Reexam.
`Cert. 6:11–35. Claims 60 and 61 depend directly from claim 59. Id. at
`Reexam. Cert. 6:53–65.
`Claim 8 is illustrative of the challenged claims and is reproduced
`below.
`8. A memory cell comprising
`a plurality of substantially oblong active regions formed in a
`semiconductor substrate and arranged substantially in
`parallel with one another, and
`a plurality of substantially oblong local interconnects above
`said substrate that extend only partially across the memory
`cell and are arranged substantially in parallel with one
`another and substantially perpendicular to said active
`regions; and
`a single local interconnect layer comprising local
`interconnects corresponding to bitlines and a global
`wordline.
`Ex. 1001, Reexam. Cert. 1:25–35.
`
`7
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`
`F. Evidence3
`
`Reference
`US 6,417,549 B1
`Oh
`R. Jacob Baker et al., CMOS Circuit Design,
`Layout and Simulation, (1998) (“Baker”)
`Lee
`US 5,702,982
`Nii
`US 6,347,062 B2
`Hara
`US 5,930,163
`
`Effective Date
`July 9, 2002
`1998
`Dec. 30, 1997
`Apr. 3, 20014
`July 27, 1999
`
`Exhibit
`1004
`1005
`1020
`1021
`1023
`
`35 U.S.C. §
`103(a)
`
`Oh
`
`Reference(s)
`
`G. Asserted Grounds
`Petitioner asserts the challenged claims would have been unpatentable
`on the following grounds:
`Ground
`Claims
`1A
`8–14, 16–20, 22–25,
`27, 28, 30–32
`8–14, 16–20, 22–25,
`27, 28, 30–32
`7, 15, 21, 26, 295
`7, 15, 21, 26, 29
`53–57, 59–61
`53–57, 59–61
`58
`58
`53–57, 59–61
`53–57, 59–61
`58
`58
`
`1B
`
`2A
`2B
`3A
`3B
`4A
`4B
`5A
`5B
`6A
`6B
`
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`
`Oh, Baker
`Oh, Lee
`Oh, Baker, Lee
`Oh, Nii
`Oh, Baker, Nii
`Oh, Nii, Lee
`Oh, Baker, Nii, Lee
`Oh, Hara
`Oh, Baker, Hara
`Oh, Hara, Lee
`Oh, Baker, Hara, Lee
`
`
`3 Petitioner also relies upon the Declarations of Jack C. Lee, Ph.D.
`(Ex. 1019) and Sylvia Hall-Ellis, Ph.D. (Ex. 1028).
`4 Petitioner relies on this date, the filing date of Nii, for its prior art status
`under 35 U.S.C. § 102(e). See Pet. 6.
`5 Petitioner lists claim 58 under grounds 2A/2B, however, provides no
`analysis for claim 58 under either ground. Compare Pet. 5, with id. at 77–
`92. Therefore, we do not list claim 58 under these grounds.
`
`8
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`
`II. ANALYSIS
`A. Institution of Inter Partes Review
`Petitioner avers that the “Petition is substantially identical to the
`petition in IPR2020-01491; it contains the same grounds (based on the same
`prior art and supporting evidence) against the same claims.” Pet. 3. We
`agree based on our independent review of the Petition, the petition filed in
`the QCOM IPR, and the evidence relied on in both petitions. Compare Pet.
`6–118, with QCOM IPR, Paper 1 at 5–117; see also Ex. 1032.
`We instituted inter partes review of claims 7–29, 30–32, and 53–61 of
`the ’805 patent based on the petition filed in the QCOM IPR on March 8,
`2021. QCOM IPR, Paper 10 (“Decision on Institution”). For the same
`reasons discussed in our Decision on Institution in the QCOM IPR, we find
`Petitioner has demonstrated a reasonable likelihood of showing at least one
`claim of the ’805 patent is unpatentable. Id. We, therefore, find the Petition
`warrants institution of inter partes review of all challenged claims on all
`grounds raised.
`
`B. Motion for Joinder
`Joinder in inter partes reviews is governed by 35 U.S.C. § 315(c),
`which states:
`If the Director institutes an inter partes review, the Director, in
`his or her discretion, may join as a party to that inter partes
`review any person who properly files a petition under section
`311 that the Director, after receiving a preliminary response
`under section 313 or the expiration of the time for filing such a
`response, determines warrants the institution of an inter partes
`review under section 314.
`Procedurally, a motion for joinder must be filed “no later than one month
`after the institution date of any inter partes review for which joinder is
`requested.” 37 C.F.R. § 42.122(b) (2019). Petitioner filed its Motion for
`
`9
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`Joinder on April 2, 2021, within one month of our March 8, 2021 decision
`granting review of the challenged claims in the QCOM IPR that Petitioner
`seeks to join. Mot. 6; QCOM IPR, Paper 10.
`To ensure the just, speedy, and inexpensive resolution of every
`proceeding, a motion for joinder should (1) set forth reasons why joinder is
`appropriate; (2) identify any new grounds of unpatentability asserted in the
`petition; (3) explain what impact (if any) joinder would have on the trial
`schedule for the existing review; and (4) address specifically how briefing
`and discovery may be simplified. See Kyocera Corp. v. SoftView LLC,
`IPR2013-00004, Paper 15 at 4 (PTAB Apr. 24, 2013),
`Petitioner argues Joinder is appropriate in this proceeding because
`“the Petition asserts the same grounds and relies on the same evidence for
`unpatentability presented in the [QCOM] IPR,” and the Board “routinely
`grants motions for joinder where the party seeking joinder introduces
`identical arguments and the same grounds raised in the existing proceeding.”
`Mot. 4 (quoting Samsung Elecs. Co., Ltd. v. Raytheon Co., IPR2016-00962,
`Paper 12 at 9 (PTAB Aug. 24, 2016)). Petitioner argues joinder will not
`impact the trial schedule of the QCOM IPR because Petitioner will adopt an
`“understudy” role in the QCOM IPR, “will not request any alterations to the
`trial schedule that the Board issued in the [QCOM] IPR,” and will “assume a
`primary role only if the [QCOM] IPR petitioner ceases its participation in that
`proceeding.” Id. at 5. Lastly, Petitioner argues joinder will not affect
`briefing and discovery because “Qualcomm will file briefing and conduct
`discovery, and Petitioner will not be involved. Petition will become
`involved only if Qualcomm exits the proceeding.” Id. at 6.
`Upon considering Petitioner’s arguments and the evidence presented,
`we are persuaded that it is appropriate under these circumstances to join
`
`10
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`Petitioner to the QCOM IPR. Petitioner challenges the same claims that are
`challenged in the QCOM IPR on the same grounds using the same prior art
`and evidence. See Mot. 4; Ex. 1032. Petitioner avers it will take an
`“understudy” role in the QCOM IPR and only assume a primary role should
`Qualcomm cease participation in the QCOM IPR. See Mot. 5. Thus, joinder
`to the QCOM IPR would result in the just, speedy, and inexpensive
`resolution of Petitioner’s challenge. See 37 C.F.R. § 42.1(b).
`Accordingly, for the reasons discussed above, we grant Petitioner’s
`Motion for Joinder and join Petitioner to the QCOM IPR.
`III. ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that, pursuant to 35 U.S.C. § 314, an inter partes review
`of the ’805 patent is instituted based on the grounds raised in the Petition;
`FURTHER ORDERED that the Motion for Joinder with IPR2020-
`01491 is granted, and Petitioner is joined as a petitioner to IPR2020-01491;
`FURTHER ORDERED that Petitioner’s role in IPR2020-01491 shall
`be limited as stated by Petitioner in the Motion for Joinder unless and until
`Qualcomm ceases to participate in IPR2020-01491;
`FURTHER ORDERED that the case caption in IPR2020-01491 shall
`be changed to reflect joinder of STMicroelectronics, Inc. as a petitioner in
`accordance with the attached example;
`FURTHER ORDERED that a copy of this Decision shall be entered
`into the record of IPR2020-01491.
`
`
`11
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`For PETITIONER:
`
`Tyler Bowen
`Philip Morin
`PERKINS COIE LLP
`bowen-ptab@perkinscoie.com
`morin-ptab@perkinscoie.com
`
`
`FOR PATENT OWNER:
`
`Theodoros Konstantakopoulos
`Yung-Hoon Ha
`DESMARAIS LLP
`tkonstantakopoulos@desmaraisllp.com
`yha@desmaraisllp.com
`
`
`
`
`
`
`12
`
`
`
`IPR2021-00704
`Patent 6,534,805 C1
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`QUALCOMM, INC. and STMICROELECTRONICS, INC.,6
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2020-01491
`Patent 6,534,805 C1
`
`
`
`
`
`
`
`
`
`
`6 STMicroelectronics, Inc., who filed a petition in IPR2021-00704, has been
`joined as a petitioner to this proceeding.
`
`1
`
`
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