Paper No. 1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
`
`STMICROELECTRONICS, INC.,
`
`PETITIONER
`
`v.
`
`MONTEREY RESEARCH, LLC
`
`PATENT OWNER.
`
`______________
`
`INTER PARTES REVIEW NO. IPR2021-00702
`PATENT 6,651,134
`______________
`
`PETITION FOR INTER PARTES REVIEW UNDER 35 U.S.C. § 312
`
`
`
`
`
`

`

`IPR2021-00702
`Patent 6,651,134
`
`TABLE OF CONTENTS
`PETITIONER’S EXHIBIT LIST ............................................................................. iv
`I.
`INTRODUCTION ........................................................................................... 1
`II. MANDATORY NOTICES ............................................................................. 2
`A.
`Real Party in Interest (37 C.F.R. § 42.8(b)(1)) ..................................... 2
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) .............................................. 3
`C.
`Lead and Back-Up Counsel (37 C.F.R. § 42.8(b)(3)) ........................... 4
`D.
`Service Information (37 C.F.R. § 42.8(b)(4)) ....................................... 5
`III. THE GROUNDS IN THIS PETITION ARE NOT CUMULATIVE
`OVER THE GROUNDS IN IPR2020-00985 ................................................. 5
`IV. GROUNDS FOR STANDING ........................................................................ 6
`V.
`STATEMENT OF PRECISE RELIEF REQUESTED FOR EACH
`CLAIM CHALLENGED ................................................................................ 7
`A.
`Claims for Which Review Is Requested (37 C.F.R. §
`42.104(b)(1)) ......................................................................................... 7
`Statutory Grounds of Challenge (37 C.F.R. § 42.104(b)(2)) ................ 7
`B.
`VI. FIELD OF TECHNOLOGY ........................................................................... 8
`A. DRAM Memory and Architecture ........................................................ 8
`B. DRAM Operations .............................................................................. 10
`C.
`External Commands vs. Internal Procedures ...................................... 12
`D.
`Burst Termination................................................................................ 14
`VII. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 15
`VIII. THE ’134 PATENT ....................................................................................... 15
`A. Admitted Prior Art............................................................................... 16
`B.
`The ’134 Patent’s Asserted Improvement to the Prior Art ................. 16
`C.
`Prosecution History ............................................................................. 19
`D.
`Claim Construction (37 C.F.R. § 42.104(b)(3)) .................................. 22
`“non-interruptible” (claims 1, 16, 17) ..................................... 22
`1.
`“internal address signal” (claims 1-4, 10-12, 15-17) .............. 22
`2.
`
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`

`

`3.
`
`4.
`
`IPR2021-00702
`Patent 6,651,134
`“predetermined number of [said] internal address signals”
`(claims 1-4, 10-12, 15-18, 21) / “fixed burst length” (claims
`2, 5-7, 17) .................................................................................. 23
`“means for reading data … / means for generating a
`predetermined number of said internal address signals” (claim
`16)” ........................................................................................... 25
`IX. REASONS FOR THE RELIEF REQUESTED UNDER 37 C.F.R.
`§§ 42.22(a)(2) AND 42.104(b)(4) ................................................................. 28
`A. Ground 1A—Claims 1-5, 7, 9-10, 12-18, 20, and 21 are
`anticipated by US 5,600,605 (“Schaeffer”) ......................................... 28
`Overview of Schaefer ................................................................ 28
`1.
`Element-by-element analysis .................................................... 37
`2.
`B. Ground 1B—Claims 1-7, 9-10, and 12-21 are Obvious Over
`Schaefer in View of Fujioka ................................................................ 65
`Fujioka ...................................................................................... 66
`1.
`2. Motivation to combine Schaefer and Fujioka ........................... 67
`3. Modification of Schaefer in view of Fujioka ............................. 69
`Element-by-element analysis .................................................... 70
`4.
`C. Ground 2A—Claim 11 is Obvious Over Schaefer and Lysinger ....... 78
`Lysinger ..................................................................................... 78
`1.
`2. Motivation to combine Schaefer and Lysinger ......................... 80
`3. Modification of Schaefer in view of Lysinger ........................... 82
`Element-by-element analysis .................................................... 83
`4.
`D. Ground 2B—Claim 11 is Obvious Over Schaefer in View of
`Lysinger and Fujioka ........................................................................... 83
`1. Motivation to combine Schaefer with Lysinger and Fujioka .... 83
`2. Modification of Schaefer with Lysinger and Fujoka ................ 83
`Element-by-element analysis .................................................... 84
`3.
`CONCLUSION .............................................................................................. 84
`
`X.
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`PETITIONER’S EXHIBIT LIST
`
`IPR2021-00702
`Patent 6,651,134
`
`Exhibit
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`
`1012
`
`1013
`
`1019
`
`1020
`1021
`
`1022
`
`Cowles
`CMOS Circuit
`Design
`Monterey FAC
`
`Description
`Shorthand
`U.S. Patent No. 6,651,134
`’134 Patent
`Omitted
`
`Omitted
`
`’134 File History Prosecution History of U.S. Patent No. 6,651,134
`
`Omitted
`Fujioka
`U.S. Patent No. 6,185,149
`Tiede
`U.S. Patent No. 5,900,021
`
`Omitted
`Lysinger
`U.S. Patent No. 5,784,331
`
`Omitted
`U.S.I.T.C Claim
`Order 29 Construing Claims, Inv. No. 337-TA-792,
`Construction Order
`U.S.I.T.C (February 9, 2012)
`N.D. Cal Claim
`Order Construing Claims, Cypress Semiconductor
`Construction Order
`Corp. v. GSU Tech., Inc., 13-cv-02013-JST (N.D.
`Cal.) (July 29, 2014)
`Commission Opinion, Inv. No. 337-TA-792,
`Commission
`U.S.I.T.C. (June 28, 2013)
`Opinion
`U.S. Patent No. 5,360,992
`Lowrey
`1014
`Declaration of Robert Murphy
`Murphy
`1015
`Curriculum Vitae of Robert Murphy
`Murphy CV
`1016
`U.S. Patent No. 5,600,605
`Schaefer
`1017
`1018 Cypress Whitepaper Cypress Semiconductor, Understanding Burst
`Modes in Synchronous SRAMs (June 30, 1999)
`Cypress Response Complainant
`Cypress
`Semiconductor
`Corporation’s Response to Respondents' Petition
`for Review of the Remand Initial Determination on
`Validity and Enforceability (April 3, 2013)
`U.S. Patent No. 5,729,504
`Baker et al, CMOS Circuit Design, Layout, and
`Simulation (First Ed. 1998)
`First Amended Complaint in Monterey Research,
`LLC v. Qualcomm Incorporated, et. al, No. 19-cv-
`2083-CFC (D. Del. Feb. 14, 2020)
`Petition for Inter Partes Review, IPR2020-00985,
`Paper 1, filed May 26, 2020.
`
`1023
`
`IPR2020-00985
`
`
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`Exhibit
`1024
`
`Description
`Shorthand
`Petition Comparison Comparison between the current Petition and
`petition in IPR2020-01492
`
`IPR2021-00702
`Patent 6,651,134
`
`
`
`
`
`v
`
`

`

`IPR2021-00702
`Patent 6,651,134
`
`I.
`
`INTRODUCTION
`STMicroelectronics, Inc. (“Petitioner”) requests inter partes review (“IPR”)
`
`of Claims 1-7 and 9-21 of U.S. Patent No. 6,651,134 (“the ’134 Patent”) (Ex-1001),
`
`currently assigned to Monterey Research, LLC (“Patent Owner”).
`
`This Petition is being submitted concurrently with a motion for joinder.
`
`Specifically, Petitioner requests institution and joinder with Qualcomm, Inc. v.
`
`Monterey Research, LLC, IPR2020-01492 (“the Qualcomm IPR”), which the Board
`
`instituted on March 8, 2021. This Petition is substantially identical to the petition in
`
`the Qualcomm IPR; it contains the same grounds (based on the same prior art and
`
`supporting evidence) against the same claims. See Ex. 1024, illustrating changes
`
`between the instant Petition and the petition in IPR2020-01492.
`
`The ’134 Patent is directed to well-known “burst” functionality in which a
`
`memory device generates a number of internal addresses in response to a single
`
`external address. EX1001, Abstract, 1:57-58. In the claimed burst functionality: (1)
`
`the generation of the internal address signals is “non-interruptible,” and (2) the
`
`number of
`
`internal address signals
`
`is “predetermined”
`
`/ “fixed”
`
`(yet
`
`“programmable”). Both are disclosed by the prior art cited in this Petition.
`
`First, Schaefer discloses read-and-write burst operations “with auto-
`
`precharge” in which “[t]he user is not allowed to issue another command until the
`
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`IPR2021-00702
`Patent 6,651,134
`precharged time (tRP)” at the end of the operation “is completed.” EX1017, 7:42-
`
`44.1 Thus, Schaefer discloses a “non-interruptible” burst.
`
`Second, Schaefer discloses a burst length / number of internal address signals
`
`is “predetermined” / “fixed” through programming of a mode register. Id., 6:1-2
`
`(“Burst lengths of 2, 4, 8, or full page (1,024) cycles are programmable into mode
`
`register 40”); see also EX1022, ¶94 (asserting Claim 1 is met by technical standard
`
`in which burst length is set by programming mode register). And, to the extent PO
`
`may contradict its own infringement mapping here, and assert that burst length must
`
`be “predetermined”
`
`/ “fixed” during
`
`fabrication, Fujioka discloses
`
`the
`
`interchangeability of setting burst length via mode register and via bond options
`
`“during the fabrication process” (EX1006, 14:50-15:13) which matches the ’134
`
`Patent’s preferred embodiment. EX1001, 3:29-35.
`
`Accordingly, Claims 1-7 and 9-21 of the ’134 Patent are invalid.
`
`II. MANDATORY NOTICES
`A. Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Petitioner STMicroelectronics, Inc. (“ST”) is a real party-in-interest.
`
`Although STMicroelectronics N.V., ST’s parent company, and STMicroelectronics
`
`International N.V., which is under common ownership with ST, are not real parties-
`
`
`1 All emphasis added unless otherwise indicated.
`
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`IPR2021-00702
`Patent 6,651,134
`in-interest under the governing legal standard for making that determination, ST
`
`identifies them as real parties-in-interest for purposes of this Petition to avoid any
`
`disputes over that issue.
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`(1) Cypress Semiconductor Corporation v. GSI Technology, Inc., 0-11-cv-
`
`00789 (D. Min. 2011) (terminated), which involved the ’134 Patent.
`
`(2)
`
`Static Random Access Memories and Products Containing Same, ITC-
`
`337-TA-792 (I.T.C. 2011) (terminated) (hereafter the “792 Investigation”), which
`
`involved the ’134 Patent.
`
`(3) Cypress Semiconductor Corporation v. GSI Technology, Inc., 3-13-cv-
`
`02013 (N.D. Cal. 2013) (terminated), which involved the ’134 Patent.
`
`(4) Cypress Semiconductor Corporation v. GSI Technology, Inc., 3-13-cv-
`
`03757 (N.D. Cal. 2013) (terminated), which involved the ’134 Patent.
`
`(5) Monterey Research, LLC v. Qualcomm Inc. et al., Civil Action No.
`
`1:19-cv-02083 (D. Del. 2019) (stayed), which involves the ’134 Patent.
`
`(6) Monterey Research, LLC v. Nanya Technology Corp. et al., Civil
`
`Action No. 1:19-cv-02090 (D. Del. 2019), which involves the ’134 Patent.
`
`(7) Monterey Research, LLC v. Advanced Micro Devices, Inc., Civil Action
`
`No. 1:19-cv-02149 (D. Del. 2019) (stayed), which involves the ’134 Patent.
`
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`IPR2021-00702
`Patent 6,651,134
`(8) Monterey Research, LLC v. STMicroelectronics NV et al., Civil Action
`
`No. 1:20-cv-00089 (D. Del. 2020) (stayed), which involves the ’134 Patent.
`
`(9) Monterey Research, LLC v. Marvell Technology Group, Ltd. et al.,
`
`Civil Action No. 1:20-cv-00158 (D. Del. 2020) (dismissed), which involved the ’134
`
`Patent.
`
`(10) Marvell Semiconductor Inc. v. Monterey Research, LLC, Civil Action
`
`No. 3:20-cv-03296 (N.D. Cal. 2020) (terminated), which involved the ’134 Patent.
`
`(11) Advanced Micro Devices, Inc. v. Monterey Research, LLC, IPR2020-
`
`00985 (P.T.A.B. 2020) (instituted), which involves the ’134 Patent.
`
`(12) Qualcomm, Inc. v. Monterey Research, LLC, IPR2020-01492 (P.T.A.B.
`
`2020) (instituted), which involves the ’134 Patent. The instant petition is being
`
`submitted concurrently with a motion for joinder to IPR2020-01492.
`
`C. Lead and Back-Up Counsel (37 C.F.R. § 42.8(b)(3))
`
`
`
`Lead Counsel
`Tyler R. Bowen
`(Reg. No. 60,461)
`
`PERKINS COIE LLP
`2901 N. Central Avenue,
`Suite 2000
`Phoenix, Arizona 85012
`Telephone: (602) 351-8000
`Facsimile: (602) 648-7000
`
`
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`Back-Up Counsel
`Chad S. Campbell
`Pro hac vice to be submitted
`Roque Thuo
`(Reg. No. 71,985)
`
`PERKINS COIE LLP
`2901 N. Central Avenue, Suite 2000
`Phoenix, Arizona 85012
`Telephone: (602) 351-8000
`Facsimile: (602) 648-7000
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`

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`IPR2021-00702
`Patent 6,651,134
`
`D.
`Service Information (37 C.F.R. § 42.8(b)(4))
`ST consents
`to electronic service by email at STMicro-Monterey-
`
`IPR_Service@perkinscoie.com.
`
`ST is concurrently filing an executed Power of Attorney appointing the above
`
`counsel.
`
`III. THE GROUNDS IN THIS PETITION ARE NOT CUMULATIVE
`OVER THE GROUNDS IN IPR2020-00985
`The grounds presented here are not cumulative over those in IPR2020-00985
`
`for at least three reasons.
`
`First, the petitions rely on different primary references—Schaefer here, versus
`
`U.S. Patent No. 6,115,280 (Wada) in IPR2020-00985. These distinct primary
`
`references are unrelated and map to the challenged claims in different ways. The
`
`petitions share certain secondary references (Fujioka and Lysinger), but only in
`
`combination with the different primary references.
`
`Second, this Petition relies primarily on Schaefer’s disclosure of burst modes
`
`known as READ and WRITE with AUTO-PRECHARGE, and the disclosure that
`
`during a burst operation with AUTO-PRECHARGE, “[t]he user is not allowed to
`
`issue another command until the precharged time (tRP) is completed.” EX1017,
`
`7:42-44. The grounds in IPR2020-00985 do not rely on any such mode or disclosure.
`
`Third, this Petition applies an alternative construction of the terms
`
`“predetermined number of [said] internal address signals” and “fixed burst length”
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`IPR2021-00702
`Patent 6,651,134
`and, accordingly, maps the art differently than the grounds in IPR2020-00985.
`
`Specifically, for Grounds 1A and 2A, this petition maps Schaefer against the
`
`construction that “predetermined” / “fixed” means determined prior to receipt of a
`
`signal rather than at manufacturing of the circuit. Under this construction,
`
`Schaefer’s disclosure of programming a mode register discloses the predetermined /
`
`fixed limitation after manufacture, but before issuance of a read or write command
`
`signal. This contrasts with IPR2020-00985’s use of what that petition characterizes
`
`as a “narrower interpretation adopted by the ITC (fixed or programmable at
`
`manufacture time using bond options or voltage levels).” IPR2020-00985, 16.
`
`Without accepting that alternative construction as correct, this Petition, in
`
`Grounds 1B and 2B, also maps Schaefer and Fujioka to that “narrower
`
`interpretation.”
`
`IV. GROUNDS FOR STANDING
`Pursuant to 37 C.F.R. § 42.104(a), Petitioner certifies that the ’134 Patent is
`
`available for inter partes review, and that Petitioner is not barred or estopped from
`
`requesting an inter partes review on the grounds identified in this Petition. The ’134
`
`Patent has not been subject to a previous final written decision in an estoppel-based
`
`AIA proceeding.
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`V.
`
`IPR2021-00702
`Patent 6,651,134
`STATEMENT OF PRECISE RELIEF REQUESTED FOR EACH
`CLAIM CHALLENGED
`A. Claims for Which Review Is Requested (37 C.F.R. § 42.104(b)(1))
`Petitioner requests review and cancellation of Claims 1-7 and 9-21 from the
`
`’134 Patent (EX1001) based on the following Grounds.
`
`B.
`Statutory Grounds of Challenge (37 C.F.R. § 42.104(b)(2))2
`Grounds 1A and 1B:
`
`Ground 1A: Claims 1-5, 7, 9-10, 12-18, 20, and 21 are invalid under
`
`§102(b) over Schaefer (EX1017). Issued February 4, 1998, Schaefer is prior art
`
`under §102(b).
`
`Ground 1B: Claims 1-7, 9-10, and 12-21 are invalid under §103(a) over
`
`Schaefer and Fujioka (EX1006). Fujioka was filed June 28, 1999 and issued
`
`February 6, 2001, qualifying as prior art under at least pre-AIA 35 U.S.C. §102(e).
`
`Grounds 1B and 2B are not cumulative because they add evidence addressing the
`
`“non-interruptible” and “predetermined” / “fixed” claim limitations under the
`
`narrower claim constructions that Patent Owner has asserted in the 792 Investigation
`
`involving the ’134 Patent.
`
`Grounds 2A and 2B:
`
`
`2 All Grounds are supported by a POSITA’s general knowledge. Koninklijke
`
`Philips N.V. v. Google LLC, 948 F.3d 1330, 1337-38 (Fed. Cir. 2020).
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`IPR2021-00702
`Patent 6,651,134
`Ground 2A: Claim 11 is invalid under §103(a) over Schaefer and
`
`Lysinger (EX1009). Issued July 21, 1998, Lysinger is prior art under §102(b).
`
`Ground 2B: Claim 11 is invalid under §103(a) over Schaefer and
`
`Lysinger (EX1009), in further view of Fujioka.
`
`VI. FIELD OF TECHNOLOGY
`The ’134 Patent describes burst read and write operations using a memory
`
`circuit in which the generation of internal address signals is non-interruptible.
`
`EX1001, Abstract, 1:6-8, 3:5-29, 4:15-48.
`
`A. DRAM Memory and Architecture
`As shown in the example below, a DRAM memory device includes two
`
`primary functional components: (a) [blue] core memory, which includes an array of
`
`DRAM cells along with addressing and read/write circuitry, and (b) control circuitry
`
`that operates the core memory based on received [red] external inputs from
`
`command, address, and data lines. EX1015, ¶26. Each DRAM memory cell
`
`typically includes a transistor and a capacitor that is charged or discharged to
`
`produce a 1 or a 0. Id., ¶25. A DRAM memory device is typically a stand-alone
`
`chip receiving external inputs from a memory controller on a separate chip. Id., ¶26.
`
`Schaefer refers to the entity providing the external signals, typically the
`
`memory controller, as the “user” of the memory device. E.g., EX1017, 7:33-37.
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`IPR2021-00702
`Patent 6,651,134
`
`EX1021, Figure 17.1.
`
`
`
`Schaefer’s Figure 1 (annotated below) illustrates an example of a complete
`
`DRAM device with control circuitry surrounding the [blue] core memory and
`
`receiving inputs from the [red] external command, address, and data lines.
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`IPR2021-00702
`Patent 6,651,134
`
`EX1017, Fig. 1.
`
`
`
`B. DRAM Operations
`To accomplish an operation such as reading a piece of data, typically, an
`
`external memory controller (not subject of the ’134 Patent) will issue one or more
`
`external commands to the memory device. EX1015, ¶28. In response to an external
`
`command, the memory device will perform one or more internal procedures
`
`accessing the memory array. Id.
`
`An exemplary basic DRAM read operation involves issuance of a series of
`
`external commands to the DRAM device:
`
` first, ACTIVE to activate or select a row in the array of DRAM cells,
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`IPR2021-00702
`Patent 6,651,134
` next, READ to “read” a specific column of the row that corresponds to an
`
`address, and
`
` finally, a manual PRECHARGE command to close the row.
`
`Id.
`
`In DRAM, the internal procedure of reading a row of data is destructive,
`
`meaning the read data is no longer stably stored in the cell. Id., ¶29. As such, in
`
`response to an external READ command, the memory device generally performs
`
`internal procedures not only to read the data, but also to “write back,” thereby
`
`restoring the data. Id. A typical DRAM write operation requires a similar series of
`
`external commands (with a WRITE command instead of the READ command). Id.,
`
`¶¶31-32. And in response to an external WRITE command, the memory device
`
`generally performs internal procedures first to read the data and then write back the
`
`modified data. Id.
`
`Based on the nature of DRAM cells, rows must be periodically “refreshed” to
`
`avoid charge loss and loss of data even if not subject of an active read and write. Id.,
`
`¶33. This is accomplished by the writeback procedure during a read or write and
`
`may also be accomplished through issuance of an external REFRESH command. Id.
`
`Additionally, some systems may automatically perform hidden refreshes of rows of
`
`a non-active memory bank during a read or write operation to the active memory
`
`bank. Id., ¶34.
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`IPR2021-00702
`Patent 6,651,134
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`C. External Commands vs. Internal Procedures
`There is often not a one-to-one correspondence between memory operations,
`
`external commands, and internal chip procedures. Id., ¶35. As discussed above, a
`
`read or write operation may require issuance of a series of external commands. Id.,
`
`¶28. And a single external command often results in multiple internal procedures.
`
`Id., ¶35.
`
`Additionally, well before filing of the ’134 Patent, memory designers
`
`developed compound external commands that combined and optimized what had
`
`previously been accomplished through issuance of a sequence of external
`
`commands. Id., ¶37. Two such compound operations discussed below are (1) burst
`
`READ and WRITE commands and (2) burst READ and WRITE commands WITH
`
`AUTO-PRECHARGE. Id.
`
`The ’134 Patent does not purport to have developed burst operations.
`
`EX1001, 1:11-27. In known burst operations, an initial address is provided with the
`
`external command. The memory device reads/writes from/to that initial location as
`
`well as additional locations within the burst, internally generating the addresses of
`
`the additional locations within the burst. EX1015, ¶39. A prior art paper, from the
`
`original assignee of the ’134 Patent cited on the face of the patent, illustrates
`
`exemplary hardware and a flowchart for generating these addresses.
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`IPR2021-00702
`IPR2021-00702
`Patent 6,651,134
`Patent 6,651,134
`
`Address_
`
`I
`
`Clk
`
`—>
`
`Address Latch
`
`
`
`
`Upper
`—FAddress
`bits
`
`+b
`2
`
`Lower
`2 Address
`bits
`
`2
`
`
`
`
`A0
`A1
`
`——>
`
`fa
`
`
`
`2—B it Counter
`
`Figure 1. Key Signals for Burst Feature on Typical
`SRAMs
`
`EX1018, Figure 1.
`EX1018, Figure 1.
`
`
`
`
`
`ADV=0
`
`CLK=+
`
`ADV=U
`
`CLK=+
`
`ADV=D
`
`CLK=+
`
`Figure 2. Burst Mode Address Update
`EX1018, Figure 2.
`EX1018, Figure 2.
`
`
`
`
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`Schaefer discloses additional compound external commands that combine a
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`burst READ or WRITE command with “AUTO-PRECHARGE.” EX1017, 7:38 43.
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`“By using the AUTO-PRECHARGE command feature, a manual PRECHARGE
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`command does not need to be issued” and, instead, “the precharge is initiated at the
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`earliest, valid stage within a burst cycle.” Id.
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`D. Burst Termination
`In some systems, a burst can be interrupted or terminated by using a dedicated
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`“BURST TERMINATE” command or by issuing another READ, WRITE, OR
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`PRECHARGE command. EX1015, ¶41. The ability to terminate a burst may be
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`advantageous. Id. ¶41. However, a chip designer may choose not to offer such
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`functionality where the necessary internal procedures conducted during of a
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`particular burst operation would conflict with permitting termination of the burst.
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`Id., ¶42. In such a case, the chip designer can preclude termination/interruption, for
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`example, by specifying that additional commands during a given period of time are
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`“not allowed” or “illegal.” Id., ¶42. As explained below, this is precisely what
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`Schaefer (earlier) and the ‘134 Patent (later) each disclose.
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`VII. LEVEL OF ORDINARY SKILL IN THE ART
`A POSITA as of February 14, 20003—the ’134 Patent’s earliest claimed
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`priority date (“ECPD”)—would have had at least a degree in electrical or computer
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`engineering, and at least two years of experience in design, development, and/or
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`testing of memory circuits, related hardware design, or the equivalent, with
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`additional education substituting for experience and vice versa. EX1015, ¶48. The
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`prior art and the ’134 Patent also evidence this level of ordinary skill. See Chore-
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`Time Equip., Inc. v. Cumberland Corp., 713 F.2d 774, 779 (Fed. Cir. 1983); Okajima
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`v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001). Here, the prior art described in
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`this Petition demonstrates that a POSITA would have been familiar with
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`synchronous random access memory circuits that use burst operations to transfer
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`data to and from memory. EX1015, ¶47.
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`VIII. THE ’134 PATENT
`Entitled “Memory Devices with Fixed Length Non Interruptible Burst,” the
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`‘134 Patent’s memory circuit provides that “generation of [a] predetermined number
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`of internal address signals may be non-interruptible.” EX1001, 1:55-56.
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`3 All statements in this Petition about the knowledge and skills of, and what would
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`have been obvious to, a POSITA are offered from this perspective as of this date.
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`Patent 6,651,134
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`A. Admitted Prior Art
`The ‘134 Patent confirms that “provid[ing] data from multiple address
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`locations using a single address” called “burst mode access” was well-known.
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`EX1001, 1:11-14. Per the ’134 Patent, “the burst mode of a conventional
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`synchronous SRAM can be started and stopped in response to a control signal.” Id.,
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`1:16-27.
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`B.
`The ’134 Patent’s Asserted Improvement to the Prior Art
`The ’134 Patent discloses a memory circuit that reads and writes data from
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`memory using a burst of a “predetermined” number of “internal address signals”
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`wherein the generation of internal address signals is “non-interruptible.” Id., 1:55-
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`56. The patent asserts that in such a system: (1) “refresh activity (e.g., writeback,
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`read for refresh, and writeback for refresh) may be completed [i.e. hidden] within
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`the time of the burst transfer,” and (2) “the address bus and control bus” are “free[d]
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`up” “for a known number of cycles.” Id., 5:8-15, 3:56-61.
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`As shown in the ’134 Patent’s Figure 1 (annotated below), circuit 100 includes
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`a [orange] circuit 102 that generates multiple internal address signals (ADDR_INT)
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`that are fed into a [blue] memory array 104 to write/read burst data to/from that
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`array.
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`The memory array 104 is where data is stored (a “write” operation) or accessed (a
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`“read” operation). Id., 5:23-25 (claim 1), 2:26-30, 2:61-65, 3:2-4.
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`As further depicted in Figure 2 (annotated below), an embodiment of circuit
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`102 includes a [yellow] address counter register 126 and a [green] burst counter 130.
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`The circuit generates the predetermined number of internal address signals when the
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`[yellow] address counter register 126 receives (i) an external address signal
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`(ADDR_EXT), (ii) a clock signal (CLK) and (iii) one or more control signals (e.g.
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`LOAD/ADV). Id., 5:26-29 (claim 1); 3:65-4:1.
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`For example, when the LOAD signal 108 is asserted, [yellow] address counter
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`register 126 latches (captures) in external address ADDR_EXT to generate an initial
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`internal address. Id., 4:6-8. Subsequent internal addresses are generated when the
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`ADV is asserted, which causes the [green] burst counter 128 to output the
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`BURST_CLK signal 132 in response to each clock signal, CLK. Upon receipt of
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`the BURST_CLK signal, address counter register 126 increments the latched
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`address to generate and output the next internal address. Id., 4:8-14. Further, “[o]nce
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`the circuit 102 has started generating the fixed number of addresses, the circuit 102
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`will generally not stop until the fixed number of addresses has been generated (e.g.,
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`a non-interruptible burst).” Id., 3:25-29.
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`As shown in Figure 3 (annotated below), a second embodiment of the logic
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`circuit includes a [yellow] latch 134, a [green] counter 138, and [purple] multiplexer
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`136. This embodiment substantially matches prior art EX1018, discussed above.
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`Compare EX1001, Figure 1.
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`C.
`Prosecution History
`During prosecution of the ’134 Patent’s application, the claims were
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`repeatedly rejected and only allowed after the Examiner did not file a response to
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`
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`the applicant’s appeal brief.
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`In a first Office Action, the Examiner rejected all pending claims, including
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`dependent Claims 6 and 15 (which recite that the burst length is programmed by
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`“bond options”) under as lacking sufficient written description support for the
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`recited concept. EX1004, 41-42/186.4 All claims were also rejected as anticipated
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`by Yip (U.S. 6,289,138). Id., 42-44/186. The applicant responded to the written
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`description requirement by arguing that:
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`Support for claims 6 and 15 may be found on page 8, lines 3-8 of the
`specification. Furthermore, bond options are well known in the art and,
`therefore, one skilled in the art would understand how to make and/or
`use bond options. Copies of U.S. patents 6,188,636 (issued February
`13, 2001), 5,900,021 (issued May 4, 1999) and 5,360,992 (issued
`November 1, 1994) from the USPTO web site (www.uspto.gov) are
`attached as evidence of bond options being well known in the art.
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`Id., 62/186. In response to the §102 rejections, the applicant argued that Yip did not
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`disclose “the generation of a predetermined number of internal address signals that
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`is non-interruptible.” Id., 63/186. Specifically, the patentee argued that Yip’s write
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`burst “can be interrupted when there is a cycle request from a higher priority port.”
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`Id., 64/186.
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`In a second Office Action, the Examiner rejected all pending claims as
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`anticipated by Cowles (US 5,729,504). Id., 70-73/186. The applicant responded by
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`arguing that Cowles’ internal address bursts were not non-interruptible. Id., 83/186.
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`The applicant also argued that “Cowles teaches that a low to high transition of the
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`4 The pages of Exhibit 1004 have been numbered consecutively from 1 to 186.
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`WE* signal within a burst write access to the memory array 112 will terminate the
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`burst access, preventing further writes from occurring . . . .” Id., 84/186.
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`In a third Office Action, the Examiner repeated and made final the Cowles
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`rejection. Id., 93/186. The applicant again argued that Cowles did not teach that the
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`burst memory accesses were non-interruptible. Id., 115/186. The Examiner rejected
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`that argument in an Advisory Action, and the applicant appealed based on the same
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`arguments. Id., 121-123/186. The Examiner filed no responsive brief but instead
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`issued a Notice of Allowance, conceding that Cowles disclosed:
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`[T]o terminate a continuous burst read operation, the WE signal merely
`has to transition high prior to a falling edge of the CAS signal (see, for
`example, Cowles). [T]hus prior art of record does not teach or fairly
`suggest the non-interruptible generation of a predetermined number of
`internal address signals.”
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`Id., 172/186 (emphasis original).
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`As discussed in below, Schaefer is not cumulative of the art at issue in
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`prosecution because, unlike Cowles for example, Schaefer discloses that during a
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`burst operation with AUTO-PRECHARGE, “[t]he user is not allowed to issue
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`another command until” after generation of the internal addresses for the burst is
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`completed. EX1017, 7:42-44.
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`D. Claim Construction (37 C.F.R. § 42.104(b)(3))
`Claim terms are given a meaning in accordance with the standard used in
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`§ 282(b) civil actions, including their “ordinary and customary meaning … as
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`understood by [a POSITA] and the prosecution history.” 37 C.F.R. § 42.100(b).
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`1.
`“non-interruptible” (claims 1, 16, 17)
`In the 792 Investigation (see Section II.B), the parties agreed that “non-
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`interruptible” means “cannot be stopped or terminated once initiated until the fixed
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`number of internal addresses has been generated.” EX1011, 15-16/45. The ’134
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`Patent specification describes “non-interruptible” in less absolute terms, stating:
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`Once the circuit 102 has started generating the fixed number of
`addresses, the circuit 102 will generally not stop until the fixed number
`of addresses has been generated (e.g., a non-interruptible bu