U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`
`
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
`
`
`
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,651,134
`
`
`
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 1 of 80
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`

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`TABLE OF CONTENTS
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`
`Page
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`TABLE OF CONTENTS
`
`
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. §42.8 ................................... 3
`III.
`FEE AUTHORIZATION ............................................................................... 4
`IV. GROUNDS FOR STANDING ....................................................................... 4
`V.
`PRECISE RELIEF REQUESTED ................................................................. 4
`VI. THE CHALLENGED PATENT .................................................................... 6
`VII. PATENT PROSECUTION HISTORY .......................................................... 9
`VIII. LEVEL OF ORDINARY SKILL IN THE ART .......................................... 11
`IX. CLAIM CONSTRUCTION ......................................................................... 11
`A.
`“non-interruptible” (claims 1, 16, 17) ................................................ 12
`B.
`“means for reading data . . . / means for generating a
`predetermined number of said internal address signals” (claim
`16) ....................................................................................................... 13
`“external address signal” (claims 1, 13, 15-17) ................................. 15
`“burst” (claim 2) ................................................................................. 15
`“internal address signal” (claims 1, 2, 12, 15-17) .............................. 15
`“logic circuit” (claims 1, 12) .............................................................. 16
`“predetermined number of [said] internal address signals”
`(claims 1-4, 12, 15-17) ....................................................................... 16
`“memory” (claims 1, 8-9, 14, 17)....................................................... 17
`H.
`“address signal” (claims 1-4, 10-13, 16-17) ....................................... 17
`I.
`SPECIFIC EXPLANATION OF GROUNDS ............................................. 17
`A. Ground 1: Claims 1-3, 8, 12-13, 16, and 17 are anticipated by
`US 6,115,280 (“Wada”) ..................................................................... 17
`1. Wada ........................................................................................ 17
`
`C.
`D.
`E.
`F.
`G.
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`X.
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`i
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 2 of 80
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`B.
`
`2.
`Independent Claim 1 ................................................................ 24
`Dependent Claim 2 .................................................................. 30
`3.
`Dependent Claim 3 .................................................................. 32
`4.
`Dependent Claim 8 .................................................................. 33
`5.
`Dependent Claim 12 ................................................................ 34
`6.
`Dependent Claim 13 ................................................................ 36
`7.
`Independent Claim 16 .............................................................. 39
`8.
`Independent Claim 17 .............................................................. 46
`9.
`Ground 2: Claims 1-4, 8, 12-14, 16, and 17 are obvious over
`Wada in view of the knowledge of a POSITA ................................... 47
`1.
`Independent Claims 1 and 16 ................................................... 47
`2.
`Dependent Claims 2-3, 8, 12-13, and 17 ................................. 48
`3.
`Dependent Claim 4 .................................................................. 48
`4.
`Dependent Claim 14 ................................................................ 49
`Ground 2a: Claims 1-4, 8, 12-14, 16, and 17 are rendered
`obvious by the combination of Wada and US 5,584,033
`(“Barrett”) in view of the knowledge of a POSITA ........................... 50
`1.
`Barrett ....................................................................................... 50
`2.
`Claims 1-4, 8, 12-14, 16, and 17 .............................................. 53
`D. Ground 3: Claims 4-7, and 18-20 are rendered obvious by the
`combination of Wada and U.S. 6,185,149 (“Fujioka”) in view
`of the knowledge of a POSITA. ......................................................... 53
`1.
`Fujioka ..................................................................................... 53
`2.
`Dependent Claim 4 .................................................................. 57
`3.
`Dependent Claim 5 .................................................................. 57
`4.
`Dependent Claim 6 .................................................................. 58
`5.
`Dependent Claim 7 .................................................................. 58
`6.
`Dependent Claim 18 ................................................................ 59
`
`C.
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`ii
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 3 of 80
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`

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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`
`
`7.
`Dependent Claim 19 ................................................................ 59
`Dependent Claim 20 ................................................................ 60
`8.
`Ground 3a: Claims 4-7, and 18-20 are rendered obvious by the
`combination of Wada, Barrett, and Fujioka in view of the
`knowledge of a POSITA. ................................................................... 60
`Ground 4: Claims 9-10, 14, and 21 are rendered obvious by the
`combination of Wada and US 6,226,755 (“Reeves”) in view of
`the knowledge of a POSITA .............................................................. 60
`1.
`Reeves ...................................................................................... 60
`2.
`Dependent Claim 9 .................................................................. 63
`3.
`Dependent Claim 10 ................................................................ 63
`4.
`Dependent Claim 14 ................................................................ 64
`5.
`Dependent Claim 21 ................................................................ 65
`G. Ground 4a: Claims 9-10, 14, and 21 are rendered obvious by
`the combination of Wada, Barrett, and Reeves in view of the
`knowledge of one of ordinary skill in the art ..................................... 65
`H. Ground 5: Claims 11 and 15 are rendered obvious by the
`combination of Wada and US 5,784,331 (“Lysinger”) in view
`of the knowledge of one of ordinary skill in the art ........................... 65
`1.
`Lysinger ................................................................................... 65
`2.
`Dependent Claim 11 ................................................................ 69
`3.
`Dependent Claim 15 ................................................................ 69
`Ground 5a: Claims 11 and 15 are rendered obvious by the
`combination of Wada, Barrett, and Lysinger in view of the
`knowledge of one of ordinary skill in the art ..................................... 72
`XI. CONCLUSION ............................................................................................. 72
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`E.
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`F.
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`I.
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`iii
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 4 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`LIST OF EXHIBITS
`
`Ex-1001
`
`U.S. Patent No. 6,651,134
`
`Ex-1002
`
`Declaration of Dr. R. Jacob Baker
`
`Ex-1003
`
`Curriculum Vitae of Dr. R. Jacob Baker
`
`Ex-1004
`
`Prosecution History of U.S. Patent No. 6,651,134
`
`Ex-1005
`
`U.S. Patent No. 6,115,280 (“Wada”)
`
`Ex-1006
`
`U.S. Patent No. 6,185,149 (“Fujioka”)
`
`Ex-1007
`
`U.S. Patent No. 5,900,021 (“Tiede”)
`
`Ex-1008
`
`U.S. Patent No. 6,226,755 (“Reeves”)
`
`Ex-1009
`
`U.S. Patent No. 5,748,331 (“Lysinger”)
`
`Ex-1010
`
`U.S. Patent No. 5,584,033 (“Barrett”)
`
`Ex-1011
`
`Ex-1012
`
`Ex-1013
`
`Order 29 Construing Claims, Inv. No. 337-TA-792, U.S.I.T.C
`(February 9, 2012)
`
`Order Construing Claims, Cypress Semiconductor Corp. v. GSU
`Tech., Inc., 13-cv-02013-JST (N.D. Cal.) (July 29, 2014)
`
`Commission Opinion, Inv. No. 337-TA-792, U.S.I.T.C. (June 28,
`2013)
`
`Ex-1014
`
`U.S. Patent No. 5,360,992 (“Lowrey”)
`
`
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`iv
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 5 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`I.
`
`INTRODUCTION
`Advanced Micro Devices, Inc. (“Petitioner”) requests inter partes review
`
`(“IPR”) of Claims 1-21 of U.S. Patent No. 6,651,134 (“the ’134 Patent”) (Ex-
`
`1001), currently assigned to Monterey Research, LLC (“Patent Owner”).
`
`The ’134 Patent discloses neither a new memory circuit design, a new
`
`memory addressing technique, nor a new data transfer technique. Indeed, the
`
`patent admits that conventional memories can be accessed in both single address
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`mode and in “burst” mode, wherein multiple data locations are accessed in
`
`response to a single initial address. Ex-1001 at 1:14-16. The claims of the ’134
`
`Patent merely combine techniques and memory architectures already well known
`
`in the art.
`
`The claimed improvement of the ’134 Patent is to read and write data from a
`
`memory using a burst of internal address signals wherein the generation of internal
`
`address signals is “non-interruptible.” Specifically, the ’134 Patent notes that
`
`while conventional systems employing static random access memory (SRAM) can
`
`operate in a burst mode that can be started and stopped in response to a control
`
`signal (Id. at 1:16-18), conventional systems employing dynamic random access
`
`memory (DRAM) are required to periodically interrupt burst transfers in order to
`
`refresh the charge on the memory cells, which slowly leaks away. Id. at 1:19-24.
`
`Nevertheless, the claims of the ’134 Patent are written to encompass not only
`
`1
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 6 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`DRAM systems, configured to hide refresh cycles behind burst reads of other
`
`memory partitions, but also SRAM systems, which do not need to be interrupted
`
`because they do not require refresh. Compare, e.g., claims 1, 8, and 9. So it is not
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`surprising that the claims were rejected multiple times during prosecution over
`
`prior art disclosing generating internal addresses in a continuous burst. The
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`applicant finally overcame those rejections after filing an appeal brief and arguing
`
`that while the primary prior art reference did disclose continuous burst transfers
`
`using internally generated addresses, it also disclosed that there was a way for a
`
`burst to be terminated, so it was not non-interruptible. See, e.g., Ex-1004 (File
`
`History) at 115.
`
`Prior art presented in this Petition, which was not considered during
`
`prosecution, teaches an apparatus and method for generating a predetermined
`
`number of internal address signals for reading from and writing to memory
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`wherein the burst of internal address signals is non-interruptible. The primary
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`reference, Wada, anticipates the independent claims, disclosing memory burst
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`transfers that are not interrupted. Nevertheless, because of the patentee’s
`
`narrowing arguments during prosecution, Petitioners also present the combination
`
`of Wada and Barrett, which expressly teaches bursts that are non-interruptible.
`
`Thus, for the reasons set forth in this Petition, Claims 1-21 of the ’134 Patent are
`
`unpatentable. These grounds are likely to prevail, and this Petition should be
`
`2
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 7 of 80
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`

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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`granted and the challenged claims cancelled.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. §42.8
`Real Parties-in-Interest: Petitioner Advanced Micro Devices, Inc. and ATI
`
`Technologies ULC are the real parties-in-interest. ATI Technologies ULC is an
`
`indirect, wholly owned subsidiary of Advanced Micro Devices, Inc.
`
`Related Matters:
`
`• Patent Owner has asserted the ’134 Patent against Petitioner in
`
`Monterey Research, LLC v. Advanced Micro Devices, Inc., No. 1:19-
`
`cv-02149-CFC (D. Del.).
`
`• The ’134 Patent was previously asserted in the International Trade
`
`Commission in In the Matter of Certain Static Random Access
`
`Memories and Products Containing the Same, Inv. No. 337-TA-792
`
`(U.S.I.T.C., hereinafter the “792 Investigation”) and in District Court
`
`in Cypress Semiconductor Corp. v. GSI Tech., Inc., No. 13-cv-02013-
`
`JST (N.D. Cal).
`
`Lead and Back-Up Counsel:
`• Lead Counsel: Ryan K. Yagura (Reg. No. 47,191), O’Melveny &
`
`Myers LLP, 400 S. Hope Street, Los Angeles, CA 90071.
`
`(Telephone: 213-430-6000; Fax: 213-430-6407; Email:
`
`ryagura@omm.com)
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`3
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 8 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`• Backup Counsel: Nicholas J. Whilt (Reg. No. 72,081), Vincent Zhou
`
`(Reg. No. 63,366), Brian M. Cook (Reg. No. 59,356), O’Melveny &
`
`Myers LLP, 400 S. Hope Street, Los Angeles, CA 90071.
`
`(Telephone: 213-430-6000; Fax: 213-430-6407; Email:
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`nwhilt@omm.com, vzhou@omm.com, bcook@omm.com)
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`Service Information: Petitioner consents to electronic service by email to
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`OMMAMDMONTEREY@omm.com. Please address all postal and hand-delivery
`
`correspondence to lead counsel at O’Melveny & Myers LLP, 400 S. Hope Street,
`
`Los Angeles, CA 90071, with courtesy copies to the email address identified
`
`above.
`
`III. FEE AUTHORIZATION
`Pursuant to 37 C.F.R. §42.15(a) and §42.103(a), the PTO is authorized to
`
`charge $34,400 (or other fees required for this filing) to Deposit Account No. 50-
`
`0639.
`
`IV. GROUNDS FOR STANDING
`Under 37 C.F.R. §42.102(a)(2), §42.104(a), Petitioner certifies that the ’134
`
`Patent is available for IPR, this Petition is timely filed, and Petitioner is not barred
`
`or estopped from requesting IPR review on the grounds presented.
`
`V.
`
`PRECISE RELIEF REQUESTED
`Petitioner respectfully requests review and cancellation of all 21 claims of
`
`4
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 9 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`the ’134 Patent under 35 U.S.C. §102 and/or §103 based on the following grounds:
`
`Ground 1: Claims 1-3, 8, 12-13, 16, and 17 are anticipated by US 6,115,280
`
`(“Wada”);
`
`Ground 2: Claims 1-4, 8, 12-14, 16, and 17 are rendered obvious by Wada
`
`in view of the knowledge of a person of ordinary skill in the art (“POSITA”);
`
`Ground 2a: Claims 1-4, 8, 12-14, 16, and 17 are rendered obvious by Wada
`
`and US 5,584,033 (“Barrett”) in view of the knowledge of a POSITA;
`
`Ground 3: Claims 4-7, and 18-20 are rendered obvious by Wada and U.S.
`
`6,185,149 (“Fujioka”) in view of the knowledge of a POSITA.
`
`Ground 3a: Claims 4-7, and 18-20 are rendered obvious by Wada, Barrett,
`
`and Fujioka in view of the knowledge of a POSITA
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`Ground 4: Claims 9-10, 14, and 21 are rendered obvious by Wada and US
`
`6,226,755 (“Reeves”) in view of the knowledge of a POSITA;
`
`Ground 4a: Claims 9-10, 14, and 21 are rendered obvious by Wada, Barrett,
`
`and Reeves in view of the knowledge of a POSITA;
`
`Ground 5: Claims 11 and 15 are rendered obvious by Wada and US
`
`5,784,331 (“Lysinger”) in view of the knowledge of a POSITA; and
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`Ground 5a: Claims 11 and 15 are rendered obvious by Wada, Barrett, and
`
`Lysinger in view of the knowledge of one a POSITA.
`
`None of the references relied upon in this Petition was cited by the Examiner
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`5
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 10 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`during prosecution of the ’134 Patent. Ex-1001, 1.
`
`VI. THE CHALLENGED PATENT
`The ’134 Patent is directed to a system and method for addressing a memory
`
`circuit with a burst of internal address signals that may be non-interruptible. Ex.
`
`1001 at Abstract. A device reads data from memory by asserting an address and
`
`receiving data from the memory location specified by that address. In “burst”
`
`mode, however, a controller asserts a single address, and memory circuit logic
`
`generates a series of internal addresses, typically offset from the initial address as
`
`address+0, address+1, address+2, etc., and returns data from multiple memory
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`locations specified by those internal addresses in response to one external
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`addresses. Ex-1002 ¶35.
`
`An embodiment of the alleged invention is “configured to transfer a fixed
`
`number of words of data with each access (e.g., read or write).” Ex-1001 at 2:28-
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`30. An array of memory cells may be addressed by a “burst address counter”
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`circuit that receives an external address (ADDR_EXT), a clock (CLK), and control
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`signals (e.g., LOAD, ADV) and that outputs a burst of internal addresses
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`ADDR_INT that access the memory cells. See id. at 2:31-46. Figure 1, for
`
`example, depicts “Burst Address Counter / Register” 102, which latches in external
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`address ADDR_EXT when the LOAD signal is asserted. Id. at 3:14-19. When
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`ADV is asserted, a fixed number of internal addresses (ADDR_INT) are generated
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`6
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 11 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`in response to the CLK signal. Id. at 3:19-24. “Once the circuit 102 has started
`
`generating the fixed number of addresses, the circuit 102 will generally not stop
`
`until the fixed number of addresses has been generated (e.g., a non-interruptible
`
`burst).” Id. at 3:25-29.
`
`
`
`The ’134 Patent discloses two embodiments of the “Burst Address Counter”
`
`102, depicted in Figures 2 and 3. In Fig. 2, below, an initial address
`
`(ADDR_EXT) is latched into the address counter register 126 when LOAD is
`
`asserted. Id. at 4:6-8. When ADV is asserted, the BURST_CLK signal is
`
`generated in response to CLK and increments the address in the address counter
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`register 126 to produce a predetermined number of internal address values
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`ADDR_INT (116). Id. at 4:6-14.
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`7
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 12 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`
`
`In Figure 3, an n-bit external address (ADDR_EXT) is divided into an m-bit
`
`portion and a k-bit portion. Id. at 4:18-25. The k-bit portion is sent to counter
`
`(138) and is incremented by the CLK signal when ADV is asserted. Id. at 4:28-33.
`
`A multiplexer (136) selects either the latched k-bit portion of the external address
`
`(142) or the k-bit output of the counter (138) and concatenates it with the latched
`
`m-bit portion of the address to create the internal addresses (ADDR_INT) that are
`
`used to address the memory array. Id. at 4:34-39; Ex-1002 ¶¶35-38
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`8
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 13 of 80
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`

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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`
`
`VII. PATENT PROSECUTION HISTORY
`The application that became the ’134 Patent was repeatedly rejected during
`
`prosecution and eventually allowed after the Examiner did not file a response to
`
`the applicant’s appeal brief.
`
`On 10/1/2001, the Examiner rejected the 17 pending claims, rejecting
`
`dependent claims 6 and 15 (which recite that the burst length is programmed by
`
`“bond options”) under 35 U.S.C. §112 paragraph 1 because the specification did
`
`not sufficiently support that concept. Ex. 1004 (File History) at 42. All claims
`
`were also rejected as anticipated by Yip (U.S. 6,289,138). Id. at 42-44. The
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`applicant responded on 2/4/2002, and with respect to the Section 112 rejections,
`
`stated:
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`9
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 14 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`Support for claims 5 and 15 may be found on page 8, lines 3-8 of the
`specification. Furthermore, bond options are well known in the art and,
`therefore, one skilled in the art would understand how to make and/or
`use bond options. Copies of U.S. patents 6,188,636 (issued February
`13, 2001), 5,900,021 (issued May 4, 1999) and 5,360,992 (issued
`November 1, 1994) from the USPTO web site (www.uspto.gov) are
`attached as evidence of bond options being well known in the art.
`Id. at 62. Regarding the 102 rejections, the applicant argued that Yip did not
`
`disclose “the generation of a predetermined number of internal address signals that
`
`is non-interruptible, as presently claimed.” Id. at 63. Specifically, the patentee
`
`argued that Yip discloses a write burst “can be interrupted when there is a cycle
`
`request from a higher priority port…” Id. at 64. The applicant added three
`
`additional claims.
`
`On 4/25/2002, the Examiner rejected claims 1-20 as anticipated by Cowles
`
`(US 5,729,504). Id. at 70-73. The applicant responded on 6/26/2002, arguing the
`
`internal address bursts were not non-interruptible, and added an additional claim.
`
`Id. at 83. The applicant asserted that “Cowles teaches that a low to high transition
`
`of the WE* signal within a burst write access to the memory array 112 will
`
`terminate the burst access, preventing further writes from occurring . . . .” Id. at
`
`84 (emphasis original).
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`On 10/22/2002, the Examiner repeated and made final the Cowles rejection.
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`Id. at 89. In response, the applicant argued that Cowles did not teach that the burst
`
`memory accesses were non-interruptible. Id. at 115. The Examiner rejected those
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`10
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 15 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`arguments in an Advisory action, and the applicant appealed, raising the same
`
`arguments on appeal. Id. at 14-16. The Examiner filed no responsive brief but
`
`instead issued a Notice of Allowance, conceding that Cowles disclosed “to
`
`terminate a continuous burst read operation, the WE signal merely has to transition
`
`high prior to a falling edge of the CAS signal (see, for example, Cowles). [T]hus
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`prior art of record does not teach or fairly suggest the non-interruptible generation
`
`of a predetermined number of internal address signals.” Id. at 172 (emphasis
`
`original); Ex-1002 ¶¶39-42.
`
`VIII. LEVEL OF ORDINARY SKILL IN THE ART
`At the time the ’134 Patent was filed, a person of ordinary skill in the art
`
`would have had a bachelor’s degree in electrical or computer engineering, applied
`
`physics, or a related field, and at least two years of experience in design,
`
`development, and/or testing of memory circuits, related hardware design, or the
`
`equivalent, with additional education substituting for experience and vice versa.
`
`Ex-1002 ¶43.
`
`IX. CLAIM CONSTRUCTION
`Petitioner interprets the ’134 Patent’s claims according to Phillips. 83 Fed.
`
`Reg. 51340, 51340-44 (Oct. 11, 2018); Phillips v. AWH Corp., 415 F.3d 1303
`
`(Fed. Cir. 2005). Certain terms of the ’134 Patent were previously construed in the
`
`792 Investigation (Order No. 29, Feb. 9, 2012) and in Cypress Semiconductor
`
`11
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 16 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`Corp. v. GSI Tech., Inc., No. 13-cv-02013-JST (N.D. Cal July 29, 2014), attached
`
`hereto as Exhibits Ex-1011 and Ex-1012, respectively. The construction of the
`
`following claim terms may be relevant to this proceeding.
`
`A.
`“non-interruptible” (claims 1, 16, 17)
`The ’134 Patent specification defines “non-interruptible” as follows:
`
`Once the circuit 102 has started generating the fixed number of
`addresses, the circuit 102 will generally not stop until the fixed number
`of addresses has been generated (e.g., a non-interruptible burst).
`Ex. 1001 (’134 Patent) at 3:3:36-28.1 During prosecution, however, the applicant
`
`distinguished prior art disclosing a generally continuous address burst, arguing
`
`that any disclosure describing the possibility of terminating a burst rendered that
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`burst not “non-interruptible,” as was discussed above in the summary of the file
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`history, suggesting a narrower construction. In the 792 Investigation, the parties
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`agreed that “non-interruptible” means “cannot be stopped or terminated once
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`initiated until the fixed number of internal addresses has been generated.” Ex-1011
`
`at 12-13.
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`Nevertheless, the Board need not resolve that issue here, as the prior art
`
`applied to the claims discloses this limitation under the narrower construction
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`(cannot be stopped). Ex-1002 ¶¶44-46.
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`
`1 Emphasis is added unless stated otherwise.
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`12
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 17 of 80
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`B.
`
`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`“means for reading data . . . / means for generating a
`predetermined number of said internal address signals” (claim
`16)
`During prosecution, the applicant agreed that claim 16 (then claim 12)
`
`should be construed as means-plus-function under pre-AIA 35 U.S.C. §112(6),
`
`although the applicant did not identify the claimed function or corresponding
`
`structure. Ex. 1004 (File History) at 129, 131, 146, 167. Claim 16 includes two
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`“means” clauses: (a) “means for reading data from and writing data to a plurality
`
`of storage elements in response to a plurality of internal address signals,” and (b)
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`“means for generating a predetermined number of said internal address signals in
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`response to (i) an external address signal, (ii) a clock signal, and (iii) one or more
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`control signals, wherein said generation of said predetermined number of internal
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`address signals is non-interruptible.”
`
`The function recited in element (a) is “reading data from and writing data to
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`a plurality of storage elements in response to a plurality of internal address
`
`signals.” The corresponding disclosed structure is the memory array 104 depicted
`
`in Figure 1 (annotated below) and described as “a static random access memory
`
`(SRAM), a dynamic random access memory (DRAM), or other appropriate
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`memory to meet the design criteria of a particular implementation.” Ex. 1001
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`(’134 Patent) at 2:34-38. The memory array 104 includes an address input 118 that
`
`receives a plurality of internal address signals, and a DATA_OUT line 124, and a
`
`13
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 18 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`DATA_IN line 122 for reading data from and writing data to the memory. Id. at
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`2:44-29.
`
`
`
`The function in element (b) is “generating a predetermined number of said
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`internal address signals in response to (i) an external address signal, (ii) a clock
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`signal, and (iii) one or more control signals, wherein said generation of said
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`predetermined number of internal address signals is non-interruptible.” The
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`corresponding structure is the “burst address counter/register 102” implemented
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`either as shown in (1) Figure 2, described at 3:62-4:14 or (2) Figure 3, described at
`
`4:15-39, or their equivalents. In annotated Figures 2 and 3 below, the logic blocks
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`highlighted in yellow generate a predetermined number of internal address signals
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`(ADDR_INT) in response to (i) an external address signal (green) (ii) a clock
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`signal (blue) and (iii) one or more control signals (red). While Figure 2 uses a
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`counter that increments the entire n-bit address, Figure 3 splits the address into two
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`parts and increments only the bottom k bits, concatenating them with the m top bits
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`to generate the n-bit internal address signals. Ex-1002 ¶¶47-49.
`
`14
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 19 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`
`
`C.
`“external address signal” (claims 1, 13, 15-17)
`In the 792 Investigation, the parties agreed that “external address signal”
`
`means “an address signal that originates outside of the circuit.” Ex-1011 at 12.
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`Petitioner applies the prior art here consistent with that construction. Ex-1002 ¶50.
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`D.
`“burst” (claim 2)
`In the 792 Investigation, the parties agreed that “burst” means “a number of
`
`words transferred as a group.” Ex-1011 at 13. Petitioner applies the prior art here
`
`consistent with that construction. Ex-1002 ¶51.
`
`E.
`“internal address signal” (claims 1, 2, 12, 15-17)
`In the 792 Investigation, the ALJ construed this term to mean “an address
`
`signal that is generated within the circuit claimed by the preamble.” Id. at 15. The
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`order was referring to claim 1, in which the preamble reads “a circuit comprising.”
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`Thus, the “internal address signal” is generated within the circuit, as opposed to
`
`arriving from outside. Petitioner applies the prior art here consistent with that
`
`15
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 20 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
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`construction. Ex-1002 ¶53.
`
`F.
`“logic circuit” (claims 1, 12)
`In the 792 Investigation, the ALJ construed this term to mean “a circuit that
`
`is designed to perform one or more logic operations or to represent logic
`
`functions.” Petitioner applies the prior art here consistent with that construction.
`
`Ex-1002 ¶53.
`
`G.
`
`“predetermined number of [said] internal address signals”
`(claims 1-4, 12, 15-17)
`In the 792 Investigation, the ALJ construed this term to mean “a fixed
`
`number of internal address signals for a burst access.” The Commission later
`
`affirmed a narrower reading by the ALJ, finding that a prior-art reference fixing
`
`the burst length before a data transfer by using a mode register did not disclose a
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`“predetermined number” because it could be programmed. Ex-1013 at 24-25.
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`This implied construction appears overly narrow, given that dependent claim 5
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`requires that “the fixed burst length is programmable.” The ITC’s construction
`
`limits the claims to programming at manufacture time, such as by bond options or
`
`voltage levels (see claims 6 and 7). However, the Board need not resolve this
`
`issue, as Petitioner relies on prior art disclosing “predetermined number” under the
`
`narrower interpretation adopted by the ITC (fixed or programmable at manufacture
`
`time using bond options or voltage levels). Ex-1002 ¶54.
`
`16
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 21 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`H.
` “memory” (claims 1, 8-9, 14, 17)
`In the Cypress District Court litigation, this term was construed to mean
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`“addressable storage.” Ex-1012 at 3, 8. Petitioner applies the prior art here
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`consistent with that construction. Ex-1002 ¶55.
`
`I.
`“address signal” (claims 1-4, 10-13, 16-17)
`In the Cypress District Court litigation, this term was construed to mean “a
`
`signal for determining the address location in the memory array from which data is
`
`read to [sic] or to which data is written.” Ex-1012 at 4, 8. Petitioner applies the
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`prior art here consistent with that construction. Ex-1002 ¶56.
`
`X.
`
`SPECIFIC EXPLANATION OF GROUNDS
`A. Ground 1: Claims 1-3, 8, 12-13, 16, and 17 are anticipated by US
`6,115,280 (“Wada”)
`1. Wada
`Wada was filed April 4, 1997 and issued September 5, 2000, qualifying as
`
`prior art under at least pre-AIA 35 U.S.C. §102(e). Ex-1005 (Wada) at 1.
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`Wada is entitled “Semiconductor memory capable of burst operation.” Id. at
`
`1. Wada discloses numerous embodiments of “a semiconductor memory operating
`
`in burst mode” comprising “a semiconductor memory comprising a memory cell
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`array, a plurality of output registers, an output register selecting circuit, a counter
`
`circuit, a data output pin, and an output data transfer circuit.” Id. at 5:67, 6:14-17.
`
`“This makes it possible to output a plurality of target data items in burst mode
`
`17
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1023, IPR2021-00702
`Page 22 of 80
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`U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
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`without interruption therebetween.” Id. at 6:59-61.
`
`Wada discloses “a typical conventional SRAM operating in burst mode.” Id.
`
`at 1:22-23; Figs. 12-14