United States Patent (19)
`Tiede et al.
`
`USOO5900021A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,900,021
`May 4, 1999
`
`54 PAD INPUT SELECT CIRCUIT FOR USE
`WITH BOND OPTIONS
`
`75 Inventors: John William Tiede; Jon Allan Faue,
`both of Colorado Springs, Colo.
`73 Assignees: United Memories, Inc., Colorado
`Springs; Nippon Steel Semiconductor
`Corporation, Chiba, Japan
`
`21 Appl. No.: 08/833,105
`22 Filed:
`Apr. 4, 1997
`51) Int. Cl. ............................... G06F 12/00; G11C 7/00
`52 U.S. Cl. ................ 711/170; 365/189.02; 365/230.02
`58 Field of Search ....................... 711/170; 365/189.02,
`365/230.02; 395/653
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,551,634 11/1985 Takahashi et al..
`4,825,099 4/1989 Barton ..................................... 307/270
`5,373,470 12/1994 Jones, Jr. ........................... 365/189.05
`5,406.525 4/1995 Nicholes.
`5,572,718 11/1996 Scriber et al..
`... 327/108
`5,600.271
`2/1997 Erickson et al......
`... 365/201
`5,706.235
`1/1998 Roohparvar et al.
`5,757,704 5/1998 Hachiya ............................. 365/189.02
`
`FOREIGN PATENT DOCUMENTS
`0 198429 A2 10/1986 European Pat. Off..
`O 513968 A2 11/1992 European Pat. Off..
`2 271 449 4/1994 United Kingdom.
`Primary Examiner Tod R. Swann
`ASSistant Examiner Tuan V. Thai
`Attorney, Agent, or Firm-Richard A. Bachand; Stuart T.
`Langley; Holland & Hart llp
`57
`ABSTRACT
`A configurable input device for an integrated circuit having
`a plurality of input pads, the input device including a
`plurality of buffers, where each buffer is associated with one
`of the input pads. Each buffer receives a mode Select Signal
`and the buffer is responsive to the mode Select Signal to place
`the buffer in an enabled mode or a disabled mode. A receiver
`portion within each buffer is coupled to the associated input
`pad. The receiver portion pulls the associated input pad to a
`preselected logic state while the buffer is in the disabled
`mode. An output driver within each buffer generates an
`output signal responsive to a signal on the associated input
`pad while the buffer is in the enable mode and provides a
`high impedance while the buffer is in the disabled mode. An
`output node is coupled to the output drivers of the plurality
`of buffers.
`
`18 Claims, 5 Drawing Sheets
`
`TIMING AND
`CONTROLSIGNAL
`GENERATOR
`
`-1 1Of
`
`RAS
`WE
`315
`
`X16 UCAS
`X8 CAS
`X16 LCAS
`OE
`CONFIG
`310
`
`PAD INPUT
`
`SELECT
`CERCUT
`
`
`
`
`
`
`
`
`
`MEMORY
`CEL ARRAY
`
`
`
`
`
`
`
`
`
`
`
`ROW ADDRESS
`BUFFER
`
`COUMN
`ADDRESSBUFFER
`
`OUTPUT
`CONTROL
`
`DATA
`OUT
`BUFFER
`
`DATA
`N
`BUFFER
`
`DATA
`OUT
`BUFFER
`
`
`
`DATA
`N
`BUFFER
`
`314
`
`313
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 1 of 12
`
`

`

`U.S. Patent
`U.S. Patent
`
`May4, 1999
`May 4, 1999
`
`Sheet 1 of 5
`Sheet 1 of 5
`
`5,900,021
`5,900,021
`
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 2 of 12
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 2 of 12
`
`

`

`U.S. Patent
`
`May 4, 1999
`
`Sheet 2 of 5
`
`5,900,021
`
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 3 of 12
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 3 of 12
`
`
`
`
`
`
`

`

`U.S. Patent
`
`May 4, 1999
`
`Sheet 3 of 5
`
`5,900,021
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 4 of 12
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 4 of 12
`
`
`

`

`U.S. Patent
`
`May 4, 1999
`
`Sheet 4 of 5
`
`5,900,021
`
`PADA
`
`BUFFERA
`ENABLE
`
`MODEA
`SELECT
`
`BUFFER/DRIVER A
`
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`513
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`ENABLE
`
`MODEB
`SELECT
`
`515
`
`514
`
`512
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 5 of 12
`
`

`

`U.S. Patent
`
`May 4, 1999
`
`Sheet 5 of 5
`
`5,900,021
`
`VCC
`6O1
`Ju?
`X8 CAS
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`603
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`BUFFER
`ENABLE
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`
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`SELECT
`
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`PAD
`
`X16 CAS
`BUFFER
`ENABLE
`
`X16
`SELECT
`
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`6O2
`
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`---------
`----------
`X16 BUFFER/DRIVER
`
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`
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`
`611
`
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`
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`
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`
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`612
`614
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 6 of 12
`
`

`

`1
`PAD INPUT SELECT CIRCUIT FOR USE
`WITH BOND OPTIONS
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates, in general, to Semiconduc
`tor integrated circuits, and, more particularly, to a circuit for
`configuring input devices in an integrated circuit.
`2. Relevant Background
`In the production and manufacturing of different types of
`integrated circuits (ICs) it is desirable to have a single IC
`that can be packaged to operate with different interfaces. For
`example, a random access memory (RAM) may be config
`ured as a “by-16” device or a “by-8' device. When config
`ured as a by-16 device, the RAM receives sixteen data bits
`at Sixteen data input/output (I/O) pins. These input data bits
`represent a single 16-bit word that is stored in the RAM at
`a location determined by address bits received at the address
`pins. In a by-8 device only eight bits of data are input to the
`RAM at one time.
`For a given memory size (e.g., a 4 megabyte (MB)
`dynamic random access memory (DRAM)) much of the
`internal circuitry of a by-16 device can be identical to that
`of a by-8 device. However, the external control and data
`Signals that are applied to the device differ between the two
`configurations. For example, a 4 MB by-16 device is typi
`cally packaged in a 40-pin plastic Small outline J-lead (SOJ)
`or a 44-pin thin, small-outline package (TSOP) to provide an
`adequate number of pins for the 16-bit wide data bus. A 4
`MB by-8 device, however, is typically packaged in a 28-pin
`SOG or 28-pin TSOP package. With respect to control
`Signals, a by-16 device may require two column address
`strobe (CAS) signals or two write enable (WE) signals to
`Separately activate columns in lower and upper memory
`banks within the chip. In contrast, a by-8 device uses a single
`CAS and WE signal, together with an additional address bit,
`to access data Stored in both the upper and lower banks.
`In spite of the great similarity between by-16 and by-8
`devices from the Standpoint of internal circuitry, most manu
`facturers must produce two separate IC designs to account
`for the different pin-outs and control Signals. A by-16 device
`may be realized as an entirely different chip design and
`layout from the by-8 device, or the chips may differ only by
`customization of one or more metal layers. In either case, a
`particular chip must be committed to a by-8 or a by-16
`design during the wafer fabrication process.
`From a manufacturing efficiency Standpoint, it is desirable
`to fabricate multiple device configurations using a single
`integrated circuit design. Not only is design time used more
`efficiently, but a Single chip design Simplifies Scheduling and
`work flow in a wafer fabrication facility. Because the
`Semiconductor fabrication process takes Several weeks to
`process raw Substrates into packaged electronic devices, a
`great deal of effort is placed in predicting customer orderS So
`that finished goods are available when customers demand.
`For these reasons, it is desirable to be able to select the
`configuration of a Semiconductor device as late as possible
`in the manufacturing process.
`Many configurable circuits are available that allow the
`end-user to change the configuration after the manufacturing
`proceSS is completed. Examples include field programmable
`gate arrays (FPGAS) and programmable logic devices
`(PLDs). However, these circuits tend to be cost prohibitive
`except for Specialized applications. In cost Sensitive markets
`Such as exists for memory devices, user-configurable cir
`
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`cuits are usually impractical. What is needed is a config
`urable input circuit that allows configuration to be chosen
`late in the manufacturing process, preferably during the
`assembly and packaging Stages.
`Semiconductor devices are manufactured to meet industry
`Standards for functionality and performance. These Stan
`dards dictate the packaging and pin-out configuration of
`most Semiconductor devices. This Standardization allows
`commodity devices Supplied by one manufacturer to be
`Substituted for those of another manufacturer. Any internal
`circuitry used to enable configurability must be implemented
`in a manner that allows compliance with industry Standards,
`and does not adversely impact device functionality, perfor
`mance and reliability.
`SUMMARY OF THE INVENTION
`Briefly Stated, the present invention involves a config
`urable input device for an integrated circuit having a plu
`rality of input pads, the input device including a plurality of
`buffers, where each buffer is associated with one of the input
`pads. Each buffer receives a mode Select Signal and the
`buffer is responsive to the mode Select Signal to place the
`buffer in an enabled mode or a disabled mode. A receiver
`portion within each buffer is coupled to the associated input
`pad. The receiver portion pulls the associated input pad to a
`preselected logic state while the buffer is in the disabled
`mode. An output driver within each buffer generates an
`output signal responsive to a signal on the associated input
`pad while the buffer is in the enable mode and provides a
`high impedance while the buffer is in the disabled mode. An
`output node is coupled to the output drivers of the plurality
`of buffers.
`In another aspect, the present invention involves a method
`for configurably coupling an input pad to an internal circuit
`node of an integrated circuit. In accordance with the method
`a mode Select Signal is provided on a mode Select node. A
`Selected one of the plurality of input pads is coupled to an
`internal circuit node in response to the mode Select signal. A
`pull-down device is controlled to pull the unselected input
`pads to a first logical State in response to the mode Select
`Signal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 shows in outline form a representation of a first
`implementation of a memory circuit embodying the present
`invention;
`FIG. 2 shows in outline form a representation of a Second
`implementation of the memory circuit in accordance with
`the present invention;
`FIG. 3 shows in block diagram form a memory circuit
`embodying an pad input Select circuit in accordance with the
`present invention;
`FIG. 4 shows in block diagram form a first portion of a
`generic implementation of a configurable input circuit in
`accordance with the present invention;
`FIG. 5 illustrates in block diagram form a second portion
`of the generic implementation of the configurable input
`circuit in accordance with the present invention; and
`FIG. 6 illustrates a particular embodiment of the present
`invention in a memory device.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Typically, an input pad is coupled to a buffer circuit that
`may latch, invert, or simply buffer a Signal on the input pad.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 7 of 12
`
`

`

`15
`
`3
`The output of the buffer is then coupled through an internal
`circuit node to additional logic on the integrated circuit (IC).
`Often, the buffer output is gated by a power gating Signal
`that is generated by internal circuitry on the IC. This gating
`allows the input pads to be decoupled from the internal
`circuitry to prevent conflicts that may interfere with circuit
`performance. Gating is optional.
`As used herein, the term “configurable ICs” means
`devices that can be configured during manufacturing to
`operate in one of Several Selected modes. The term is not
`intended to include programmable logic or user configurable
`logic Such as programmable gate arrays unless Such devices
`also include configuration options that are fixed during
`manufacturing. Specifically, the present invention is directed
`to configuration options that are Selected during the pack
`aging process by, for example, bond wire options.
`Using bond options configuration, a mode Select Signal
`can be permanently provided to the IC by selectively bond
`ing mode configuration pads to ground or power busses.
`Combinatorial logic coupled to the mode configuration pads
`generates internal configuration signals that enable and/or
`disable portions of the internal circuitry to realize a desired
`configuration option. Because the mode Select Signals are
`chosen by permanent bonds, the configuration cannot be
`changed after packaging. However, bonding occurs very late
`in the IC manufacturing proceSS and allows great flexibility
`to Select the final device configuration to meet customer
`demand just before completing manufacturing.
`Bond options are an increasingly important feature in
`many modern Semiconductor devices, especially memory
`devices. By tying a configuration pad high or low it is
`possible to change the entire configuration of an IC. For
`example, a 4 MB DRAM can be organized as a 512Kx8
`device (i.e., a “by-8” device shown in FIG. 1) or as a
`256Kx16 device (i.e., a “by-16” device shown in FIG. 2)
`depending on the State of the configuration pad. In accor
`dance with the present invention, the same chip 101 can be
`used in either the configuration of FIG. 1 or FIG. 2. IC 101
`is not configured until bonds coupling pads 103 to device
`pins 102 and 202 are formed.
`Because bond options or mode configuration options are
`available on IC 101, the exact input pad 103 from which a
`control or data Signal may come may change depending on
`the configuration. For example, by-16 device 200 receives
`active-low upper CAS (labeled UCAS) and active-low lower
`CAS (labeled LCAS) control signals while by-8 device 100
`requires only one CAS Signal. AS used herein, a signal
`identifier designated with a bar indicates an active low
`Signal, while the absence of a bar indicates an active high
`signal. Input circuit 301 (shown in FIG. 3) in accordance
`with the present invention steers the correct input pad 103 to
`the internal circuit path where it is required. This allows
`various internal circuitry and circuit paths to function the
`Same regardless of the mode Specified by the bond option.
`Preferably, all of the unused input pads 103 are disabled.
`FIG. 3 shows an exemplary IC 101 incorporating a pad
`input select circuit 301 in accordance with the present
`invention. In the particular example, IC 101 is a 4 MB
`DRAM circuit that is configurable as a by-8 or a by-16
`60
`device. The configuration of IC 101 is accomplished by
`Setting the signal level on the configuration pad (labeled
`CONFIG) to select circuit 301. The preferred technique for
`setting the voltage level is to bond the CONFIG pad to either
`the VCC or the VSS power supply bus.
`A single CONFIG pad with a binary signal level will
`allow pad input select circuit 301 to select between two
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`configuration options. If more configuration options are
`desired, multiple binary CONFIG pads can be provided. In
`cases where only one CONFIG pad is used, the signal on the
`CONFIG pad can be used directly as a mode select signal in
`pad input select circuit 301. In cases where multiple CON
`FIG pads are used, pad input Select circuit will require
`additional combinatorial logic (not shown) to generate one
`or more mode Select Signals having desired properties to
`meet the needs of a particular application. Design and
`implementation of the combinatorial logic can be accom
`plished using available logic design techniques.
`Pad input select circuit 301 receives the active-low output
`enable (OE) signal, the active-low by-16 lower column
`address strobe (X16 LCAS on node 310), the active-low
`by-16 upper column address strobe (X16 UCAS on node
`315) and the active-low by-8 column address strobe (X8
`CAS on node 305) signals. Pad input select circuit 301
`serves to select one of the X16 UCAS and X8 CAS signals
`to couple as the modified active-low upper column address
`Strobe (UCAS) signal to timing and control signal generator
`302. Also, pad input select circuit 301 serves to select one of
`the X16 LCAS and X8 CAS signals to couple as the
`modified active-low lower column address strobe (LCAS)
`Signal to timing and control Signal generator 302. Pad input
`Select circuit 301 also generates one or more modified
`active-low output enable signals such as OE (L) and OE
`(U) to output control circuit 316 in the preferred implemen
`tation.
`Control signal generator 302 receives two active-low
`column address Strobe Signals as expected by a convention
`control signal generator used in a by-16 device. IC 101 has
`three input pads Supporting CAS Signals, of which only one
`or two are used for any Selected configuration. A first of the
`column address Strobe inputs is Selected from either the
`input pad coupled to node 305 or the input pad coupled to
`node 310 by input pad selector 301. A second of the column
`address Strobe inputS is Selected from either the input pad
`coupled to node 305 or the input pad coupled to node 315 by
`input pad selector 301. In accordance with the present
`invention, the unused input pad(s) are pulled to a selected
`power Supply Voltage to avoid problems associated with
`“floating input pads.
`To configure IC 101 as a by-8 device, the input pad
`coupled to node 305 is bonded to the CAS input pin of the
`industry standard package (e.g., a 28-pin SOJ package). The
`mode Select input is bonded to indicate a by-8 configuration
`causing pad input Select circuit 301 to Select the input pad
`coupled to node 305 as both the LCAS and UCAS outputs.
`Hence, when configured as a by-8 device, both CAS inputs
`to control Signal generator 302 come from the Single CAS
`provided by the industry Standard by-8 package.
`To configure IC 101 as a by-16 device, the input pad
`coupled to node 310 is coupled to X16 LCAS and the input
`pad coupled to node 315 is coupled to X16 UCAS. The
`mode Select input is bonded to indicate a by-16 configura
`tion causing pad input Select circuit 301 to Select the input
`pad coupled to node 310 as the LCAS output and the input
`pad coupled to node 315 as the UCAS output. Hence, when
`configured as a by-16 device, the CAS inputs to control
`signal generator 302 come from the dual CAS pins provided
`by the industry standard by-16 package (e.g., a 40 pin SOJ
`package).
`Pad input select circuit 301 also generates active-low
`upper and lower output enable signals OE (L) and OE (U)
`coupled to output control circuit 316. In a conventional
`by-16 design, two output enable signals are used to inde
`pendently enable data output buffers 312 and 314.
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 8 of 12
`
`

`

`S
`In this manner, pad input Select circuit 301 in accordance
`with the present invention enables the remainder of the
`circuitry shown in FIG. 3 to be substantially identical to a
`conventional by-16 memory device. Pad input Select circuit
`301 generates the expected Signals for a by-16 device So that
`downstream circuitry that is responsive to pad inputs need
`not be modified in order to function properly as either a by-8
`or a by-16 configured memory circuit. Timing and control
`Signal generator 302 generates required timing Signals to
`row address buffer 303 and column address buffer 304 to
`load address information A0-A9. For a by-8 device, all of
`A0-A9 are used, whereas for a by-16 device, A0-A8 are
`used. Invention does not impact or change column and row
`address method.
`Row address buffer 303 and column address buffer 304
`couple to row decoder 306 and column decoder 307 respec
`tively in a conventional manner. Row decoder 306 outputs
`row select signals to memory cell array 309 and column
`decoder 307 outputs column Select signals to Sense amplifier
`array 308 in a conventional manner. Sense amplifier array
`308 drives column lines within memory cell array 309 in a
`conventional manner. Together, row decoder 306, column
`decoder 307, and sense amplifier array 308 select a desired
`address space within memory cell array 309 for read and
`write operations. Data is coupled through Sense amplifier
`array 308 from data in and data out buffers 311,312,313 and
`314 in a conventional manner. U.S. Pat. No. 5,373,470
`describes Several circuits Suitable for implementation of data
`I/O circuits buffers 311-314 that are capable of configurably
`Steering data Signals to/from appropriate output pins in
`either a by-8 or by-16 configuration.
`FIG. 4 shows in block diagram form a first portion of pad
`input select circuit 301 in accordance with the present
`invention. FIG. 4 represents a receiver portion of the input
`pad select circuit 301 while FIG. 5 represents a buffer and
`output driver portion of input pad select circuit 301. It
`should be understood that FIG. 4 and FIG. 5 show a general
`implementation in accordance with the present invention
`while FIG. 6 shows a specific implementation useful in the
`memory circuit shown in FIG. 3.
`In FIG.4, a mode select signal such as the CONFIG signal
`shown in FIG. 3 is applied to inverter 401 to generate an
`inverted mode select signal on the MODE A SELECT line.
`The mode select signal is coupled directly to the MODE B
`SELECT line. In the examples herein, each device has two
`configurable modes that can be adequately identified by a
`Single bit binary mode Select signal and the complementary
`MODE A SELECT and MODE B SELECT lines. Where the
`modes are complementary, the only combinatorial logic
`required can be supplied by inverter 401. The present
`invention is also useful to Select one input pad from among
`three or more input pads, however. In these cases, more
`complex combinatorial logic could be used in place of
`inverter 401 to generate multiple MODE SELECT signals
`Such that only one input pad is Selected.
`Pad A is coupled to a Source/drain terminal of pull-down
`transistor 403. In the preferred embodiment, pull-down
`transistor 403 comprises an n-channel transistor having a
`Second Source/drain terminal coupled to a logic level Voltage
`supplied by V or ground. The gate of transistor 403 is
`controlled by the mode Select Signal Such that when the
`mode Select Signal is a logic high, transistor 403 is activated,
`and input pad A as well as the PADA Signal are pulled to
`logic low or ground. In this manner when the mode Select
`Signal is bonded to the V power Supply, input pad A is
`disabled and pulled to a logic low. When the mode select
`Signal is bonded to the ground or V power Supply, tran
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`sistor 403 is off and the PADA signal is passed from the
`input pad A to the circuitry shown in FIG. 5. This feature of
`the present invention ensures that the unselected input pad is
`tied to a fixed power Supply Voltage and not left floating.
`As shown in FIG.4, it is preferable that pull-down device
`403 is implemented as an N-channel transistor Such that the
`unselected input pad is pulled to ground. Alternatively,
`pull-down transistor 403 could be replaced by a p-channel
`pull-up transistor (not shown) to pull the unselected pad to
`a logic high (i.e., V). However, in a CMOS circuit built on
`a charge pumped p-type Substrate, p-channel Source/drain
`nodes form one terminal of a parasitic four layer PNPN
`Structure that has a greater tendency to latch up than does the
`Source/drain of an n-channel device built in the Same circuit.
`It is recommended that input pads, which are more likely to
`experience transients than internal circuitry, be coupled
`directly to only N-channel device S/D to avoid latch up.
`However, in Some applications p-channel pull-up devices
`may be adequate in which case they are equivalent to the
`preferred embodiment disclosed herein.
`Preferably, input pad select circuit 301 also includes
`power gating circuitry to generate an active-low BUFFERA
`ENABLE control signal used by the circuitry shown in FIG.
`5. Transmission gate 404 is responsive to the MODE B
`SELECT signal and the MODE A SELECT signal to pass
`the power gate signal when the MODE SELECT signal is a
`logic high and block the power gate signal when the MODE
`SELECT signal is a logic low. Also, transistor 405 is coupled
`to the MODE A SELECT signal to such that while the
`MODE B SELECT signal is a logic low (i.e., the MODE
`SELECT signal is a logic high) transistor 405 is on and the
`BUFFER AENABLE is tied to the V power supply.
`This configuration places the BUFFER AENABLE signal
`in a permanently disabled state when the MODE SELECT
`Signal is a logic high. Also, this configuration places the
`BUFFER AENABLE under control of the power gate signal
`when the MODE SELECT signal is a logic low.
`The receiver circuitry coupled to pad B at node 412 is
`substantially identical to the circuitry described above with
`respect to pad A at node 402. However, a gate of pull down
`device 413 is controlled by the BUFFER AENABLE line to
`pull pad B to the logic low Voltage while mode A is Selected.
`Transmission gate 414 passes the power gate Signal to the
`active-low buffer B enable line (BUFFER B ENABLE)
`while mode B is high, and transistor 415 is off while the
`MODE B SELECT signal is a logic high. In a complemen
`tary fashion, transmission gate 414 blocks the power gate
`signal and transistor 415 pulls the BUFFER BENABLE
`Signal to a logic high (i.e., disabled) while mode A is
`Selected.
`Pad input select circuit 301 can be configured to select
`from any desired number of input pads by duplicating the
`pull-down device 403, 413, transmission gate 404, 414 and
`transistor 405, 415 as well as providing multiple MODE
`SELECT signals to independently control each pad under
`control of the pad input Select Signal.
`Referring to FIG. 5, the PADA, BUFFER AENABLE,
`and MODE A SELECT lines are coupled to a buffer/output
`portion of input pad select circuit 301. Similarly, the PADB,
`BUFFER BENABLE, and MODE B SELECT lines are
`coupled to the buffer/output portion of input pad Select
`circuit 301. Transistors 501 and 502 form a buffer for the
`PADA signal. One source/drain of p-channel transistor 501
`is coupled to V and the gate of transistor 501 is coupled to
`the PADA signal. The output of transistor 501 is provided on
`the second Source/drain terminal of transistor 501. Transistor
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1007, IPR2021-00702
`Page 9 of 12
`
`

`

`7
`502 is preferably an N-channel transistor having a first
`Source/drain terminal coupled to ground or V and a second
`Source/drain terminal coupled to output node 510. Node 510
`is an output node of input pad Select circuit 301 and is
`coupled to internal circuitry of IC 101.
`The BUFFER AENABLE line is coupled to control the
`gates of p-channel transistor 503 and n-channel transistor
`504. When the BUFFER AENABLE line is a logic high,
`transistor 503 is off creating a high impedance between the
`output node of transistor 501 and output node 510. As set out
`hereinbefore, the BUFFER AENABLE signal is pulled to a
`logic high when MODE A SELECT is a logic low. Also, the
`PADA signal is pulled to a logic low by pull-down device
`403 shown in FIG. 4 when the MODE A SELECT signal is
`a logic low. The logic low PADA signal turns off transistor
`502. Hence, when the MODE A SELECT signal is a logic
`low all of the transistors coupled directly to output node 510
`from pad A are off. This minimizes the parasitic capacitance
`presented by the pad A buffer circuit (i.e., transistors
`501-505) while pad A is unselected.
`When the MODE A SELECT signal is a logic high,
`transistor 505 is on and the PADA signal follows the signal
`on input pad Ashown in FIG. 4. Also, when the MODE A
`SELECT signal is high the BUFFER AENABLE signal
`25
`follows the power gate Signal shown in FIG. 4. In the case
`that the BUFFER AENABLE is a logic high, transistor 504
`place pulls output node 510 low through transistor 505. In
`the case that the BUFFER A ENABLE is a logic low,
`transistor 503 couples the output of transistor 501 to output
`node 510, hence, node 510 is under the control of input pad
`A shown in FIG. 4.
`In a similar manner, transistors 511, 512, 513, 514, and
`515 selectively couple the PADB signal to output node 510
`while MODE B SELECT is high and BUFFER BENABLE
`35
`is low. While MODE B SELECT is low, all transistors
`directly coupled to node 510 in the B buffer are off and in
`a high impedance State to avoid loading node 510. Any
`number of output buffer/driver circuits such as shown in
`FIG. 5 can be used for each input pad under control of input
`pad Selector circuit 301 So long as only one is Selected.
`FIG. 6 illustrates a portion of particular embodiment of
`the present invention in a input pad select circuit 301 shown
`in FIG. 3. The circuit portion shown in FIG. 6 is used to
`select either the by-8 CAS or the by-16 LCAS for output to
`the modified LCAS Signal to timing and control Signal
`generator 302. The circuit portion shown in FIG. 6 is
`substantially duplicated to enable selection of either the by-8
`CAS or the by-16 UCAS to generate the modified UCAS)
`to timing and control Signal generator 302 as shown in FIG.
`50
`3
`While the by-8 SELECT line is high, the by-16 SELECT
`line is low. Hence, when the by-8 SELECT line is high, the
`by-16 LCAS pad is pulled low as described hereinbefore.
`Transistors 612, 613, and 615 are turned off to prevent
`loading of node 610 while the by-16 SELECT line is low. In
`contrast, transistor 605 is on, and transistor 603 is turned on
`under control of the by-8 CAS BUFFERENABLE signal.
`The by-8 CAS BUFFERENABLE signal is under control of
`a power gating Signal, if used.
`While the by-8 SELECT line is high, transistors 601 and
`602 that make up the by-8 input buffer are responsive to a
`Signal on the input pad designated to receive the active-low
`by-8 CAS signal. The signal at node 610 is thus controlled
`by the by-8 CAS signal when by-8 CAS BUFFERENABLE
`is low, and is pulled to a logic low by transistor 604 when
`the by-8 CAS BUFFERENABLE is high. In the particular
`
`45
`
`55
`
`60
`
`65
`
`5,900,021
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`15
`
`40
`
`8
`implementation shown in FIG. 6, node 610 is the inverse of
`the Signal on the Selected input pad because transistorS 601
`and 602 form an inverting buffer.
`While the by-8 SELECT line is low, the by-16 SELECT
`line is high. Hence, when the by-16 SELECT line is high, the
`active-low by-16 LCAS pad is pulled low as described
`hereinbefore. Transistors 602, 603, and 605 are turned off to
`prevent loading of node 610 while the by-8 SELECT line is
`low. In contrast, transistor 615 is on, and transistor 613 is
`turned on under control of the by-16 CAS BUFFER
`ENABLE signal. The by-16 CAS BUFFERENABLE signal
`is under control of the power gating Signal, if used.
`While the by-16 SELECT line is high, transistors 611 and
`612 that make up the by-16 input buffer are responsive to a
`Signal on the input pad designated to receive the active-low
`by-16 CAS signal. The signal at node 610 is thus controlled
`by the by-16 CAS signal when the by-16 CAS BUFFER
`ENABLE is low, and is low by transistor 614 when the
`by-16 CAS BUFFERENABLE is high. In the particular
`implementation shown in FIG. 6, node 610 is the inverse of
`the Signal on the Selected input pad because transistorS 611
`and 612 form an inverting buffer.
`Signal conditioning circuitry 620 affects the delay and
`edge characteristics of the output UCAS Signal in a con
`ventional manner and can be implemented in any manner
`appropriate for a particular application. The modified output
`enable signal OE (L) is generated by NOR gate 621 having
`a first node coupled to node 610 and a Second node coupled
`to receive the active-high output enable signal (OE) from an
`output enable buffer (not shown). The OE signal is supplied
`to IC 101 through and external pin in the industry standard
`package for either an by-8 or by-16 configuration.
`Although the invention has been described and illustrated
`with a certain degree