(12) United States Patent
`Fujioka et al.
`
`I 1111111111111111 11111 111111111111111 lllll lllll lllll 111111111111111 11111111
`US006185149Bl
`US 6,185,149 Bl
`Feb.6,2001
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`MEMORY
`
`(75)
`
`Inventors: Shinya Fujioka; Masao Taguchi;
`Yasuharu Sato; Takaaki Suzuki;
`Tadao Aikawa; Yasurou Matsuzaki;
`Toshiya Uchida, all of Kawasaki (JP)
`
`(73) Assignee: Fujitsu Limited, Kawasaki (JP)
`
`( *) Notice:
`
`Under 35 U.S.C. 154(b), the term of this
`patent shall be extended for O days.
`
`(21) Appl. No.: 09/340,147
`
`(22) Filed:
`
`Jun. 28, 1999
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 30, 1998
`
`(JP) ................................................. 10-185097
`
`Int. Cl.7 ....................................................... GllC 8/00
`(51)
`(52) U.S. Cl. .................. 365/233; 365/230.03; 365/238.5
`(58) Field of Search ..................................... 365/233, 220,
`365/203, 238.5, 221, 239, 230.03
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,386,385
`5,647,287
`5,703,828
`5,781,499 *
`
`1/1995
`7/1997
`12/1997
`7/1998
`
`Stephens, Jr .................... 365/189.05
`McLaury et al. ............... 365/230.01
`Park et al.
`...................... 365/230.03
`Kohikawa ............................ 365/233
`
`5,808,959 * 9/1998 Kengeri et al. ...................... 365/233
`5,812,488 * 9/1998 Zagar et al.
`......................... 365/233
`6,094,380 * 7/1998 Kim ..................................... 365/194
`
`FOREIGN PATENT DOCUMENTS
`
`0 778 575 A2
`
`6/1997 (EP) .
`
`OTHER PUBLICATIONS
`
`International Publication No. WO 98/19248, published May
`7, 1998.
`* cited by examiner
`Primary Examiner-Richard Elms
`Assistant Examiner-Hien Nguyen
`(74) Attorney, Agent, or Firm-Arent Fox Kitner Plotkin &
`Kahn PLLC
`
`(57)
`
`ABSTRACT
`
`A semiconductor memory includes memory cell blocks, a
`burst-length information generating circuit which generates
`burst-length information based on a burst length, and a block
`enable circuit which receives the burst-length information.
`The block enable circuit selectively enables one of the
`memory cell blocks when the burst length is equal to or
`shorter than a predetermined burst length and selectively
`enables a plurality of memory cell blocks based on the burst
`length when the burst length is longer than the predeter(cid:173)
`mined burst length. Data are read from the above-mentioned
`one or plurality of memory cell blocks.
`
`16 Claims, 20 Drawing Sheets
`
`CI.K
`
`/CS
`
`/WE
`
`AO
`
`An
`
`DQ
`
`bsprx
`
`BANK-! CIRCUIT
`
`INTERNALLY GENERATED
`INTERLEAVE SIGNAL
`GENERATING CIRCUIT
`
`,_..--+----~
`BANK ADDRESS
`INTERNALLY
`GENERATED
`
`ROW ACTIVATION
`CIJ,\MAND INTERNALLY
`GENERATED
`
`BURST-LENGTH
`
`INFORMATION (bl8)
`
`BANK SELECT SIGNAL (baz)
`
`ADDRESS
`
`17
`
`outp
`~---<DQ
`CONTROLLER
`
`psclk
`
`P/S
`- - - - - - - - - - - - - - e - - - - 4
`
`SENSE BUFFER
`ENABLE SIGNAL
`(sbez)
`
`SENS AMP
`ENABLE
`SIGNAL
`
`16
`
`COMMON DATA BUS
`
`( c d b)
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 1 of 32
`
`

`

`U.S. Patent
`U.S. Patent
`
`FIG.1 PRIORART
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`Feb. 6, 2001
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`US 6,185,149 Bl
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 2 of 32
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 2 of 32
`
`

`

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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 3 of 32
`
`

`

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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 4 of 32
`
`

`

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`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 5 of 32
`
`

`

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`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 6 of 32
`
`

`

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`
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`
`F I G. 6
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 7 of 32
`
`

`

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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
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`
`-----------------+-------\----------+-----, (brasOz)
`
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`COMMAND
`
`F I G. 7
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 8 of 32
`
`

`

`U.S. Patent
`
`Feb.6,2001
`
`Sheet 8 of 20
`
`US 6,185,149 Bl
`
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`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 9 of 32
`
`

`

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`(INTERNAL
`
`FROM BANK O FROM BANK 1 FROM BANK O FROM BANK 1
`
`outp -------------1
`
`DQ
`
`m ITT mm[[) ITT mm[[) mm m [[)mm m [[)mm m
`cdbx/z __________ _, , ___ ___J ------''-----' ..._ ___ _, -----
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`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 10 of 32
`
`

`

`,1;;;..
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`
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`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 11 of 32
`
`

`

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`rJ'l
`e
`
`'° ~
`
`i,-
`
`0
`N
`
`'""" 0 ....,
`'"""
`~ ....
`'JJ. =(cid:173)~
`
`'"""
`0
`0
`N
`~~
`?'
`~
`"!"l
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`423
`
`42'2
`
`DFF
`
`' I ou,t·~·' 'T ~.1~.}ddl'
`
`swddl
`
`•• ~
`
`I
`
`•
`
`CIRCUIT
`SHIFTER
`: LATCH&LEVEL-
`c····················..l~ ....... ~dO( '7f +··· ·~; d ___ do_· ------.
`
`·
`:
`
`ddl:
`
`IT
`
`'
`. :1 out
`
`;
`
`430
`
`0
`0
`::,
`::,
`.......
`+-'
`P. 0.
`.......
`0
`N
`N
`
`0..0.0..0..
`Cl) Cl) Cl) (I'.)
`<J<JUU
`........... ..--f,..--f,..--f,
`..:.:::..:.:::..:.:::..:.:::
`o...-.NOO
`NNNN
`
`18a (18b)
`
`OFF
`
`408
`
`OFF
`
`407
`
`--i
`406
`
`OFF
`
`OFF
`
`·•········..c 460
`
`405
`
`0.
`0
`...-.
`N
`
`F I G. 11
`
`=······························cts:··· = ..•................
`)·
`.
`.
`. .
`!:~
`
`d3+--t) • •
`sw4n I -.I
`
`I
`
`d2__;_-y-.
`
`poOz
`
`404
`
`OFF
`
`403
`
`:
`
`• I • I >I
`
`•
`
`' swl4
`II •
`
`)I OFF 1
`
`I \ l 1 I r402
`
`. '
`
`•
`
`J:.:..w2n
`
`--
`
`=
`
`ct1
`
`···········1 ....
`450
`
`440 dO'
`
`I
`(401
`
`)I OFF
`
`~
`,...................................
`
`•) • .I •
`swl3 swl2
`
`dO _:___ ..__
`
`-!swln
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 12 of 32
`
`

`

`U.S. Patent
`
`Feb.6,2001
`
`Sheet 12 of 20
`
`US 6,185,149 Bl
`
`FIG. 12
`
`~ BL=4
`caaO, lz --
`swln
`close
`sw2n
`close
`sw3n
`close
`open
`sw24
`open
`sw14
`open
`swl3
`open
`swl2
`
`BL=2
`H/-
`open
`open
`close
`close
`open
`close
`open
`
`L/-
`close
`close
`close
`open
`open
`open
`open
`
`BL=l
`H/L
`open
`close
`close
`open
`open
`open
`close
`
`L/H
`open
`close
`close
`open
`open
`close
`open
`
`L/L
`close
`close
`close
`open
`open
`open
`open
`
`H/H
`open
`close
`close
`open
`close
`open
`open
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 13 of 32
`
`

`

`,1;;;..
`i,(cid:173)
`-..(Ji
`~
`i,(cid:173)
`_,.a-...
`rJ'J.
`e
`
`'° ~
`
`i,-
`
`0
`N
`0 ....,
`'"""' ~
`~ ....
`'JJ. =(cid:173)~
`
`'"""'
`0
`0
`N
`~~
`?'
`~
`"'!"j
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`LATCHlNG DATA IN SECOND REGlSTER
`
`IN OFF OF SECOND REGISTER
`ACQUIRING DATA OF FIRST REGISTER
`
`polz
`
`poOz
`
`d ( 1. 3] ------..
`d(0,3] --~
`
`tl
`
`lN OFF OF FlRST REGlSTER
`
`LATCHfNG DATA (d( 0 -----3])
`
`FIG. 13
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 14 of 32
`
`

`

`U.S. Patent
`U.S. Patent
`
`Feb.6, 2001
`Feb.6,2001
`
`Sheet 14 of 20
`Sheet 14 of 20
`
`US 6,185,149 B1
`US 6,185,149 Bl
`
`••••••••••• ••••••••••• •••• .1.._-4-_-:-; ••••••••••.
`
`0
`
`•••••••••••••••••••••••••• ..1....--+---:-: ..•.•.•.••.
`
`0
`
`·•••••••·•· .•..•...•..••.• ..1-_4-~ .• •········
`
`••••••••••• ••••••••••• •••• ..1.....--1--..:-:-•••••••••.
`
`0
`
`••••• ••·····••••·••••· ••.• .L.--+--<-..••••••••.
`
`0
`
`..... ················· ····-'---1---:";; .. ·········
`
`FIG,14
`
`(cid:127)
`(9
`
`LL
`
`0
`
`0
`
`psclk[0-3]z
`
`N
`,.......,
`C"J
`I
`0
`..:.:::
`u
`(£2
`
`0 -
`
`ddO
`
`-0
`-0
`
`ddl
`
`-0
`-0
`
`DQ
`O'
`0
`
`outp(0,1}z
`
`N
`,.......,
`
`c5
`0..
`
`:::i
`0
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 15 of 32
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 15 of 32
`
`

`

`U.S. Patent
`
`Feb. 6, 2001
`
`Sheet 15 of 20
`
`US 6,185,149 Bl
`
`FIG. 15A
`
`~ BL=4
`BL=l
`BL=2
`outpOz clocking clocking clocking
`outplz clocking clocking
`
`FIG. 15B
`
`~ BL=4
`BL=2
`BL=l
`clocking clocking clocking
`psclklz
`clocking clocking
`psclk2z
`clocking
`psclk3z
`clocking
`psclkOz
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 16 of 32
`
`

`

`U.S. Patent
`
`Feb.6,2001
`
`Sheet 16 of 20
`
`US 6,185,149 Bl
`
`FIG. 16A
`
`clkz
`
`507
`
`1 n -+-----1
`
`508
`i--...._ ____ ---1 )0------4.,_ au t
`
`---- ------' :
`
`510
`
`FIG. 168
`
`LATCH PERIOD
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 17 of 32
`
`

`

`U.S. Patent
`
`Feb.6,2001
`
`Sheet 17 of 20
`
`US 6,185,149 Bl
`
`FIG. 17A
`
`519
`
`,
`
`..........
`-
`'
`.,.,,
`•
`I
`' I
`'
`
`I
`
`I
`
`1n - - -
`
`516
`
`clkz
`
`·---------
`
`FIG. 178
`
`out
`
`Buffer
`Hi-z
`OUT
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 18 of 32
`
`

`

`U.S. Patent
`
`Feb.6,2001
`
`Sheet 18 of 20
`
`US 6,185,149 Bl
`
`FIG. 18
`
`523
`. . ... . . [ .....
`I :
`Vccq
`:
`
`I
`
`I
`
`525
`, ....... [ .... .
`Vccq
`
`I
`I
`I
`I
`I
`
`' ' I
`'
`
`_--i-__._~] -.547
`
`I
`I
`
`Vssq 1
`--------------·
`
`524
`..•.... [ .•.••
`Vccq
`:
`
`I
`
`I
`I
`
`521
`•..•••••...•••..... [ ..... .
`
`Vssq
`······------------···--·--·-·
`522
`··················r..·······
`Vccq
`
`I
`
`ddO'
`ddl'
`
`ddO'
`ddl'
`
`539
`
`---.--~ -... 548
`
`I
`
`:
`Vssq
`-------------·
`
`Vssq
`·- ------. -----
`
`Vssq
`
`I••••••••••••••••••••••••••
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 19 of 32
`
`

`

`,1;;;..
`i,(cid:173)
`-..(Ji
`~
`i,(cid:173)
`-..a-...
`rJ'J.
`e
`
`'° ~
`
`i,-
`
`0
`N
`0 ....,
`'"""' \0
`~ ....
`'JJ. =(cid:173)~
`
`'"""'
`0
`0
`N
`~~
`?'
`~
`"'!"j
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`:
`:
`:
`,
`:
`'--;
`••··•··••···•·•········•••··
`12 b '-: • • • • • • • • • • · · · · • • · • • • · · • • • •
`12c, \ •.••..•.....•.•...••....
`
`~ r---+--HI--I
`§
`~
`
`(cid:144)
`
`20
`
`swl
`
`__ ,., ~
`__ ,, =
`11
`
`BLOCK
`
`BANK-0 CIRCUIT
`
`BANK-I CIRCUIT
`
`12d
`
`13
`12a
`
`SIGNAL
`ENABLE
`BLOCK
`
`( c d b)
`
`COMMON DATA BUS
`
`18 a _____ .J "
`CONVERTER ~
`
`CTP/S ~----:
`
`I
`
`r
`
`I...__ 16
`
`SENSE BUFFER
`
`db "'
`
`Rg
`
`14
`...
`!·
`•;1
`
`SIGNAL
`ENABLE
`SENS AMP
`
`--
`.__ __
`
`...........
`8:
`@----✓1
`~ ..__,_....___,.'-I
`
`.., = 0
`
`S/A
`
`J ! r1sb
`
`90
`
`COUNTER 1------,1--,1----1
`ADDRESS 1-----...:+-~---1
`
`psclk
`
`CONTROLLER
`DQ
`
`17
`
`outp
`
`L19
`
`1€
`
`BUFFER
`DQ --i OUTPUT
`
`DATA
`
`ADDRESS
`
`r
`...
`
`BANK SELECT SIGNAL (baz)
`
`BURST-LENGTH INFORMATION (blB)
`
`clkcount
`
`Ao-r-1-"1r--
`
`I
`
`BUFFER
`ADDRESS
`
`An --+j
`
`3
`
`. REG I STER
`
`SET
`REGISTER: ;
`MODE ~-, MODE
`
`J4
`
`....... ~..........
`CONTROL
`TIMING
`.---~----..
`10
`
`--r--,........,~
`
`brasz
`
`,........._....___,
`
`DECODER
`COt,t.tAND 1-------------------' _____ __."'-1
`.-----"--,
`
`COlttdAND SIGNAL
`
`2
`
`5
`
`/WE
`/CS
`
`......------.......,
`
`GENERATING CIRCUIT
`INTERLEAVE SIGNAL
`INTERNALLY GENERATED
`
`COUNTER
`CLOCK
`
`bsprx
`
`1-----+ TO EACH BLOCK
`
`CL Kl
`
`BUFFER
`
`CLOCK
`
`CLK-+
`
`F I G. 1 9
`
`ENABLE SIGNAL
`SENSE BUFFER
`
`(sbez)
`
`', -
`J~
`) r
`,; I COi.MAND INTERNALLY
`
`GENERATED
`
`ROW ACTIVATION
`
`GENERATED
`INTER~LU
`BANK ADDRESS
`....---1-------
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 20 of 32
`
`

`

`,1;;;..
`i,(cid:173)
`-..(Ji
`~
`i,(cid:173)
`_,.a-...
`rJ'J.
`
`'° ~
`
`i,-
`
`e
`
`~ ....
`'JJ. =(cid:173)~
`
`0
`N
`0 ....,
`0
`N
`
`'"""'
`0
`0
`N
`~~
`?'
`~
`"'!"j
`
`~ = ......
`~ ......
`~
`•
`r:JJ.
`d •
`
`16-BIT BURST TO RDO(B)
`h
`FROM BANK 0
`(cid:141)1----..
`
`FROM BANK l
`
`16-BIT BURST TO RDO(A)
`
`FROM BANK O
`(cid:141)I(cid:141)
`
`FROM BANK l
`
`' ..
`
`' ' '--4
`' ''
`
`' .... ~, .......
`
`,..-,..
`
`' '
`
`FROM BANK 0
`1----11----I(cid:141)
`0111 21 31°111 21 310111213101112131 0111213101
`
`-4.
`
`''' ,...,_
`' '
`
`' '' ' ' ' '
`
`oa
`
`bras 1 z ________________ _
`
`j ADDRESS(B1)
`
`~
`
`COUNT UP
`
`ADDRESS(B0)
`
`I
`
`\
`
`\
`
`\
`
`\
`
`ADD~f;:SS(A 1)
`
`' ' ' ' '
`~
`COUNT UP
`' '
`
`j
`
`AD'b{3ESS(AO)
`
`' '
`
`j
`
`\
`
`\
`
`' ' '
`
`\
`
`\
`
`\
`
`\
`
`ADDRESS(B1)
`
`~
`COUNT UP
`
`l
`
`'
`\ ADDRESS(BO)
`
`\\
`
`J1
`II
`
`: ',
`
`I
`\
`I\
`
`ADDRESS(Al)
`
`J
`
`~
`COUNT UP
`
`RDO(B) •
`FIG. 20
`
`'
`\ ADDRESS(AO)
`
`\
`
`'
`
`address I
`
`BANKl
`
`brasOz
`
`\
`
`\
`
`\
`
`address°--j 1
`I
`I
`I
`I
`I
`\
`I\
`~
`
`BANKO
`
`CLOCK
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 21 of 32
`
`

`

`US 6,185,149 Bl
`
`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`MEMORY
`
`BACKGROUND OF THE INVENTION
`
`5
`
`15
`
`2
`turned ON. In that state, the data on the bit lines BL and /BL
`are read by the sense amplifier 220 via the NMOS transistors
`203 and 204. Then, the sense amplifier 220 amplifies the
`data on the bit lines BL and /BL, and the amplitude between
`the bit lines BL and /BL is increased. At that time, data
`stored in the memory cells connected to the selected word
`line are read and amplified by the respective sense amplifiers
`220.
`Thereafter, a column line select signal CL switches to the
`10 high level in response to the column address strobe signal
`/CAS, and the corresponding column is selected. Then, the
`NMOS transistors 210 and 211 of the selected column gate
`are turned ON, and the amplified data on the bit lines BL and
`/BL are read to the data bus lines DB and /DB.
`In order to successively read data related to the same row
`address (the same word line) in the single-bank
`configuration, different columns are sequentially selected by
`sequentially setting the column line select signals to the high
`level. Hence, the data already stored in the sense amplifiers
`20 and specified by the different column address values are
`sequentially read. When the burst length L is equal to 4, 4
`consecutive bits of data can be read as shown in FIG. 2.
`Thereafter, the precharge command is input. Hence, the
`precharge signal PR is switched to the high level at an
`appropriate timing. Hence, the NMOS transistors 207, 208
`and 209 are turned ON, and the bit lines BL and /BL are set
`to a given potential VPR. Hence, the bit lines BL and /BL are
`reset, and are ready to the next control signal (R or W).
`However, when the commands (R), (C) and (PRE) are
`input again in order to read data from a different row address
`(different word line), it is required to newly read data from
`the memory cells newly selected by the above commands
`and output the read data to the bit lines BL and /BL. In the
`single-bank configuration, it is required to precharge the bit
`lines BL and /BL in order to newly output data to the bit lines
`BL and /BL. Hence, a long blank period equal to 10 clocks
`occurs until the next data are read, as shown in FIG. 2.
`In order to fill up the blank period, a bank interleaving
`method is employed in the SDRAM of the multi-bank
`configuration. In the bank interleaving method, command
`are applied so that a plurality of banks are sequentially
`selected and data are sequentially output from each selected
`bank at the respective timings. As shown in the lower part
`of FIG. 2, the commands are sequentially applied to banks
`0 and 1. Hence, read data from the bank 1 can be output
`during the 10-clock blank period related to the bank 0.
`There is an FCRAM, which is one of the semiconductor
`memories. A description will be given of the difference
`between the SDRAM and the FCRAM and a data read
`timing control of the FCRAM. The configuration of the
`peripheral circuits of the memory cells of the FCRAM is the
`same as that of the SDRAM.
`In the first difference, the FCRAM is configured so that a
`plurality of columns are read at one time and data are read
`from the sense amplifiers 220 in parallel. Hence, it is
`sufficient to drive the sense amplifiers 220 during a fixed
`period. That is, the operation period of the sense amplifiers
`220 can be set to a constant length regardless of the burst
`60 length BL. For instance, the operation periods of the ampli(cid:173)
`fiers 220 with BL equal to 1 are the same as those with BL
`equal to 4. Hence, a reliable pipeline operation of the row
`system can be realized.
`In the second difference, the FCRAM employs an internal
`precharge signal (which corresponds to the precharge signal
`(PRE) employed in the SDRAM). The internal precharge
`signal is used to automatically perform the reset operation.
`
`1. Field of the Invention
`The present invention generally relates to semiconductor
`integrated circuit memories, and more particularly to a
`semiconductor integrated circuit memory which operates in
`synchronism with a clock.
`Recently, semiconductor memory devices such as DRAM
`(Dynamic Random Access Memory) devices have been
`required to input and output data at higher frequencies in
`accordance with speeding up of CPUs so that the data
`transmission rate can be increased.
`An SDRAM (Synchronous DRAM) device and FCRAM
`(Fast Cycle RAM) can operate at a high speed in synchro(cid:173)
`nism with a clock signal supplied from the outside of the
`device.
`2. Description of the Related Art
`FIG. 1 illustrates a circuit configuration of a periphery of
`a memory cell of the SDRAM. The circuit shown in FIG. 1
`includes a capacitor 201, NMOS (N-channel Metal Oxide
`Semiconductor) transistors 212, 223 and 224, and PMOS
`(P-channel MOS) transistors 213, 221 and 222. The PMOS 25
`transistors 221 and 222 and the NMOS transistors 223 and
`224 form a sense amplifier 220.
`The capacitor 201, which forms a memory cell, can store
`one-bit data. The data stored in the capacitor 201 is read onto
`a pair of data bus lines DB and /DB as follows.
`FIG. 2 is a timing chart of a read operation of the SD RAM
`having the memory cell peripheral circuit shown in FIG. 1.
`A description will now be given of a timing control of the
`data read operation with reference to FIGS. 1 and 2.
`At the time of reading data, commands are sequentially
`applied to the SDRAM. More particularly, the SDRAM is
`supplied with a precharge command (PRE), a row address
`strobe signal /RAS (R), and a column address strobe signal
`/CAS (C). The precharge command is used to precharge a
`pair of bit lines BL and /BL to a predetermined potential.
`The row address strobe signal /RAS is used to select a
`memory cell block of the row system from a core circuit of
`the SDRAM, that is, to select a word line. The column
`address strobe signal /CAS is used to select a column, that
`is, the sense amplifier 220. The core circuit includes a
`plurality of memory cells 201 that are arrayed in the row and
`column directions. Each column is provided with the respec(cid:173)
`tive sense amplifier 220. Hence, the selected sense amplifier
`220 senses data from the memory cell connected to the
`selected word line.
`When the row address strobe signal /RAS is input to the
`SDRAM, a bit line transfer signal BLT0 is switched to the
`low level. At that time, a bit line transfer signal BLTl is at
`the high level, and the NMOS transistors 203 and 204 are in 55
`the conducting states. Hence, the bit lines BL and /BL are
`connected to the sense amplifier 220. Simultaneously, a
`precharge signal PR is switched to the low level, and thus the
`bit lines BL and /BL are released from the reset state.
`Then, a sub word line select signal SW is selected so that
`it is switched to the high level. Hence, the corresponding
`word line is selected, and the NMOS transistor 202 is caused
`to conduct. Hence, data stored in the capacitor 201 is read to
`the bit line BL.
`Then, sense amplifier drive signals SAl and SA2 are 65
`activated in order to drive the sense amplifier 220. Thus, the
`NMOS transistor 212 and the PMOS transistor 213 are
`
`30
`
`35
`
`40
`
`45
`
`50
`
`Petitioner STMICROELECTRONICS, INC.,
`Ex. 1001, IPR2021-00702
`Page 22 of 32
`
`

`

`US 6,185,149 Bl
`
`4
`between an increased number of pairs of bit lines connected
`to the selected word line are simultaneously amplified and
`the pairs of bit lines are simultaneously reset. This causes a
`delay in the read operation.
`It is preferable that the core size be as small as possible
`in order to speed up the read operation. This, however, leads
`to a reduction in the number bits which can be simulta(cid:173)
`neously read in parallel. Nowadays, there is a requirement
`that a large number of bits of data can be simultaneously
`10 read at a higher speed. Such a tradeoff requirement cannot be
`satisfied at the present time.
`
`SUMMARY OF THE INVENTION
`
`15
`
`It is a general object of the present invention to provide
`semiconductor integrated circuit memory in which the above
`disadvantages are eliminated.
`A more specific object of the present invention is to
`provide a semiconductor integrated circuit memory in which
`a large number of bits of data can be simultaneously read at
`a higher speed.
`The above objects of the present invention are achieved
`by a semiconductor memory comprising: memory cell
`blocks; a burst-length information generating circuit which
`25 generates burst-length information based on a burst length;
`and a block enable circuit which receives the burst-length
`information. The block enable circuit selectively enables
`one of the memory cell blocks when the burst length is equal
`to or shorter than a predetermined burst length and selec-
`30 tively enables a plurality of memory cell blocks based on the
`burst length when the burst length is longer than the prede(cid:173)
`termined burst length.
`
`3
`The automatic reset operation utilizes the fact that the sense
`amplifiers operate during only the constant period. The
`precharge operation is carried out at an appropriate timing
`immediately after data are read from the sense amplifiers
`220. Hence, it is possible to realize the data read operation 5
`in fast cycles close to the critical driving capability of the
`sense amplifiers 220.
`In the third difference, the FCRAM has the read cycle in
`random access shorter than that of the SDRAM. This is
`because the FCRAM employs the pipeline operation and the
`self-precharge operation. For example, when the burst
`length BL is equal to 4 as in the case of the SDRAM, the
`4-bit parallel data read from the sense amplifiers are con(cid:173)
`verted into serial data. Hence, data can serially be read
`without any interruption.
`FIG. 3 is a timing chart of the data read operation of the
`FCRAM having the memory peripheral circuits shown in
`FIG. 1. The data read timing control of the FCRAM will be
`described with reference to FIGS. 1 and 3. The burst length
`BL of read data is equal to 4 as in the case of the SDRAM 20
`shown in FIG. 2.
`In response to an activation command (AC1), a signal
`RASZ is generated in the FCRAM. The signal RASZ
`instructs data of the memory cells 201 to be latched in the
`sense amplifiers 220. Further, in the FCRAM, generated are
`main and sub word line select signals MW and SW, the bit
`line transfer signal BLT, and the sense amplifier drive signals
`SAl and SA2 at respective appropriate timings. Hence, data
`stored in the memory cells 201 appear on the bit lines BL,
`and are latched and amplified in the sense amplifiers 220.
`Further, the internal precharge signal PRE is generated in
`the FCRAM when a given time elapses after the signal
`RASZ is received.
`Furthermore, in response to the read command (RD), the 35
`column line select signals CL related to the column selected
`by the column address are switched to the high level, and
`data stored in the sense amplifier 220 are read out to the data
`bus lines DB and /DB. The data thus read are 4-bit parallel
`data, which are converted into serial data. Finally, the serial 40
`data is output to the outside of the FCRAM as read data DQ.
`As shown in FIG. 3, the internal precharge signal PRE
`generated in the FCRAM resets the bit line transfer signal
`BLT and the word line select signals MW and SW, and
`precharges the bit lines BL and /BL to the given potential.
`The timing of the precharge operation responsive to the
`internal precharge signal PRE is placed immediately after
`the data are read from the sense amplifiers 220 in response
`to the column line select signals CL.
`In the FCRAM, commands are received in a packet 50
`formation in order to reduce the intervals between the
`commands. As shown in FIG. 3, the activation command
`(AC1) and the read command (RD) are input as a single
`packet which extends over two cycles.
`When the data read operation is repeatedly carried out,
`data can serially be read without any interruption with the
`burst length BL equal to four because the read cycle of the
`random access is comparatively short. That is, the FCRAM
`does not need the bank interleaving method employed in the
`SDRAM.
`As described above, the FCRAM does not have the blank
`period which occurs in the SDRAM at the time of reading
`data, and can read data at a higher speed.
`Theoretically, as the number of bits of data to be simul(cid:173)
`taneously read in parallel increases, the burst length
`increases. This requires that the potential differences
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Other objects, features and advantages of the present
`invention will become more apparent from the following
`detailed description when read in conjunction with the
`accompanying drawings, in which:
`FIG. 1 is a circuit diagram of a peripheral circuit con(cid:173)
`figuration of a memory cell of an SDRAM;
`FIG. 2 is a timing chart of a conventional data read
`operation of the SDRAM;
`FIG. 3 is a timing chart of a data read operation of a
`45 conventional FCRAM;
`FIG. 4 is a block diagram of a semiconductor memory
`according to an embodiment of the present invention;
`FIG. 5 is a block diagram illustrating a sequence of a RAS
`generating unit and an internal interleave generating circuit
`shown in FIG. 4;
`FIG. 6 is a block diagram of a clock counter shown in
`FIG. 4;
`FIG. 7 is a circuit diagram of the RAS generating circuit
`and the internal interleave generating circuit shown in FIG.
`55 4;
`
`60
`
`FIG. 8 is a timing chart of a data read operation of the
`memory shown in FIG. 4 performed when the burst length
`is equal to 4;
`FIG. 9 is a timing chart of a data read operation of t