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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG DISPLAY CO., LTD.,
`Petitioner,
`
`v.
`
`JOLED INC.,
`Patent Owner.
`
`Case No. IPR2021-00677
`U.S. Patent No. 10,198,992
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO.
`10,198,992 UNDER 35 U.S.C. §§ 311–319 AND 37 C.F.R. § 42.100 et seq.
`
`
`
`

`

`Exhibit
`1001
`1002
`1003
`1004
`1005
`
`1006
`
`1007
`1008
`1009
`
`1010
`1011
`1012
`
`1013
`1014
`
`1015
`1016
`1017
`1018
`
`1019
`
`1020
`
`1021
`
`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`LIST OF EXHIBITS
`
`
`Description
`U.S. Patent No. 10,198,992 (the “’992 patent”)
`File History for U.S. Patent No. 10,198,992
`U.S. Patent No. 6,175,345 (“Kuribayashi”)
`U.S. Patent No. 6,583,775 (“Sekiya”)
`Certified Translation of Japanese Laid-Open Patent Application
`No. 2001-210122A (“Takahara”)
`2021.02.03 JOLED Reply in Case ref.: 2 O 87/20 (District Court
`of Mannheim)
`European Patent No. EP 3,407,340
`2020.10.30 Nullity action against EP 3,407,340
`Improvement of Current-Voltage Characteristics in Organic
`Light Emitting Diodes by Application of Reversed-Bias Voltage
`(“Zou”)
`U.S. Patent No. 6,380,689 (“Okuda”)
`U.S. Patent No. 6,859,193 (“Yumoto”)
`Low-Temperature Polysilicon Thin-Film Transistor Driving with
`Integrated Driver for High-Resolution Light Emitting Polymer
`Display (“Kimura IEEE”)
`U.S. Patent Publication No. 2002/0033718 (“Tam”)
`International Publication No. WO 98/48403 of PCT/US98/08367
`(“Dawson PCT”)
`Japanese Laid-Open Patent Application No. 2001-210122A
`U.S. Patent No. 6,525,704 (“Kondo”)
`U.S. Patent No. 6,580,657 (“Sanford”)
`C. Tang, et. al. “Organic Electroluminescent Diodes” Applied
`Physics Letters, vol. 51, page 913 (1987) (“Tang APL”)
`2/8/21 Samsung’s Proposed Constructions in JOLED Inc., v.
`Samsung Electronics America, Inc. et al., Case No. 6:20-CV-
`00559-ADA (W.D. Tex.)
`2/8/21 JOLED’s Proposed Constructions in JOLED Inc., v.
`Samsung Electronics America, Inc. et al., Case No. 6:20-CV-
`00559-ADA (W.D. Tex.)
`Scheduling Order in JOLED Inc., v. Samsung Electronics
`America, Inc. et al., Case No. 6:20-CV-00559-ADA (W.D. Tex.)
`
`- ii -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`Description
`11/16/2020 JOLED Infringement Contentions in JOLED Inc., v.
`Samsung Electronics America, Inc. et al., Case No. 6:20-CV-
`00559-ADA (W.D. Tex.)
`Correspondence re JOLED dropping ’336 Claim 16
`U.S. Patent No. 6,323,631 (“Juang”)
`U.S. Patent No. 6,348,906 (“Dawson 906”)
`U.S. Patent No. 5,550,066 (“Tang 066”)
`Curriculum Vitae of Dr. Miltiadis Hatalis
`Declaration of Dr. Miltiadis Hatalis
`
`
`
`Exhibit
`1022
`
`1023
`1024
`1025
`1026
`1027
`1028
`
`
`
`
`- iii -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`
`
`B.
`
`Table of Contents
`I.
`Introduction ................................................................................................... 1
`Standing, Mandatory Notices, and Fee Authorization ............................. 3
`II.
`III. Summary of Challenge ................................................................................. 4
`IV. Overview of the ’992 Patent ......................................................................... 5
`A.
`The Challenged Independent Claims ............................................... 8
`B.
`Prosecution History ............................................................................ 9
`Level of Ordinary Skill ............................................................................... 10
`V.
`VI. Claim Construction .................................................................................... 10
`A.
`“a voltage line … being configured to supply a reverse bias
`voltage for reverse biasing the anode terminal of the EL
`device” (Claims 1, 8, 10) ................................................................... 10
`“a gate driver circuit including a first gate driver circuit
`connected to the plurality of first gate signal lines and a
`second gate driver circuit connected to the plurality of
`second gate signal lines” (Claims 1, 8, 10). ..................................... 12
`“the first gate driver circuit is configured to select the
`plurality of first gate signal lines as a block simultaneously”
`(Claims 6 and 14) / “selecting the plurality of first gate
`signal lines via the first gate driver circuit as a block
`simultaneously” (Claims 8) .............................................................. 13
`VII. Overview of the Prior Art .......................................................................... 14
`A. Kuribayashi ....................................................................................... 14
`B.
`Sekiya ................................................................................................. 16
`C.
`Takahara ........................................................................................... 19
`VIII. Unpatentability Analysis ............................................................................ 21
`
`C.
`
`- iv -
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`A. Ground I: Claims 1, 2, 4, 7, 10, 11, and 15 Are Unpatentable
`Under 35 U.S.C. § 103 Based on Kuribayashi in View of
`Sekiya ................................................................................................. 21
`1.
`Claim 1 .................................................................................... 22
`3.
`Claim 4 .................................................................................... 56
`5.
`Claim 10 .................................................................................. 60
`2.
`Claims 2 and 11 ...................................................................... 60
`4.
`Claims 7 and 15 ...................................................................... 66
`B. Ground II: Claims 3, 5, 6, 8, 9, and 12–14 Are Unpatentable
`Under 35 U.S.C. § 103 Over Kuribayashi in View of Sekiya
`and Takahara .................................................................................... 66
`1.
`Claims 3 and 12 ...................................................................... 67
`2.
`Claims 5 and 13 ...................................................................... 71
`3.
`Claims 6 and 14 ...................................................................... 77
`4.
`Claim 8 .................................................................................... 81
`5.
`Claim 9 .................................................................................... 82
`IX. Discretionary Denial Is Not Appropriate ................................................. 82
`A.
`Factor 1: Potential for a Stay Renders This Factor Neutral ........ 83
`B.
`Factor 2: Uncertainty in Litigation Schedule Favors
`Institution .......................................................................................... 83
`Factor 3: The District Court Has Not Invested Significant
`Resources ........................................................................................... 84
`Factor 4: Lack of Overlap in Issues Strongly Favors
`Institution .......................................................................................... 87
`Factor 6: The Petition’s Merits Are Strong and Favor
`Institution .......................................................................................... 88
`
`C.
`
`D.
`
`E.
`
`- v -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`X. Conclusion ................................................................................................... 89
`
`
`- vi -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`I.
`
`Introduction
`Samsung Display Co., Ltd. (“Petitioner”) petitions for inter partes review
`
`seeking cancellation of Claims 1–15 of U.S. Patent No. 10,198,992 (Ex. 1001, “’992
`
`patent”), assigned to JOLED, Inc. (“JOLED”).
`
`The ’992 patent relates to an electroluminescent (EL) display apparatus with
`
`circuitry configured to “supply a reverse bias voltage for reverse biasing the EL
`
`device [e.g., the organic EL film, or OLED]” of each pixel. ’992 patent, Abstract.
`
`The claims are directed to a specific pixel circuit configuration for implementing
`
`reverse biasing: one that incorporates a “driving” transistor, three “switch”
`
`transistors, and first and second “gate driver circuits” connected to the gates of the
`
`first and third switch transistors. Id., cls. 1, 8, 10. The first switch transistor controls
`
`the flow of current to the EL device, and is turned on and off periodically, to
`
`illuminate and extinguish the EL device. When the EL device is not illuminated, the
`
`third switch transistor is turned on to supply a reverse bias voltage to the EL device.
`
`See id.
`
`According to the ’992 patent, reverse biasing alleviates the accumulation of
`
`“space-charges” (electrons and holes) in the organic layer, “which deteriorate the
`
`film quality thereby lowering the luminance and causing a rise in driving voltage
`
`during constant-current driving.” Id., 65:53–60. Reverse biasing “causes the
`
`- 1 -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`electrons and positive holes injected to be withdrawn toward the cathode and the
`
`anode,” thus counteracting this undesirable accumulation. Id., 65:61–63.
`
`Reverse biasing to promote longevity of EL devices was well known by the
`
`time of the ’992 patent, as the prosecution history confirms. See, e.g., Ex. 1002, 277–
`
`91 (rejection citing Ex. 1010 (Okuda)). To secure the ’992 patent, the applicants
`
`amended their claims to specify (1) multiple (“first” and “second”) gate driver
`
`circuits to respectively turn on or off the first and third switch transistors, and (2)
`
`that a “lapse of time” occurs between the turning the first switch transistor off (to
`
`extinguish the EL) and turning the third switch transistor on (for reverse biasing).
`
`Yet this claimed configuration was not novel. The Kuribayashi reference,
`
`which was not before the Office during prosecution, taught an EL apparatus having
`
`substantially all of the independent claim limitations, including the allegedly novel
`
`“lapse of time” capability. While Kuribayashi does not describe the means for
`
`controlling its switch transistors in detail, a skilled artisan would have been
`
`motivated to use multiple gate driver circuits, as disclosed in the Sekiya reference,
`
`as this would have been the most straightforward way to achieve Kuribayashi’s
`
`teachings of flexibly turning the multiple switch transistors on and off at different
`
`points of time.
`
`As explained below, Claims 1, 2, 4, 7, 10, 11, and 15 of the ’992 patent are
`
`obvious based on Kuribayashi and Sekiya (Ground I), and Claims 3, 5, 6, 8, 9, and
`
`- 2 -
`
`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`12–14 are obvious based on these references in further combination with Takahara
`
`(Ground II).
`
`II.
`
`Standing, Mandatory Notices, and Fee Authorization
`Grounds for Standing: Pursuant to 37 C.F.R. § 42.104(a), Petitioner certifies
`
`that the ’992 patent is available for IPR and that Petitioner is not barred or estopped
`
`from requesting this IPR on the grounds identified herein.
`
`Real Party in Interest: Petitioner identifies Samsung Display Co., Ltd.,
`
`Samsung Electronics Co., Ltd., and Samsung Electronics America, Inc. as real
`
`parties in interest.
`
`Related Matters: JOLED has asserted the ’992 patent in a lawsuit against the
`
`real parties in interest captioned, JOLED Inc., v. Samsung Electronics America, Inc.
`
`et al., Case No. 6:20-CV-00559-ADA (W.D. Tex.). In addition, JOLED has asserted
`
`a related European Patent, EP 3 407 340 (“EP ’340”) in the District Court of
`
`Mannheim, Germany, Case Ref. No. 2 O 87/20, and Petitioner filed a parallel
`
`annulment action against EP 3 407 340 in the District Court of Mannheim. Ex. 1008.
`
`Lead and Backup Counsel: Lead counsel is David A. Garr (Reg. No. 74,932,
`
`dgarr@cov.com), and backup counsel are Peter P. Chen (Reg. No. 39,631,
`
`pchen@cov.com) and Rajesh D. Paul (Reg. No. 64,492, rpaul@cov.com). Service
`
`information is Covington & Burling LLP, 850 10th St. N.W., Washington, D.C.,
`
`20001, Tel.: 202.662.6000, Fax: 202.778.5485, and 3000 El Camino Real, 5 Palo
`
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`Alto Square, 10th Floor, Palo Alto, California 94306, Tel.: 650.632.4700, Fax:
`
`650.632.4800. Petitioner consents to electronic service by email: Samsung-JOLED-
`
`IPR@cov.com. A power of attorney is being filed concurrently.
`
`Fee Authorization: The Office is authorized to charge any fees due during
`
`this proceeding to Deposit Account No. 603160.
`
`III. Summary of Challenge
`Petitioner requests IPR of Claims 1–15 of the ’992 patent under 35 U.S.C.
`
`§ 103 based on the following prior art combinations:
`
`• Ground I: Claims 1, 2, 4, 7, 10, 11, and 15 are obvious over
`Kuribayashi in view of Sekiya.
`
`• Ground II: Claims 3, 5, 6, 8, 9, and 12–14 are obvious over
`Kuribayashi in view of Sekiya and Takahara.
`
`The ’992 patent was filed on December 29, 2017, and claims priority to a PCT
`
`application filed on September 6, 2002, as well as foreign applications as early as
`
`September 7, 2001. Each of the asserted references is available as prior art under
`
`pre-AIA 35 U.S.C. § 102 (pre-AIA),1 as shown in the following table.
`
`
`1 Pre-AIA Section 102 applies because the effective filing date for the ’992 patent
`
`is before March 16, 2013.
`
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`Exhibit
`
`Reference
`
`Dates
`
`May 28, 1998 (filed)
`January 16, 2001
`(issued)
`June 15, 2000 (filed)
`
`Prior Art
`Availability
`§ 102 (a),
`(b), (e)
`
`§ 102(e)
`
`Ex. 1003 U.S. Patent No. 6,175,345
`(“Kuribayashi”)
`
`Ex. 1004 U.S. Patent No. 6,583,775
`(“Sekiya”)
`Japanese Laid-Open
`Patent Application No.
`2001-210122A
`(“Takahara”)
`
`August 3, 2001
`(published)
`
`§ 102 (a),
`(b)
`
`Ex. 1005,
`translation
`Ex. 1015,
`original
`
`Grounds I and II are both based on prior art not discussed or relied on by the
`
`Examiner during the prosecution of the ’992 patent. Kuribayashi and Takahara were
`
`not before the Examiner. Although Sekiya was of record during prosecution, it was
`
`never discussed by the Examiner or the applicants. The declaration of Dr. Miltiadis
`
`Hatalis (Ex. 1028) submitted herewith was also not before the Examiner.
`
`Accordingly, the prior art and arguments in this Petition are not the same (or
`
`substantially the same) as those previously presented to the Office under 35 U.S.C.
`
`§ 325(d).
`
`IV. Overview of the ’992 Patent
`The ’992 patent is generally directed to an EL display apparatus (e.g., an
`
`organic EL display) using a matrix of pixels (i.e., pixel circuits), each of which
`
`includes an EL device whose illumination depends, for example, on the voltage
`
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`applied to that pixel. Id, 1:32–41. In other words, the voltage applied to the pixel
`
`causes a desired current to be fed to the EL device resulting in emission of light.
`
`’992 patent, 1:32–38; Ex. 1028, ¶ 52. The ’992 patent further describes circuitry for
`
`reverse biasing—a known technique for addressing the problem of space-charge
`
`accumulation in organic EL devices. ’992 patent, 65:53–67; Ex. 1028, ¶¶ 54–55.
`
`The patent illustrates a configuration for reverse biasing in which a switch
`
`transistor (11g(N)) has its gate terminal held to a fixed voltage potential (via line
`
`473) and its drain terminal connected (via line 471) to the output of a drive circuit:
`
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`See ’992 patent, Figs. 47–51, 54.
`
`
`
`The ’992 claims, however, specify a configuration in which the transistor used
`
`for reverse biasing (the “third switch transistor”) has its gate terminal connected to
`
`- 7 -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`a “second gate signal line” (driven by a “second gate driver circuit”), id., cls. 1, 8,
`
`10, as opposed to a fixed voltage line, id., Fig. 47 (line 473).2
`
`A. The Challenged Independent Claims
`The ’992 patent contains three independent claims: Claims 1, 8, and 10. Claim
`
`1 is reproduced below:
`
`
`
`
`
`Claims 1 and 10 are identical except for the last limitations, which recite
`
`different “lapse of time” sequences. Whereas Claim 1 specifies a lapse of time
`
`
`2 In the parallel district court case, Petitioner has contended that the claims are
`
`invalid under 35 U.S.C. § 112, ¶ 1, in view of such differences between the claims
`
`and the disclosure.
`
`- 8 -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`between turning on the first switch transistor and turning off the third switch
`
`transistor, Claim 10 specifies a lapse of time between turning off the third switch
`
`transistor and turning on the first switch transistor.
`
`Method Claim 8 requires that “the first gate signal lines are divided into a
`
`plurality of blocks” and “are connected as one control line,” and adds a step of
`
`“selecting the plurality of first gate signal lines as a block simultaneously.”
`
`Prosecution History
`B.
`The Notice of Allowability for the ’992 patent’s application indicates that the
`
`purported novelty of Claims 1 and 10 lies in the use of “first” and “second” “gate
`
`driver circuit[s]” and the “lapse of time” functionality. See Ex. 1002, 345. This
`
`Notice further indicates that the purported novelty of Claim 8 lies in the use of “first”
`
`and “second” “gate driver circuit[s],” the “gate-line-block” configuration, and
`
`“selecting … simultaneously” operation. See id., 345–46.
`
`The Examiner had previously rejected the original independent claims, citing
`
`a Yamazaki reference as disclosing the majority of the claimed pixel circuit features,
`
`and further finding that “[i]t would have been obvious … to have included the system
`
`of reverse-biasing the anode terminal of the EL device as taught by Okuda into …
`
`Yamazaki in order to prevent the EL device from breaking down and extend the life
`
`of the EL device.” Id., 277–79, 281–85.
`
`- 9 -
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`

`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`The applicant did not challenge the Examiner’s findings; instead, the applicant
`
`made narrowing amendments to the original independent claims, adding (i) the
`
`“first” and “second” “gate driver circuits” requirement for Claims 1, 8, and 10; (ii)
`
`the “lapse of time” requirement for Claims 1 and 10; and (iii) the “block”
`
`configuration and “simultaneous selection” requirements for Claim 8. Ex. 1002,
`
`310–22.
`
`V. Level of Ordinary Skill
`A person of ordinary skill in the art (“POSA”) of the ’992 patent at the time
`
`of the alleged invention would have had a relevant technical degree in electrical
`
`engineering, computer engineering, computer science, or the like, and 2–3 years of
`
`experience in active matrix display technology. Ex. 1028, ¶ 27.
`
`VI. Claim Construction
`Petitioner contends that no specialized constructions are necessary for this
`
`IPR. However, meanings of certain claim limitations are discussed below.
`
`A.
`
`“a voltage line … being configured to supply a reverse bias voltage
`for reverse biasing the anode terminal of the EL device” (Claims 1,
`8, 10)
`Neither Petitioner nor JOLED proposed to construe this term in the related
`
`district court litigation (Exs. 1019, 1020), and no construction is necessary here.
`
`Petitioner notes that in the German proceeding identified above, JOLED has
`
`accused Petitioner of infringement of the related EP ’340 patent, which recites a
`
`similar claim term (italicized below):
`
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`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`EP ’340 Claim Term
`a third switch transistor (11g)
`provided between the anode terminal
`of the EL device (15) and a reverse
`bias voltage line (471), the reverse
`bias voltage line (471) configured to
`supply a reverse bias voltage (Vm)
`for reverse biasing the anode
`terminal of the EL device (15)
`
`Ex. 1007 (EP ’340), cl. 1
`
`In the German proceeding, JOLED has argued that the EP ’340 term above
`
`’992 Claim Term
`a third switch transistor provided
`between the anode terminal of the EL
`device and a voltage line, … the voltage
`line being configured to supply a reverse
`bias voltage for reverse biasing the
`anode terminal of the EL device
`
`
`’992 patent, cl. 1
`
`excludes embodiments in which (i) the “voltage line” supplies a voltage for reverse
`
`biasing the anode terminal that is the same as the voltage applied to the anode during
`
`the forward-bias state, and (ii) the EL cathode terminal voltage is changed between
`
`the forward- and reverse-bias states. See Ex. 1006, 23.
`
`To the extent JOLED proposes a similar construction in response to this
`
`Petition, it should be rejected. The plain language of the claims does not specify
`
`particular voltages for reverse biasing and forward biasing—let alone provide that
`
`the same voltage cannot be used—and the intrinsic record provides no support for
`
`such a disclaimer of claim scope. See, e.g., Openwave Sys., Inc. v. Apple Inc., 808
`
`F.3d 509, 513 (Fed. Cir. 2015) (disavowal of claim scope must be “clear” and
`
`“unmistakable”).
`
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`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`Unlike the ’992 patent claims, the EP ’340 claims expressly recite a “constant
`
`… voltage” at the cathode terminal, and that the “reverse bias voltage” be a “negative
`
`voltage”:
`
`Corresponding ’992 Claim Term
`“an EL device including an anode
`terminal and a cathode terminal”
`
`N/A
`
`N/A
`
`EP ’340 Claim Term
`“an EL device (15) including an anode
`terminal and a cathode terminal, the
`cathode terminal being connected
`directly to a constant common
`reference voltage”
`“wherein during a reverse biasing
`period, the reverse bias voltage, which
`is a negative voltage relative to the
`constant common reference voltage, is
`supplied to the anode terminal of the
`EL device (15),”
`“wherein both during the reverse
`biasing period and during a lighting
`state period of the EL device (15), the
`constant common reference voltage is
`supplied to the cathode terminal of the
`EL device (15).”
`
`By contrast, the ’992 patent claims do not speak to the voltage applied to
`
`
`
`cathode terminal, nor do they require that the reverse-bias voltage be a “negative
`
`voltage” (or any particular voltage).
`
`B.
`
`“a gate driver circuit including a first gate driver circuit connected
`to the plurality of first gate signal lines and a second gate driver
`circuit connected to the plurality of second gate signal lines”
`(Claims 1, 8, 10).
`In the related district court proceeding, Petitioner has sought to construe this
`
`term to mean “a gate driver circuit which contains two separate shift registers, the
`
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`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`first shift register controlling and connected to the first gate signal lines and the
`
`second shift register controlling and connected to the second gate signal lines, and
`
`which may contain other circuitry,” while JOLED has contended that the term
`
`requires no construction. Exs. 1019, 1020.
`
`Petitioner submits that this term need not be construed for this IPR, because
`
`the prior art teaches the claim limitation under either interpretation, as explained for
`
`Element 1[f], infra. See Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co.,
`
`868 F.3d 1013, 1017 (Fed. Cir. 2017) (claim terms need only be construed “to the
`
`extent necessary to resolve the controversy”).
`
`C.
`
`“the first gate driver circuit is configured to select the plurality of
`first gate signal lines as a block simultaneously” (Claims 6 and 14)
`/ “selecting the plurality of first gate signal lines via the first gate
`driver circuit as a block simultaneously” (Claims 8)
`In the related district court proceeding, Petitioner has sought to construe the
`
`first term to mean “the first gate driver circuit is configured to output an on voltage
`
`to the control line, which applies the voltage simultaneously to the plurality of first
`
`gate signal lines as a block,” and the second term to mean “outputting an on voltage
`
`by the first gate driver circuit to the control line, which applies the voltage
`
`simultaneously to the plurality of first gate signal lines as a block,” while JOLED
`
`has contended that neither term requires construction. Exs. 1019, 1020.
`
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`

`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
`
`Petitioner submits that this term need not be construed for this IPR, because
`
`the prior art teaches the claim limitation under either interpretation, as explained for
`
`Element 6[c], infra.
`
`VII. Overview of the Prior Art
`A. Kuribayashi
`U.S. Patent No. 6,175,345 (Ex., 1003, “Kuribayashi”) is a U.S. patent filed
`
`May 28, 1998, and issued January 16, 2001. It is prior art under Sections 102(a), (b),
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`and (e). Kuribayashi was not identified during prosecution.
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`Kuribayashi discloses an active matrix organic electroluminescent (OLED)
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`display that uses reverse biasing. Kuribayashi, 1:51–57, 6:1–6. Kuribayashi
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`identifies a problem with conventional devices: “that long-term application of dc
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`voltage” would “promote deterioration of the organic electroluminescence
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`members.” Id., 1:40–47. Kuribayashi’s solution is to apply a reverse-bias voltage to
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`the EL devices.
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`Figure 10 of Kuribayashi depicts an active matrix configuration for a display
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`having EL devices for blue (BEL), green (GEL), and red (REL) pixels:
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`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
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`Each of the pixel circuits include four transistors (Tr1, Tr2, Tr3, and Tr4). Tr1
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`is referred to as a “logic transistor” that functions as a switching device for
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`programming a given pixel, and Tr2 is a driving transistor for controlling “excitation
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`power to the EL device” of the pixel. Id., 6:19–30, Fig. 1.
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`Tr3 is positioned on the current path of the driving transistor Tr2 and the EL
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`device, and is used to forward-bias the EL device during “a predetermined emission
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`period” (i.e., illumination period). Id., 11:37–43; Ex. 1028, ¶ 80.
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`Tr4 is positioned between the EL device and a ground potential line, and is
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`used to apply a reverse bias voltage to the EL device. Kuribayashi, 11:44–50; Ex.
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`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
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`1028, ¶ 81. With respect to the “lapse of time” requirement, Kuribayashi further
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`teaches that Tr4 may be turned on after Tr3 is turned off. Kuribayashi, 11:48–50
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`(control signal pulses “are applied gate on pulses … to the gates of switching devices
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`Tr4 … in, before, or after application of a gate off pulse … to the switching devices
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`Tr3” (emphasis added)). According to Kuribayashi, an “EL color display” using such
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`a pixel circuit configuration achieves a “long life” span, including “display stability
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`in long-term use.” Id., 12:1–20.
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`Sekiya
`B.
`U.S. Patent No. 6,583,775 (Ex. 1004, “Sekiya”) is a U.S. patent filed June 15,
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`2000, and issued June 24, 2003, and is prior art under Section 102(e). Sekiya was of
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`record during prosecution, but was not cited or discussed by the Examiner.
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`Sekiya discloses an active matrix OLED display in which each pixel has a
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`pixel circuit. Ex. 1004 (“Sekiya”), Abstract, 1:5–40. In Figure 2, Sekiya shows a
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`display having two separate gate driver circuits—one on the left, for controlling the
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`“scanning lines” X, and another on the right, for controlling the “stopping control
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`lines” Z:
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`Sekiya further teaches a pixel circuit that includes a “control means” to
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`“extinguish” (i.e., cut off) current from the light-emitting element, within one period
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`of a scanning cycle after the brightness information is written to the pixel. Id.,
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`Abstract, 6:24–63. As shown in Figure 5, the “control means” is a thin-film transistor
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`(TFT3) connected in series with the light-emitting element:
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`Id., 13:63–14:18; Fig. 5.
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`The gate G of TFT3 is controlled by stopping control line Z, which is parallel
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`to a scanning control line X. Id. The pixel circuit also includes (1) thin-film transistor
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`TFT1, controlled by scanning control line X connected to the gate G of TFT1, which
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`writes brightness information into holding capacitor Cs; and (2) thin-film transistor
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`TFT2, which controls the amount of current flowing to the OLED. See id., 10:60–
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`11:39 & Figs. 1, 5.
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`As shown in Figure 2, TFT1 is controlled by scanning line drive circuit 21 (a
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`first gate driver circuit), via scanning line X associated with each pixel row, whereas
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`TFT3 is controlled by stopping control line drive circuit 23 (a second, separate gate
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`driver circuit), via stopping control line Z associated with each pixel row. Id., 11:40–
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`62 & Figs. 2, 5. Sekiya further discloses a source driver circuit (data line driver
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`circuit) connected to source signal lines (vertical lines Y).
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`C. Takahara
`Japanese Laid-Open Patent Application No. 2001-210122A (Ex. 1005,
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`Certified Translation, “Takahara”3) is a foreign patent application by one of the ’992
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`patent’s inventors, which was published on August 3, 2001, and is prior art under
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`Sections 102(a) and (b). Takahara was not cited or considered by the Examiner
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`during prosecution.
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`Takahara is broadly directed to pixel circuit configurations and driving
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`techniques for display devices, in order to achieve improved video quality and other
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`benefits. Takahara, [0001]–[0002]. The reference teaches that its drive method “is
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`not only applicable to liquid crystal display panels, but can also be applied to active
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`matrix type EL display panels.” Id., [0404], [0754]–[0758].
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`In one embodiment, Takahara discloses a pixel matrix in which the gate lines
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`for multiple pixel rows are connected together by a common control line. Ex. 1028,
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`¶ 93. This is illustrated in Figure 68:
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`3 The original (untranslated) reference is Exhibit 1015.
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`Takahara further discloses circuitry for “pre-charging” the source signal lines.
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`Takahara, [0522]–[0523]. As explained in the accompanying expert declaration by
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`Dr. Miltiadis Hatalis, precharging was a commonly used technique for reducing
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`delays caused by parasitic capacitance and resistance along source signal lines of an
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`EL display. Ex. 1028, ¶ 46, 218. Figure 68 of Takahara shows a source driver 102
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`including a “GONB terminal … used for pre-charging.” Takahara, [0523]. “[B]y
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`operating the GONB terminal, the video signal applied to the SIG terminal can be
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`applied to all source signal lines 228.” Id.
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`VIII. Unpatentability Analysis
`A. Ground I: Claims 1, 2, 4, 7, 10, 11, and 15 Are Unpatentable Under
`35 U.S.C. § 103 Based on Kuribayashi in View of Sekiya
`Claims 1, 2, 4, 7, 10, 11, and 15 are obvious based on Kuribayashi in view of
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`Sekiya. Kuribayashi expressly discloses an EL display apparatus that meets all of
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`the limitations of independent Claims 1 and 10, apart from the requirement of “first”
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`and “second” gate driver circuits. While Kuribayashi does not describe the means
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`Petition for Inter Partes Review of U.S. Pat. No. 10,198,992
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`for controlling its switch transistors in detail, a skilled artisan would have been
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`motivated to use multiple (“first” and “second”) gate driver circuits, as disclosed in
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`Sekiya, as this would be have been the most straightforward way to achieve
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`Kuribayashi’s teachings of flexibly turning the multiple switch transistors on and off
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`at different points of time.
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`1.
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`Claim 1
`Element 1[preamble]: “An electroluminescent (EL)
`a)
`display apparatus, comprising:”
`To the extent the preamble is limiting, it is disclosed by Kuribayashi.
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`Kuribayashi teaches an “invention [that] relates … to … an apparatus using organic
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`electroluminescence members suitable for full-color display of large screen.”
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`Kuribayashi, 1:8–15.
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`Element 1[a]: “a display screen including:”
`b)
`Kuribayashi discloses this element, explaining that its “apparatus [is] suitable
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`for full-color display of large screen.” Kuribayashi, 1:8–15.
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`Element 1[b]: