(12) United States Patent
`Sanford et al.
`
`(54) LOW-POWER ORGANIC LIGHT EMITTING
`DIODE PIXEL CIRCUIT
`
`(75)
`
`Inventors: James Lawrence Sanford, Hopewell
`Junction, NY (US); Eugene S. Schlig,
`Somers, NY (US)
`
`(73) Assignee: International Business Machines
`Corporation, Armonk, NY (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 09/754,489
`
`(22) Filed:
`
`Jan. 4,2001
`
`(65)
`
`Prior Publication Data
`
`US 2002/0084463 Al Jul. 4, 2002
`
`Int. Cl.7 .................................................. GllC 8/00
`(51)
`(52) U.S. Cl. .................... 365/230.05; 365/154; 257/59;
`257/88; 257/93; 257/82
`(58) Field of Search .............................. 257/59, 88, 93;
`345/76, 82; 315/169.3, 169.1
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,151,632 A * 9/1992 Troxell .................... 315/169.1
`5,353,251 A * 10/1994 Uratani et al. .............. 365/154
`5,471,225 A * 11/1995 Parks ......................... 345/205
`5,682,174 A * 10/1997 Chiu .......................... 345/211
`5,689,471 A * 11/1997 Voss et al. .................. 365/156
`5,712,652 A * 1/1998 Sato et al.
`.................. 345/204
`5,723,950 A * 3/1998 Wei et al. ................ 315/169.3
`5,903,246 A
`5/1999 Dingwall ..................... 345/82
`5,952,789 A
`9/1999 Stewart et al. ........... 315/169.4
`6,023,259 A
`2/2000 Howard et al. ............... 345/76
`6,072,517 A * 6/2000 Fork et al. .................. 347/237
`6,229,508 Bl * 5/2001 Kane ........................... 345/82
`6,310,600 Bl * 10/2001 Koyama et al.
`............ 345/103
`6,339,417 Bl * 1/2002 Quanrud ...................... 345/55
`
`I 1111111111111111 11111 lllll 111111111111111 111111111111111 IIIIII IIII IIII IIII
`
`US006580657B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,580,657 B2
`Jun.17,2003
`
`6,351,077 Bl * 2/2002 Koyama .................. 315/169.3
`6,459,611 B2 * 10/2002 Rimondi ..................... 365/156
`2002/0030647 Al * 3/2002 Hack et al. ................... 345/82
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`WO
`WO
`
`1 005 013 Al
`WO 99/38148
`WO 99/42983
`
`5/2000
`7/1999
`8/1999
`
`OTHER PUBLICATIONS
`
`"FA 16.5: A 16Mb CMOS SRAM with a 2.3µ 2 Single-Bit(cid:173)
`Line Memory Cell," Sasaki et al, pp. 250-251, 1993 IEEE
`Internaitonal Solid-State Circuits Conference.
`(Month
`unknown).
`"Low-Power SRAM Circuit Design," Martin Margala, 1999
`IEEE, pp. 115-122. (Aug.).
`"FA 16.6: A Single Bitline Cross-Point Cell Activation
`(SCPA) Architecture for Ultra Low Power SRAMs," Ukita
`et al., 1993 IEE Internaitonal Solid-State Circuits Confer(cid:173)
`ence, pp. 252-253.
`"Active Matrix Molecular OLED Microdisplays," Olivier
`Prache, 14 pages, date unknown.
`
`(List continued on next page.)
`
`Primary Examiner-David Nelms
`Assistant Examiner-Tu-Tu Ho
`(74) Attorney, Agent, or Firm----Ohlandt, Greeley, Ruggiero
`& Perle, L.L.P.; Robert M. Trepp
`
`(57)
`
`ABSTRACT
`
`A pixel circuit comprises an organic light emitting diode
`(OLED), and a static memory for storing data that represents
`an operational state of the OLED. In alternative
`embodiments, a pixel circuit may include a complementary
`metal oxide semiconductor (CMOS) circuit for controlling
`the OLED, a protection circuit for protecting the CMOS
`circuit from an over-voltage condition, and a current source
`with a field effect transistor (FET) having a static gate to
`source voltage that is greater than a threshold voltage of the
`FET.
`
`26 Claims, 8 Drawing Sheets
`
`V1
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`

`US 6,580,657 B2
`Page 2
`
`OIBER PUBLICATIONS
`
`"OL12C10M-Preliminary Data Sheet," eMagin OLED
`Microdisplay, 2 pages, date unknown.
`"Current-Writing Active-Matrix Circuit for Organic Light(cid:173)
`Emitting Diode Display Using a-Si:H Thin-Film-Transis(cid:173)
`tors," Reiji Hattori, IEICE Trans. Elelctron., vol. E83-C,
`No. 5, May 2000.
`"Polysilicon VGA Active Matrix OLED Displays-Tech(cid:173)
`nology and Performace," Stewart et al., IEDM 1998, pp.
`871-874. (Sep.).
`"VGA Active Matrix OLED Displays having the single
`polysilicon TFT Pixel Structure," Hatalis et al., Proceedings
`of SPIE, v. 3636, Jan. 27-29, 1999, pp. 22-31.
`"Sony Develops World's Largest Full Color Organic EL
`Display," Sony News Press Release, Feb. 7, 2001, three
`pages.
`
`"36.1: 6-Bit Digital VGA OLED," Mizukami et al., SID 00
`Digest, pp. 912-915. (? 2000).
`"36.4L: Late-News Paper: 4.0-in. TFT-OLED Displays
`and a Novel Digital Driving Method," Inukai et al., SID 00
`Digest, pp. 924-927. (? 2000).
`"4.2: Design of an Improved Pixel for a Polysilison Active(cid:173)
`Matrix Organic LED Display," Dawson et al., SID 98
`Digest, pp. 11-14.
`"31.3: A Poly-Si Active-Matrix OLED Display with Inte(cid:173)
`grated Drivers," Dawson et al., SID 99 Digest, pp. 438-441.
`(Months unknown).
`Sasaki et al., "A 16Mb CMOS SRAM with a 2.3µm 2 Sin(cid:173)
`gle-Bit-Line Memory Cell", IEEE International Solid-State
`Circuits Conference (1993), p. 250-251.
`
`* cited by examiner
`
`SAMSUNG EX. 1017 - 2/17
`
`

`

`U.S. Patent
`
`Jun. 17, 2003
`
`Sheet 1 of 8
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`us 6,580,657 B2
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`SAMSUNG EX. 1017 - 3/17
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`

`

`U.S. Patent
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`Jun.17,2003
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`Sheet 3 of 8
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`US 6,580,657 B2
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`U.S. Patent
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`Jun.17,2003
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`Sheet 4 of 8
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`US 6,580,657 B2
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`U.S. Patent
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`Jun.17,2003
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`Sheet 5 of 8
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`US 6,580,657 B2
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`U.S. Patent
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`Jun.17,2003
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`U.S. Patent
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`Jun.17,2003
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`US 6,580,657 B2
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`

`US 6,580,657 B2
`
`1
`LOW-POWER ORGANIC LIGHT EMITTING
`DIODE PIXEL CIRCUIT
`
`FIELD OF THE INVENTION
`
`This invention relates generally to a pixel circuit, and,
`more particularly, to a low-power organic light emitting
`diode (OLED) pixel circuit utilizing complementary metal
`oxide semiconductor (CMOS) technology.
`
`BACKGROUND OF THE INVENTION
`
`5
`
`2
`Accordingly, CMOS technology is not ordinarily capable of
`driving an OLED. Furthermore, a CMOS device in an
`OLED pixel circuit is particularly susceptible to damage
`from the voltage in excess of 4 volts.
`A traditional manner of changing a displayed image is for
`a processor to update the memory of a display controller that
`periodically and individually addresses each of the pixels of
`the display, and turn them "on" (ON) and "off" (OFF) as
`required. If the display included a large number of pixels, for
`10 example one hundred thousand, one million, or more, this
`operation would consume a significant quantity of power
`and could burden the processor.
`An additional problem when incorporating a plurality of
`pixel circuits into a display is that of physically distributing
`15 the collective elements of the display. That is, the display is
`a finite area within which the pixels and their accompanying
`circuitry are confined, yet a constant pitch between pixels
`must be maintained in order to provide a uniform image.
`Because of the aforementioned disadvantages, OLED
`displays have not been as readily adopted by designers as
`have many other conventional display technologies. The use
`of dynamic RAM and its corresponding circuitry required
`for refreshing an image, and issues relating to power dissi-
`25 pation are an obstacle to an employment of OLEDs in
`battery operated devices, and in small displays such as those
`used for hand-held devices or watches. The OLED operating
`voltages are an obstacle to the use of CMOS circuitry in an
`OLED pixel circuit. The regular addressing of every pixel in
`30 an array is an obstacle to the employment of OLEDs in large
`displays. The maintenance of a constant pitch between
`pixels is an important consideration in any display.
`
`20
`
`An OLED pixel may utilize any of a variety of organic
`materials that emit light when an electric current is applied
`thereto. An OLED display comprises a plurality of OLED
`pixels organized into an array.
`Illumination of an OLED pixel is controlled by a pixel
`circuit that may include either a constant current source or
`a constant voltage source. It is generally recognized that the
`constant current source provides a greater uniformity of
`luminance among the pixels of the array. This is because the
`dependence of luminance upon current tends to be uniform
`while the voltage across the OLEDs at a given current in the
`various pixels tends to be less uniform. U.S. Pat. No.
`6,023,259 to Howard et al. describes a current driver that
`provides a passive matrix drive current to an OLED. For
`typical display brightness, passive matrix drive operation
`results in lower OLED power efficiency and, in order to
`avoid flicker, requires a refresh rate greater than or equal to
`60 Hz.
`In an active matrix display, a provision is generally made
`for storage of the state of a pixel within its respective pixel
`circuit. This is commonly achieved by incorporating the
`equivalent of a dynamic RAM cell in each pixel circuit, in
`which the state is stored as a voltage across a capacitor. A 35
`disadvantage of such an arrangement is that the voltage
`quickly bleeds off the capacitors, and consequently any
`image represented on the display must be regularly
`refreshed. This act of refreshing the image consumes a
`significant quantity of power. It is therefore desirable to find 40
`an alternative to the conventional use of dynamic RAMs.
`Control of the luminance of an "on" pixel is commonly
`achieved by controlling a magnitude of an analog voltage
`that determines the voltage or current applied to the pixel.
`Analog control circuits are another source of excessive
`power dissipation. It is therefore desirable to find an alter(cid:173)
`native to the conventional use of analog control circuitry.
`The OLED display is constructed of thin layers of organic
`material in which individual OLED pixels are subject to an 50
`occasional short circuit between an anode of the OLED and
`a counter-electrode of the OLED. Such a short can cause
`excess current to flow in the circuit, excess voltage across
`the pixel circuit and excess power dissipation. Good pixels
`neighboring a shorted pixel may be destroyed by heat from
`the shorted pixel and the excess current may alter power
`supply voltages.
`During operation of the OLED display, the layers of
`organic material tend to trap charge, causing increases in the
`voltage drop across the OLED, which can cause a non(cid:173)
`uniformity ofluminance and a burned-in image. The trapped
`charge may be removed by reverse-biasing the OLED.
`The OLED itself typically requires a voltage on the order
`of +/-6 volts to develop an adequate luminance when turned
`ON and to remove trapped charge when reverse-biased. 65
`Conventional CMOS integrated circuit technology uses
`transistors that operate with a voltage of less than 4 volts.
`
`OBJECTS OF THE INVENTION
`
`It is an object of this invention to provide an improved
`OLED display that overcomes the foregoing and other
`problems.
`It is a further object of the present invention to provide an
`improved OLED pixel circuit that dissipates low power, and
`is therefore suitable for use in a small battery powered
`device.
`It is another object of the present invention to provide
`such an OLED pixel circuit in which a state of the pixel is
`retained in a static storage cell or memory while maintaining
`45 high circuit density and low power.
`It is another object of the present invention to provide an
`OLED pixel circuit that utilizes CMOS technology for
`controlling an OLED.
`It is another object of the present invention to provide an
`OLED pixel circuit that confines an effect of a short(cid:173)
`circuited pixel so that non-shorted pixels continue operating
`in a normal manner.
`It is yet another object of the present invention to provide
`55 an OLED pixel circuit that is capable of handling a large
`voltage variation across the OLED between normal and
`reverse-biased states without subjecting the OLED pixel
`circuit transistors to an excess voltage.
`It is a further object of the present invention to provide an
`60 OLED pixel circuit that is suitable for use in a large display
`format.
`
`SUMMARY OF THE INVENTION
`In accordance with a first embodiment of this invention,
`a pixel circuit includes an organic light emitting diode
`(OLED), and a static memory for storing data that represents
`an operational state of the OLED.
`
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`

`US 6,580,657 B2
`
`3
`In accordance with a second embodiment of this
`invention, a pixel circuit includes an OLED, a complemen(cid:173)
`tary metal oxide semiconductor (CMOS) circuit for control(cid:173)
`ling the OLED, and a protection circuit for protecting the
`CMOS circuit from over-voltage conditions.
`In accordance with a third embodiment of this invention,
`a pixel circuit includes an OLED, and a CMOS circuit for
`controlling the OLED. The CMOS circuit contains a current
`source constructed using a field effect transistor (FET)
`having a static gate to source voltage that is greater than a 10
`threshold voltage of the FET.
`In accordance with a fourth embodiment of this invention
`a display includes an array of pixel circuits. Each of the pixel
`circuits contains an OLED, and a static memory for storing
`data that represents an operational state of the OLED.
`
`15
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`4
`105 are arranged in two dimensions, forming a planar
`display. The side view shown in FIG. lB depicts the vertical
`structure of array 100 on, by example, a silicon chip 101
`upon which anode electrodes 105 are patterned. Disposed
`5 below anode electrodes 105 may be a light-blocking layer
`(not shown) to prevent OLED light or external light from
`reaching underlying circuitry. An organic layer 102 and a
`transparent cathode counter-electrode layer 103 are disposed
`above anode electrodes 105.
`In some OLED displays with a transparent anode, an
`observer may view the OLED through its anode electrode
`105, but the preferred embodiment involves viewing the
`OLED through its cathode counter-electrode layer 103. This
`is because the silicon substrate 101 is not transparent, but is
`opaque.
`A protective cover glass 104 is attached to the silicon chip
`101 over cathode electrode layer 103 to provide environ(cid:173)
`mental protection for the OLED structure. A suitable getter
`for moisture absorption may also be positioned within a
`cover-glass-to-silicon seal, but outside the boundary of array
`20 100.
`In an active matrix scheme of addressing the display, data
`that defines a state of the pixels, that is, whether the pixel is
`ON, i.e., luminous, or OFF, i.e., dark, may be written to, and
`stored, in either a dynamic or static memory structure. The
`25 stored data may also be read out from the memory structure,
`if it is so configured, for example, for purposes of electrical
`testing. In a dynamic memory array, data is stored on a
`capacitor and must be refreshed periodically, an operation
`that dissipates power. In a static memory, data is stored in an
`30 electronic latch comprised of CMOS circuits, and virtually
`no power is dissipated to hold the data. The OLED display
`apparatus in accordance with the presently preferred
`embodiments of this invention uses static memory for low
`power dissipation.
`In an active matrix display in accordance with these
`teachings the organic material is sandwiched between pixel
`electrodes of the underlying circuit and a counter-electrode.
`The pixel electrode is typically the anode of the light
`emitting diode and the counter-electrode is typically the
`40 cathode. The display is formed as a rectangular array of
`pixels that are turned ON or OFF as the displayed image
`requires. Each pixel has a pixel anode electrode and pixel
`circuits that control the electrical state of the anode relative
`to the counter-electrode.
`The pixel circuits may be constructed using thin-films
`formed on an insulating substrate, or they may be con(cid:173)
`structed using integrated circuit technology, preferably
`silicon-based. In general, the pixel circuit can be fabricated
`with (1) any suitable material, such as, for example, crys-
`50 talline silicon, amorphous silicon, polysilicon, micro crys(cid:173)
`talline silicon, an organic semiconductor or a polymer
`semiconductor, and (2) disposed, for example, on a substrate
`of silicon, glass, plastic, ceramic, or sapphire (AL2 O3 ). The
`thin-film circuits on an insulating (dielectric) substrate have
`55 the advantages of lower cost and an ability to be fabricated
`into large displays. In general, the use of crystalline silicon
`devices is confined to small area arrays, but the circuits have
`higher performance and higher fabrication density than the
`thin-film circuits. The OLED circuitry in accordance with
`60 these teachings is suitable for being implemented using a
`variety of fabrication techniques, but the crystalline silicon
`technology is the preferred embodiment. Since silicon sub(cid:173)
`strates are opaque to visible light, light emission is prefer(cid:173)
`ably through the counter-electrode, which is preferably
`65 formed as a continuous sheet of transparent conductive
`material such as indium tin oxide, e.g., see counter-electrode
`layer 103.
`
`The above set forth and other features of the invention are
`made more apparent in the ensuing Detailed Description of
`the Invention when read in conjunction with the attached
`Drawings, wherein:
`FIG. lA is an illustration of a top view of an array of
`OLED structures, in accordance with the teachings of this
`invention;
`FIG. lB is a side view of the array of FIG. lA taken
`through line lB-lB;
`FIG. 2 is a block diagram of an OLED pixel word array
`structure, each word being composed of 16 pixels;
`FIG. 3 is a block diagram of an embodiment of an OLED
`pixel word circuit;
`FIG. 4 is schematic of logic circuitry in a word select
`circuit, in accordance with these teachings;
`FIG. 5 is a simplified schematic of an embodiment of an 35
`OLED pixel circuit;
`FIG. 6 is a more detailed schematic of an OLED pixel
`circuit;
`FIG. 7 is a block diagram of display and control register
`clear connections for driving an OLED array; and
`FIG. 8 is a block diagram of an OLED pixel word
`structure showing a physical relationship of pixel circuits
`and a word select circuit to respective anodes of OLED
`pixels.
`
`45
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The teachings in accordance with presently preferred
`embodiments of this invention relate to active matrix OLED
`displays. Such displays may be configured as micro-displays
`and incorporated into small, battery-powered devices such
`as electronic wristwatches. This particular field of use and
`application should not, however, be construed in any manner
`as a limitation upon the practice of the teachings of this
`invention.
`FIG. lAis an illustration of a top view of an array 100 of
`OLED structures, e.g., picture elements (pixels) or light
`emitting elements, and FIG. lB is a side view of array 100
`taken through line lB-lB of FIG. lA. Each OLED struc(cid:173)
`ture of array 100 is constructed to have a pixel circuit that
`includes an OLED and a static memory for storing data that
`represents an operational state of the OLED.
`Array 100 may be generally considered to be a regular
`nxm array of pixels, where n may or may not be equal to m.
`Array 100 includes a plurality of OLED structures, each
`of which has an anode electrode 105. The anode electrodes
`
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`

`US 6,580,657 B2
`
`5
`In the description that follows, the term "array" is used to
`refer to an array of pixels as well as to an array of anodes.
`FIG. 2 is a block diagram of an OLED array 200 com(cid:173)
`prising a plurality of data storage devices or units, also
`referred to herein as word structures 205. Each word struc(cid:173)
`ture 205 is a static random access memory (SRAM) of, for
`example, 16 bits that correspond to sixteen pixels along a
`row of array 200. In this embodiment data is written into,
`and read out of, the array 16 bits at a time.
`The inputs to each word structure 205 are a column block
`select 204, bit lines 203, a word line read 202 and a word line
`write 201. Data is written into word structure 205 from bit
`lines 203 when word line write 201 and column block select
`204 lines are both activated, for example by switching them
`to a high state. Data is read from word structure 205 onto bit
`lines 203 when word line read 202 and column block select 15
`204 are both activated. No operation is defined for the case
`where both word line read 202 and word line write 201 lines
`are active.
`Note that each column block select 204 relates to a
`column of array 200, whereas each word line write 201 and
`word line read 202 relates to a row of array 200. By using
`an appropriate combination of column block selects 204,
`word line writes 201 and word line reads 202, data can be
`written to, or read from, any of word structures 205 in array
`200.
`The total number of bit lines 203 corresponds to the
`number of columns of pixels in array 200. Since each word
`structure 205 represents 16 pixels, the number of column
`block selects 204 corresponds to the number of columns of
`pixels in array 200 divided by 16.
`Conventional SRAMs typically use complimentary bit
`lines, i.e., two lines per bit. The present invention uses a
`single bit line per pixel column, thus reducing power dissi(cid:173)
`pation as compared to the conventional design. For example,
`in FIG. 2, a set of bit lines 203 representing data bits 1-16 35
`is configured as 16 single lines.
`From a system point of view, reading data from the
`memory cells of a display is less efficient than reading from
`a system memory external to the display because reading
`from the display typically has higher power dissipation and 40
`lower speed. However, reading data from the memory cells
`of the display is useful when electrically testing the display.
`Nonetheless, an emphasis is placed on writing to the display
`rather than reading from the display. Accordingly, conven(cid:173)
`tional SRAM design techniques such as pulsed word line 45
`addressing, bit line equalization and bit line sense circuitry
`are not required.
`FIG. 3 is a block diagram of an OLED pixel word
`structure 205. Word structure 205 includes a word select
`circuit 300 and sixteen pixel circuits 400. The inputs to word
`select circuit 300 are column block select 204, word line
`read 202 and word line write 201. The outputs of word select
`circuit 300 are word read 404 and word write 405. The
`inputs to pixel circuit 400 are a single bit line 203, word read
`404 and word write 405. Word read 404 and word write 405 55
`are the local word-selected extensions of word line read 202
`and word line write 201, respectively. Word select circuit
`300 is shown to the left of pixel circuits 400 by way of
`example.
`FIG. 4 shows the circuit details of some of the logic in
`word select circuit 300. Word select circuit 300 includes two
`AND gates 500 and 501.
`The inputs to AND gate 500 are column block select 204
`and word line read 202. Word read 404 is the output of AND
`gate 500. When both column block select 204 and word line
`read 202 are high, i.e., active, word read 404 goes high, i.e.,
`active.
`
`6
`The inputs to AND gate 501 are column block select 204
`and word line write 201. Word write 405 is the output of
`AND gate 501. When both column block select 204 and
`word line write 201 are high, i.e., active, word write 405
`5 goes high, i.e., active.
`FIG. 5 is a simplified schematic of the major functional
`elements of pixel circuit 400 in array 200. Pixel circuit 400
`includes an SRAM cell 10, a current source 20 connected to
`a voltage power supply Vl, three switches 30, 40 and 50, a
`10 grounded gate p-type metal oxide semiconductor (PMOS)
`transistor 60 with its n-well connected to its source 64, i.e.,
`a floating well, and an OLED 70 connected to a power
`supply voltage V2. During normal operation Vl is a positive
`voltage and V2 is a negative voltage.
`The inputs to SRAM cell 10 are a single bit line 203, word
`read 404, and word write 405. Note that bit line 203 is a
`single bit line for inputting a signal that represents data to,
`and outputting a signal that represents the data from, SRAM
`cell 10. Word write 405 enables writing of data into SRAM
`20 cell 10 and word read 404 enables reading of data from
`SRAM cell 10. The outputs of SRAM cell 10 are bit line
`203, and a control line 8. Note that bit line 203 is both an
`input and an output of SRAM cell 10. Control line 8 is for
`controlling switch 40. With high states on both bit line 203
`25 and word write 405, a high state is written into SRAM cell
`10. When SRAM cell 10 stores a high state, control line 8
`closes switch 40. When SRAM cell 10 stores a low state,
`control line 8 opens switch 40.
`Vl provides power for current source 20. Current source
`30 20 produces an output current corresponding to a predeter(cid:173)
`mined maximum brightness level of OLED 70.
`It is desirable to control the luminance of OLED 70 by
`controlling the average current through OLED 70. A duty
`factor NOT 6 is a pulse width modulated signal that is
`provided as an input common to all pixels in array 200. A
`low state on duty factor NOT 6 closes switch 30. A high state
`on the duty factor NOT 6 opens switch 30. The duty factor
`NOT 6 controls the average current through OLED 70 to set
`its luminance to a level of less than the maximum brightness.
`A reverse bias 7 is a signal that is provided as an input
`common to all pixels in array 200. A high state on reverse
`bias 7 closes switch 50. A low state on reverse bias 7 opens
`switch 50.
`When switches 30 and 40 are closed and switch 50 is
`open, current flows from current source 20, through switches
`30 and 40, and into source 64 of PMOS transistor 60. PMOS
`transistor 60 operates as a cascade stage to provide a greater
`voltage compliance range for current source 20, as is known
`50 in the art. Current out the drain 62 of PMOS transistor 60
`flows into OLED 70 turning OLED 70 ON. Voltage com(cid:173)
`pliance range is the range of output voltages over which the
`output current is essentially constant. A cascade stage is a
`common gate amplifier stage that improves the voltage
`compliance range by providing voltage gain.
`When current is flowing through PMOS transistor 60, it
`has a relatively low voltage, e.g., approximately 10
`millivolts, across its drain 62 and source 64. With current
`flowing, the voltage on drain 62 can be several volts above
`60 or below ground while the voltage on source 64 is at a
`minimum of one threshold voltage above ground and always
`higher than the voltage on its drain 62. A threshold voltage
`is the minimum source to gate voltage required to maintain
`the transistor in the normal conducting region of operation.
`65 When no current is flowing into source 64 of PMOS
`transistor 60, the voltage on source 64 does not go below
`ground.
`
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`

`US 6,580,657 B2
`
`8
`written into SRAM cell 10, but it can be re-inverted in a bit
`line read circuit (not shown). Preferably, inverter 14 is
`included because it isolates pixel circuit 400 from noise on
`bit line 203 and from capacitance loading by bit line 203
`5 during the read operation.
`A PMOS transistor 20A serves as a current source 20
`(FIG. 5). A VREF 21 is connected to the gate of PMOS
`transistor 20A, and also to a similarly situated PMOS
`transistor in all of the other pixel circuits of array 200.
`The previously mentioned light-blocking layer may, for
`instance, be used to distribute the +3V power of Vl. The
`light-blocking layer, a conducting layer, is distributed and
`connected throughout the array providing a low-resistance
`path for Vl power distribution. In this manner, the light-
`15 blocking layer performs two functions, i.e., light-blocking
`and power distribution.
`PMOS transistor 20Ais a field effect transistor (FET) with
`a channel width