(12) United States Patent
`Okuda
`
`I 1111111111111111 11111 lllll 111111111111111 111111111111111 1111111111 11111111
`US006380689Bl
`US 6,380,689 Bl
`Apr. 30, 2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) DRIVING APPARATUS FOR ACTIVE
`MATRIX TYPE LUMINESCENT PANEL
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`7-111341
`
`4/1995
`
`........... H0lL/33/00
`
`(75)
`
`Inventor: Yoshiyuki Okuda, Tsurugashima (JP)
`
`* cited by examiner
`
`(73) Assignee: Pioneer Corporation, Tokyo (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 09/679,814
`
`(22) Filed:
`
`Oct. 5, 2000
`
`(30)
`
`Foreign Application Priority Data
`
`Oct. 6, 1999
`
`(JP) ........................................... 11-285203
`
`Int. Cl.7 .................................................. G09G 3/10
`(51)
`(52) U.S. Cl. ................................ 315/169.3; 315/169.1;
`315/169.2; 345/60; 345/76; 345/77
`(58) Field of Search ........................... 315/169.1, 169.2,
`315/169.3; 345/76, 60
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,424,612 A * 6/1995 Kim ........................ 315/169.3
`5,670,974 A * 9/1997 Ohba et al. .............. 315/169.4
`6,100,637 A * 8/2000 Kishino et al.
`.......... 315/169.3
`
`Primary Examiner-Don Wong
`Assistant Examiner-Jimmy T. Vu
`(74) Attorney, Agent, or Firm-Morgan, Lewis & Bockius
`
`(57)
`
`ABSTRACT
`
`A driving apparatus for an active matrix type luminescent
`panel, in which a reverse bias voltage can be applied to each
`EL device in the luminescent panel effectively. An address
`period and an emission period are repeatedly set on each of
`a plurality of capacitive light emitting devices in accordance
`with synchronizing timing in input image data. In an address
`period, a driving device corresponding to at least a device to
`be light-emitted of the plurality of capacitive light emitting
`devices is designated in accordance with the input image
`data. The designated driving device is turned on in the
`emission period subsequent to the address period, so that an
`emission voltage in forward polarity is applied to the device
`to be light-emitted device through the corresponding driving
`device in the emission period. In the address period, a bias
`voltage having polarity reverse to the forward polarity is
`applied to at least the device to be light-emitted.
`
`12 Claims, 15 Drawing Sheets
`
`2
`
`DRIVE CONTROL
`CIRCUIT
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`ADDRESS
`SCAN
`DRIVER
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`LUMINESCENT
`PANEL
`
`10
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`Am
`
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`

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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 1 of 15
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`US 6,380,689 Bl
`
`FIG. 1
`
`----c
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 2 of 15
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`US 6,380,689 Bl
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 3 of 15
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`US 6,380,689 Bl
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`FIG. 3
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 5 of 15
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`US 6,380,689 Bl
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 6 of 15
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`U.S. Patent
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`Apr. 30, 2002
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 8 of 15
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`US 6,380,689 Bl
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`U.S. Patent
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 10 of 15
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`US 6,380,689 Bl
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 11 of 15
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`US 6,380,689 Bl
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 12 of 15
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 13 of 15
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`US 6,380,689 Bl
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`FIG. 13
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 14 of 15
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`US 6,380,689 Bl
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`FIG. 14
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`U.S. Patent
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`Apr. 30, 2002
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`Sheet 15 of 15
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`US 6,380,689 Bl
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`FIG. 15
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`US 6,380,689 Bl
`
`1
`DRIVING APPARATUS FOR ACTIVE
`MATRIX TYPE LUMINESCENT PANEL
`
`BACKGROUND OF THE INVENTION
`
`10
`
`2
`a plurality of capacitive light emitting devices arranged in a
`matrix, each having polarity, and driving devices for driving
`the plurality of capacitive light emitting devices
`individually, the driving apparatus comprising: setting
`5 means for setting an address period and an emission period
`repeatedly on each of the plurality of capacitive light emit(cid:173)
`ting devices in accordance with synchronizing timing in
`input image data; ON holding means for designating a
`driving device of the driving devices corresponding to at
`least a device to be light-emitted of the plurality of capaci(cid:173)
`tive light emitting devices in accordance with the input
`image data in the address period so that the designated
`driving device is turned on in the emission period subse(cid:173)
`quent to the address period; and voltage applying means for
`applying an emission voltage, in forward polarity, to the
`15 device to be light-emitted through the designated driving
`device in the emission period, wherein the voltage applying
`means applies a bias voltage, in polarity reverse to the
`forward polarity, to at least the device to be light-emitted, in
`the address period.
`A driving apparatus for an active matrix type luminescent
`panel according to the present invention is a driving appa(cid:173)
`ratus for an active matrix type luminescent panel including
`a plurality of capacitive light emitting devices arranged in a
`matrix, each having polarity, and driving devices for driving
`25 the plurality of capacitive light emitting devices
`individually, the driving apparatus comprising: setting
`means for setting an address period and an emission period
`repeatedly on each of the plurality of capacitive light emit(cid:173)
`ting devices in accordance with synchronizing timing in
`30 input image data; designating means for accepting and
`holding a brightness voltage corresponding to a brightness
`level in the input image data immediately before the address
`period, and designating, in the address period, an active
`device corresponding to at least a device to be light-emitted
`of the plurality of capacitive light emitting devices in
`accordance with the brightness voltage; holding means for
`turning the designated active device on or active in accor(cid:173)
`dance with the brightness voltage in the emission period
`subsequent to the address period; and voltage applying
`means for applying an emission voltage, in forward polarity,
`to the device to be light-emitted through the designated
`active device in the emission period, wherein the voltage
`applying means applies a bias voltage, in polarity reverse to
`the forward polarity, to at least the device to be light-emitted
`of the plurality of capacitive light emitting devices in the
`address period.
`
`1. Field of the Invention
`The invention relates to a driving apparatus for an active
`matrix type luminescent panel which uses capacitive light
`emitting devices such as organic electroluminescence
`devices.
`2. Description of the Related Background Art
`In recent years, with the trend of increasing the size of
`display devices, thinner display devices have been required,
`and a variety of thin display devices have been brought into
`practical use. An electroluminescence display comprising a
`plurality of organic electroluminescence elements arranged
`in a matrix has drawn attention as one of the thin display
`devices.
`An organic electroluminescence device (hereinafter, also
`simply referred to as EL device) can be electrically repre- 20
`sented by an equivalent circuit as shown in FIG. 1. As seen
`from the diagram, the device is replaceable with the circuitry
`consisting of a capacitive element C and an element E
`having diode characteristics, coupled to the capacitive ele(cid:173)
`ment in parallel. The EL device is therefore considered as a
`capacitive light emitting device. The EL device, when a
`direct-current emission drive voltage is applied across its
`electrodes, stores a charge into the capacitive element C.
`Subsequently, when a barrier voltage or emission threshold
`voltage specific to this device is exceeded, an electric current
`starts to flow from the electrode ( on the anode side of the
`diode element E) to an organic functional layer which carries
`the light emitting layer, so as to emit light in an intensity
`proportional to this current.
`Such known EL-device luminescent panels include
`simple matrix type luminescent panels and active matrix
`type luminescent panels. A simple matrix type luminescent
`panel has EL devices simply arranged in a matrix. An active
`matrix type luminescent panel has matrix-arranged EL
`devices each of which is added with a driving device
`consisting of transistors. A driving apparatus for an active
`matrix type luminescent panel repeatedly alternates an
`address period and an emission period to drive each EL
`device for light emission. In an address period, to-be(cid:173)
`operated EL devices on the matrix luminescent panel are
`designated. In an emission period, an emission voltage is
`applied to the EL devices designated in the address period.
`It is empirically known that the application of voltage to
`EL devices in a reverse direction not participating in light 50
`emission extends the life of the devices. Nevertheless,
`conventional driving apparatuses for an active matrix type
`luminescent panel, e.g. as described in Japanese Patent
`Laid-Open Publication No.Rei 7-111341, apply nothing but
`a forward voltage to EL devices in an emission period. No 55
`reverse bias voltage is applied to the EL devices in either
`period.
`
`35
`
`40
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a circuit diagram showing an equivalent circuit
`representing an EL device;
`FIG. 2 is a block diagram showing a driving apparatus of
`a line-sequential display system according to the present
`invention;
`FIG. 3 is a diagram showing address periods and emission
`periods within a single subfield in the apparatus of FIG. 2;
`FIG. 4 is a diagram showing the subfield divisions in a
`single field under the line-sequential display system;
`FIG. 5 is a circuit diagram showing an example of a light
`emitting circuit on the luminescent panel of FIG. 2;
`FIG. 6 is a circuit diagram showing another example of a
`light emitting circuit on the luminescent panel of FIG. 2;
`FIG. 7 is a block diagram showing a driving apparatus of
`simultaneous display system according to the present inven(cid:173)
`tion;
`FIG. 8 is a diagram showing an address period and an
`emission period within a single subfield in the apparatus of
`FIG. 7;
`
`SUMMARY OF THE INVENTION
`In view of the foregoing, it is an object of the present 60
`invention to provide a driving apparatus for an active matrix
`type luminescent panel, the driving apparatus being capable
`of applying a reverse bias voltage to each EL device in the
`active matrix type luminescent panel effectively.
`A driving apparatus for an active matrix type luminescent 65
`panel according to the present invention is a driving appa(cid:173)
`ratus for an active matrix type luminescent panel including
`
`SAMSUNG EX. 1010 - 17/24
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`US 6,380,689 Bl
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`3
`FIG. 9 is a diagram showing the subfield divisions in a
`single field under the simultaneous display system;
`FIG. 10 is a circuit diagram showing an example of a light
`emitting circuit on the luminescent panel of FIG. 7;
`FIG. 11 is a circuit diagram showing another example of
`a light emitting circuit on the luminescent panel of FIG. 7;
`FIG. 12 is a block diagram showing a driving apparatus
`which makes brightness adjustments under a current modu(cid:173)
`lation system;
`FIG. 13 is a circuit diagram showing an example of a light
`emitting circuit on the luminescent panel of FIG. 12;
`FIG. 14 is a diagram showing address periods and emis(cid:173)
`sion periods within a single field in the apparatus of FIG. 12;
`and
`FIG. 15 is a circuit diagram showing another example of
`a light emitting circuit on the luminescent panel of FIG. 12.
`
`DETAILED DESCRIPTION OF IBE
`PREFERRED EMBODIMENTS
`
`Hereinafter, preferred embodiments of the present inven(cid:173)
`tion will be described in detail with reference to the accom(cid:173)
`panying drawings.
`FIG. 2 shows a driving apparatus of a line-sequential
`display system using EL devices according to the present
`invention. The driving apparatus comprises an active matrix
`type luminescent panel 10, an AID converter 1, a drive
`control circuit 2, a memory 4, an address scan driver 6, and
`a data driver 7.
`The luminescent panel 10 has a plurality of EL devices
`E1 ,1-Em,n arranged in a matrix at a plurality of intersections
`of address lines (anode lines) A 1-A,,, and data lines (cathode
`lines) B 1-Bn.
`The address scan driver 6 is connected to the address lines
`AcA,,, of the luminescent panel 10. The address scan driver
`6 supplies the individual address lines AcA,,, with one
`potential of an emission potential Ve exceeding an emission
`threshold Vth, a reverse bias potential - Va, and O V. The data
`driver 7 is connected to the data lines B 1-Bn of the lumi(cid:173)
`nescent panel 10, and supplies the individual data lines
`BcBn with either a positive potential VL or O V.
`The AID converter 1 samples an analog image signal
`input thereto in accordance with a clock signal supplied
`from the drive control circuit 2. The signal sampled is
`converted into N-bit pixel data D corresponding to respec(cid:173)
`tive pixels, and supplied to the memory 4.
`The memory 4 sequentially stores the above-mentioned
`pixel data D in accordance with a write signal supplied from
`the drive control circuit 2. When the storage operations for
`one screen (m rows, n columns) of the luminescent panel 10
`are finished, the memory 4 divides pixel data D11 to Dmm of
`one screen for each bit digit in accordance with a read signal
`supplied from the drive control circuit 2. The resultants are
`read by row from the first row to the m-th row, and
`successively supplied to the data driver 7 as drive pixel data
`bit groups DB 1 to DBn.
`The drive control circuit 2 generates the clock signal for
`the AID converter 1 and the write and read signals for the
`memory 4 in accordance with a horizontal synchronizing
`signal and a vertical synchronizing signal contained in the
`input image signal mentioned above.
`Moreover, the drive control circuit 2 divides a single field
`period in the above-mentioned input image signal into eight
`subfields. In each subfield, the drive control circuit 2 sup(cid:173)
`plies both the address scan drive 6 and the data driver 7 with
`
`4
`a timing signal for applying various drive pulses to the
`luminescent panel 10. The field-to-subfield division is made
`for the sake of 256-gradation display. The respective sub(cid:173)
`fields are set at 1, 2, 4, 8, 16, 32, 64, and 128 in relative
`5 brightness ratio so that selective combinations of these
`subfields realize 256 levels. Here, a single field period may
`be divided into any number of subfields other than eight.
`Since the individual subfields involve common
`operations, description will be given on a single subfield
`10 alone. As shown in FIG. 3, address periods in a subfield
`correspond to the respective address lines A 1-A,,, and are in
`turn allocated from the address line A 1 to the address line
`A,,,. From the beginning of the address period for the address
`line A 1 , the respective beginnings of the address periods for
`15 address lines A2-A,,, are in turn delayed by a predetermined
`period toward the address line A,,,. In an address period, the
`address scan driver 6 supplies the address line with the
`reverse bias potential - Va as a scan pulse SP. The end of an
`address period is followed by an emission period, in which
`20 the address scan driver 6 supplies the emission potential Ve
`to the address line. For the individual address lines in one
`subfiels, the address periods have the same length and the
`emission periods also have the same length. In one field,
`however, as subfields position behind, emission periods are
`25 shorter.
`The data driver 7 generates pixel data pulse groups
`DP 1-DP n corresponding to the drive pixel data bit groups
`DB 1-DBn read in succession from the memory 4, respec(cid:173)
`tively. The pixel data pulse groups DPcDPn generated are
`30 successively supplied to the data lines BcBn under their
`address periods. For example, the data driver 7 generates a
`pixel data pulse having a voltage of VL when a data bit in a
`drive pixel data bit group DB has a logic level of "O,"
`generates a pixel data pulse of O V under a logic level of "1,"
`35 and applies the pixel data pulse of O V to the data lines
`B 1-Bn. That is, the data driver 7 applies one row (n pulses)
`of the pixel data pulses to the data lines B 1-Bn as a pixel data
`pulse group DP mentioned above.
`In an emission period, a current flows through only those
`EL devices on the intersections of the "row" to which the
`scan pulse SP is applied and the "columns" to which pixel
`data pulses of VL in voltage are applied, whereby the EL
`devices enter a luminescent state. EL devices subjected to
`45 the scan pulse SP while subjected to 0-V pixel data pulses
`are not applied with any current in the emission period,
`entering a non-luminescent state.
`FIG. 4 shows the respective temporal positions of the first
`through eighth subfields in a field, with regard to the row
`50 direction of the luminescent panel 10 (the direction of the
`address lines A 1 to A,,,). Immediately before the termination
`of each subfield, the address scan driver 6 supplies O V to the
`address lines A 1-A,,, to reset the EL devices.
`FIG. 5 shows a light emitting circuit lOi,j including an EL
`55 device E;J• The EL device Ei,j is arranged on the intersection
`between an address line A 1 of the address lines A 1-A,,, and
`a data line Bj of the data lines BcBn in the luminescent
`panel 10. As well as the EL device E;J, the light emitting
`circuit 10;,j includes a P-ch (P-channel) MOSFET 11, an
`60 N-ch MOSFET 12, and a capacitor 13. The address line A;
`is connected to the anode of the EL device E;✓ and the gate
`of the FET 11. The data line Bj is connected to the source of
`the FET 11. The drain of the FET 11 is connected to the gate
`of the FET 12, and the connecting line therebetween is
`65 grounded through the capacitor 13. The cathode of the EL
`device E;✓ is connected to the source of the FET 12. The
`drain of the FET 12 is grounded.
`
`40
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`US 6,380,689 Bl
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`5
`The address line A; is connected to a switch 6; in the
`address scan driver 6. The switch 6; selectively supplies the
`address line A; with any one potential of the above(cid:173)
`mentioned emission potential Ve, reverse bias potential - Va,
`and 0-V ground potential. The data line Bj is connected to a
`switch 7j in the data driver 7. The switch 7j supplies the data
`line Bj with either the positive potential V L or the 0-V
`ground potential. The switches 6; and 7j are selected in
`accordance with the timing signals from the drive control
`circuit 2.
`In a subfield for the EL device Ei,j to emit light, the switch
`6; supplies the reverse bias potential -Va to the address line
`A; when the row of the address line A; enters an address
`period. That is, the selection of the address line A; is effected
`by supplying an addressing pulse having the negative paten- 15
`tial of - Va. The negative potential - Va is applied to the
`anode of the EL device E;J· Since the cathode of the EL
`device Ei,j is at the ground potential, the EL device Ei,j is
`reverse-biased. During the address period, the data line Bj is
`supplied with the positive potential VL through the switch 7j 20
`so that the FET 11 is turned on to charge the capacitor 13
`with the voltage VL. Here, the terminal voltage of the
`capacitor 13, a positive voltage, is applied to the gate of the
`FET 12.
`When the address period terminates to enter an emission
`period, the switch 6; supplies the emission voltage Ve to the
`address line A;, turning off the FET 11. The FET 12 is turned
`on because the charge voltage of the capacitor 13 is applied
`to its gate. Accordingly, the turning-on of the FET 12
`equalizes the cathode of the EL device E;✓ to the ground
`potential. Since the emission voltage Ve is applied to the EL
`device Ei,j in the forward direction, a current flows to bring
`the EL device E;✓ into the luminescent state.
`When the emission period terminates, the switch 6; sup(cid:173)
`plies the 0-V ground potential to the address line A; so that
`the EL device Ei,j becomes approximately O V across to enter
`a reset period.
`The light emitting circuit 10;✓ performs the same opera(cid:173)
`tions in each of the first through eighth subfields. Moreover,
`each of the light emitting circuits 1011-lOm n in the lumi(cid:173)
`nescent panel 10 other than the light' emitti~g circuit 10;✓
`also performs the same operations as those of the light
`emitting circuit lO;J•
`The light emitting circuit 10;✓ may be configured as
`shown in FIG. 6. The light emitting circuit 10;✓ in FIG. 6
`comprises an N-ch MOSFET 16, a P-ch MOSFET 17, and
`a capacitor 18, as well as the EL device E;,F The address line
`A; is connected to the cathode of the EL device Ei,j and the
`gate of the FET 16. The data line Bj is connected to the
`source of the FET 16. The drain of the FET 16 is connected
`to the gate of the FET 17, and the connecting line therebe(cid:173)
`tween is grounded through the capacitor 18. The anode of
`the EL device Ei,j is connected to the drain of the FET 17.
`The source of the FET 17 is grounded.
`The switch 6; connected to the address line A; selectively
`supplies the address line A; with any one potential of the
`above-mentioned emission potential -Ve, reverse bias
`potential Va, and O V. The switch 7j connected to the data
`line Bj supplies the data line Bj with either the potential V L
`or O V. The switches 6; and 7j are turned in accordance with
`the timing signals from the drive control circuit 2.
`In a subfield for the EL device E;✓ of FIG. 6 to emit light,
`the switch 6; supplies the reverse bias potential Va to the
`address line A; when the row of the address line A; enters an
`address period. Here, the positive potential Va is applied to
`the cathode of the EL device E;J• Since the anode of the EL
`
`6
`device Ei,j is at the ground potential, the EL device E;✓ is
`reverse-biased as in the case of FIG. 5. During the address
`period, the data line Bj is supplied with the positive potential
`VL through the switch 7j so that the FET 16 is turned on to
`5 charge the capacitor 18 with the voltage VL. Here, the
`terminal voltage of the capacitor 18, a positive voltage, is
`applied to the gate of the FET 17.
`When the address period terminates to enter an emission
`period, the switch 6; supplies the emission voltage - Ve to the
`10 address line A;, turning off the FET 16. Meanwhile, the FET
`17 is turned on because the charge voltage of the capacitor
`18 is applied to its gate. Accordingly, the turning-on of the
`FET 17 equalizes the anode of the EL device E;✓ to the
`ground potential. Since the emission voltage Ve is applied to
`the EL device E;✓ in the forward direction, a current flows to
`bring the EL device Ei,j into the luminescent state.
`When the emission period terminates, the switch 6; sup(cid:173)
`plies the 0-V ground potential to the address line A; so that
`the EL device E;✓ becomes approximately O V across to enter
`a reset period.
`FIG. 7 shows a driving apparatus of simultaneous display
`system using EL devices according to the present invention.
`The driving apparatus comprises an active matrix type
`luminescent panel 20, an ND converter 21, a drive control
`25 circuit 22, a memory 24, an address scan driver 26, a data
`driver 27, and a power supply circuit 28.
`The luminescent panel 20 has a plurality of EL devices
`E1 1-Em n arranged in a matrix at a plurality of intersections
`of°addre~s linesA1-~ and data lines BcBn. The respective
`30 anodes of the EL devices E1 1-Em n are connected to a
`'
`common power supply line C. '
`The address scan driver 26 is connected to the address
`lines A 1-~ of the luminescent panel 20. The address scan
`35 driver 26 supplies the individual address lines Ac~ with
`either a potential V cc or a 0-V ground potential. The data
`driver 27 is connected to the data lines BcBn of the
`luminescent panel 20 to supply the individual data lines
`B 1-Bn with either a positive potential VL or O V. The power
`40 supply circuit 28 is connected to the power supply line C to
`supply the power supply line C with any one potential
`among an emission potential Ve, a reverse bias potential
`- Va, and the 0-V ground potential.
`The ND converter 21 samples an analog image signal
`45 input thereto in accordance with a clock signal supplied
`from the drive control circuit 22. The signal sampled is
`converted into N-bit pixel data D corresponding to respec(cid:173)
`tive pixels, and supplied to the memory 24.
`The memory 24 sequentially stores the above-mentioned
`50 pixel data D in accordance with a write signal supplied from
`the drive control circuit 22. When the storage operations for
`one screen (m rows, n columns) of the luminescent panel 20
`are finished, the memory 24 divides pixel data D11 to Dmm
`of one screen for each bit digit in accordance with a read
`55 signal supplied from the drive control circuit 22. The result(cid:173)
`ants are read by row from the first row to the m-th row, and
`successively supplied to the data driver 27 as drive pixel data
`bit groups DB 1 to DBn.
`The drive control circuit 22 generates the clock signal for
`60 the ND converter 21 and the write and read signals for the
`memory 24 in accordance with horizontal synchronizing
`signals and vertical synchronizing signals contained in the
`input image signal mentioned above.
`Moreover, the drive control circuit 22 divides a single
`65 field period in the above-mentioned input image signal into
`eight subfields. In each subfield, the drive control circuit 22
`supplies each of the address scan drive 26, the data driver 27,
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`US 6,380,689 Bl
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`5
`
`10
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`7
`and the power supply circuit 28 with a timing signal for
`directing the application of various drive pulses to the
`luminescent panel 20.
`Since the individual subfields involve common
`operations, description will be made on a single subfield
`alone. As shown in FIG. 8, all the address line AcA,,, enter
`an address period in a subfield. After the termination of the
`address period, all the address lines AcA,,, enter an emis(cid:173)
`sion period. In one field, subfields positioned temporally
`behind have longer emission periods.
`The address scan driver 26 supplies the 0-V ground
`potential, as a scan pulse SP, to the address lines in order
`from the address line A 1 . Supplying the scan pulse SP to the
`address line A,,, terminates the address period, followed by
`the emission period. Moreover, except when it supplies the 15
`scan pulses SP, the address scan driver 26 maintains the
`address lines A 1-A,,, at the positive potential Vee.
`The data driver 27 generates pixel data pulse groups
`DP 1-DP n corresponding to the drive pixel data bit groups
`DBcDBn read in succession from the memory 24, respec- 20
`tively. In the address period, these pixel data pulse groups
`DP 1-DP n generated are successively applied to the data
`lines B 1-Bn in synchronization with the scan pulses SP. For
`example, the data driver 27 generates a pixel data pulse
`having a voltage of VL when a data bit in a drive pixel data 25
`bit group DB has a logic level of "O," generates a pixel data
`pulse of O V under a logic level of "1," and applies the same
`to the data lines B 1-Bn. That is, the data driver 27 applies
`one row (n pulses) of these pixel data pulses to the data lines
`BcBn as a pixel data pulse group DP mentioned abov