UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`INTEL CORPORATION,
`Petitioner
`v.
`FG SRC LLC,
`Patent Owner
`____________________
`CASE NO.: IPR2020-01449
`PATENT NO. 7,149,867
`____________________
`
`DECLARATION OF STANLEY SHANFIELD, PH.D.,
`
` CONCERNING U.S. PATENT NO. 7,149,867
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`1
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`XILINX 1006
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`

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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
`
`I. 
`
`II. 
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1 
`A. 
`Educational and Work Background ...................................................... 1 
`B.  Materials Considered ............................................................................. 5 
`UNDERSTANDING OF THE LAW .............................................................. 7 
`A. 
`Legal Standard for Prior Art .................................................................. 7 
`B. 
`Legal Standard for Anticipation ............................................................ 8 
`C. 
`Legal Standard for Obviousness ........................................................... 9 
`D. 
`Legal Standard for Claim Construction .............................................. 13 
`E. 
`Legal Standard for Priority Date ......................................................... 19 
`III.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 20 
`IV.  BACKGROUND OF THE TECHNOLOGY ................................................ 22 
`A. 
`Conventional Computer Architecture ................................................. 22 
`B. 
`FPGA Technology ............................................................................... 25 
`C. 
`FPGA Processors ................................................................................. 26 
`D. 
`Scatter/Gather ...................................................................................... 27 
`THE ’867 PATENT ....................................................................................... 28 
`A. 
`Summary of the patent ........................................................................ 28 
`B. 
`Priority date and prosecution history .................................................. 30 
`C. 
`Claim construction .............................................................................. 35 
`1. 
`“reconfigurable processor” in all claims ................................... 35 
`2. 
`“data prefetch unit” in all claims .............................................. 35 
`3. 
`“data access unit” in claims 11-19 ............................................ 35 
`4. 
`“functional unit” ........................................................................ 36 
`5. 
`“memory hierarchy” .................................................................. 36 
`6. 
`“computational unit” in claims 11-19 ....................................... 36 
`VI.  SUMMARY OF THE PRIOR ART .............................................................. 37 
`A. 
`Prior Art Considered ........................................................................... 37 
`B. 
`State of the art at the time of the ’867 patent ...................................... 38 
`1. 
`Zhang (Ex 1003) ....................................................................... 38 
`
`V. 
`
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
`
`2. 
`Gupta (EX1004) ........................................................................ 43 
`Chien (EX1005) ........................................................................ 46 
`3. 
`C.  A person of ordinary skill in the art would have been
`motivated to combine the Zhang, Gupta and Chien
`references, which each disclose features of the
`MORPH/AMRM processor architecture ............................................. 50 
`VII.  Ground 1: Claims 1-2, 4-8 and 13-19 are obvious over Zhang and
`Gupta .............................................................................................................. 55 
`A. 
`Claim 1: ............................................................................................... 55 
`1. 
`Preamble: A reconfigurable processor that
`instantiates an algorithm as hardware comprising: ................... 56 
`1(a): a first memory structure having a first
`characteristic memory bandwidth and/or memory
`utilization .................................................................................. 59 
`1(b): a data prefetch unit coupled to the first
`memory ..................................................................................... 62 
`1(c): wherein the data prefetch unit retrieves only
`computational data required by the algorithm from a
`second memory of second characteristic memory
`bandwidth and/or memory utilization and places the
`retrieved computational data in the first memory ..................... 66 
`1(d): wherein the data prefetch unit operates
`independent of and in parallel with logic blocks
`using the computional [sic] data ............................................... 72 
`1(e): wherein at least the first memory and data
`prefetch unit are configured to conform to needs of
`the algorithm ............................................................................. 78 
`1(f): the data prefetch unit is configured to match the
`format and location of data in the second memory ................... 82 
`Claim 2: The reconfigurable processor of claim 1, wherein: .............. 86 
`1. 
`2(a): the data prefetch unit is coupled to a memory
`controller that controls the transfer of data between
`the first memory and the data prefetch unit .............................. 86 
`2(b): and [the memory controller] transmits only
`portions of data desired by the data prefetch unit and
`
`B. 
`
`2. 
`
`ii
`
`2. 
`
`3. 
`
`4. 
`
`5. 
`
`6. 
`
`7. 
`
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
`
`C. 
`
`D. 
`
`E. 
`
`F. 
`
`G. 
`
`H. 
`
`I. 
`
`discards other portions of data prior to transmission
`of the data to the data prefetch unit ........................................... 91 
`Claim 4: The reconfigurable processor of claim 1, wherein
`the data prefetch unit comprises at least one register from
`the reconfigurable processor ............................................................... 92 
`Claim 5: The reconfigurable processor of claim 1, wherein
`the data prefetch unit is disassembled when another
`program is executed on the reconfigurable processor ......................... 94 
`Claim 6: The reconfigurable processor of claim 1, wherein
`said second memory comprises a processor memory and
`said data prefetch unit is operative to retrieve data from a
`processor memory ............................................................................... 94 
`Claim 7: The reconfigurable processor of claim 6, wherein
`said processor memory is a microprocessor memory ......................... 95 
`Claim 8: The reconfigurable processor of claim 6, wherein
`said processor memory is a reconfigurable processor
`memory ................................................................................................ 96 
`Claim 13: ............................................................................................. 97 
`1. 
`13(a): A method of transferring data comprising:
`transferring data between a memory and a data
`prefetch unit in a reconfigurable processor ............................... 98 
`13(b): transferring the data between a computational
`unit and a data access unit ......................................................... 98 
`a. 
`Computational Unit(s) .................................................... 99 
`b. 
`Data Access Unit(s) ......................................................100 
`13(c): wherein the computational unit and the data
`access unit, and the data prefetch unit are configured
`to conform to needs of an algorithm implemented on
`the computational unit and transfer only data
`necessary for computations by the computational
`unit ........................................................................................... 103 
`13(d): wherein the prefetch unit operates
`independent of and in parallel with the
`computational unit................................................................... 104 
`Claim 14: ........................................................................................... 105 
`
`2. 
`
`3. 
`
`4. 
`
`iii
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
`
`J. 
`
`1. 
`
`2. 
`
`3. 
`
`2. 
`
`3. 
`
`K. 
`
`14(a): The method of claim 13, wherein the data is
`written to the memory, said method comprising: ................... 105 
`14(b): transferring the data from the computational
`unit to the data access unit ...................................................... 106 
`14(c): writing the data to the memory from the
`prefetch unit ............................................................................ 106 
`Claim 15: ........................................................................................... 108 
`1. 
`15(a): The method of claim 13, wherein the data is
`read from the memory, said method comprising: ................... 108 
`15(b): transferring only the data desired by the data
`prefetch unit as required by the computational unit
`from the memory to the data prefetch unit ............................. 108 
`15(c): reading the data directly from the data
`prefetch unit to the computational unit through a
`data access unit ........................................................................ 109 
`Claim 16: The method of claim 15, wherein all the data
`transferred from the memory to the data prefetch unit is
`processed by the computational unit ................................................. 110 
`Claim 17: The method of claim 15, the data is selected by
`the data prefetch unit based on an explicit request from the
`computational unit ............................................................................. 110 
`M.  Claim 18: The method of claim 13, wherein the data
`transferred between the memory and the data prefetch unit
`is not a complete cache line ............................................................... 111 
`Claim 19: The method of claim 13, wherein a memory
`controller coupled to the memory and the data prefetch
`unit, controls the transfer of the data between the memory
`and the data prefetch unit .................................................................. 112 
`VIII.  Ground 2: Claims 3 and 9-12 are obvious over Zhang, Gupta and
`Chien ............................................................................................................ 112 
`A. 
`Claim 3: The reconfigurable processor of claim 1, wherein
`the data prefetch unit receives processed data from on-
`board memory and writes the processed data to an external
`off-processor memory ....................................................................... 112 
`Claim 9: ............................................................................................. 118 
`
`L. 
`
`N. 
`
`B. 
`
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
`
`1. 
`
`2. 
`3. 
`
`4. 
`
`5. 
`
`6. 
`
`7. 
`
`Preamble: A reconfigurable hardware system
`comprising: .............................................................................. 118 
`9(a): a common memory ......................................................... 119 
`9(b): one or more reconfigurable processors that can
`instantiate an algorithm as hardware coupled to the
`common memory .................................................................... 121 
`9(c): wherein at least one of the reconfigurable
`processors includes a data prefetch unit to read and
`write only data required for computations by the
`algorithm between the data prefetch unit and the
`common memory .................................................................... 121 
`9(d): wherein the data prefetch unit operates
`independent of and in parallel with logic blocks
`using the computational data .................................................. 122 
`9(e): wherein the data prefetch unit is configured to
`conform to needs of the algorithm .......................................... 122 
`9(f): and [the data prefetch unit is configured to]
`match format and location of data in the common
`memory ................................................................................... 122 
`Claim 10: The reconfigurable hardware system of claim 9,
`comprising a memory controller coupled to the common
`memory and the data prefetch unit that transmits to the
`prefetch unit only data desired by the data prefetch unit as
`required by the algorithm .................................................................. 123 
`Claim 11: The reconfigurable hardware system of claim 9,
`wherein the at least one of the reconfigurable processors
`also includes a computational unit coupled to a data access
`unit ..................................................................................................... 123 
`Claim 12: The reconfigurable hardware system of claim
`11, wherein the computational unit is supplied the data by
`the data access unit ............................................................................ 124 
`
`C. 
`
`D. 
`
`E. 
`
`IX.  RESERVATION OF RIGHTS .................................................................... 124 
`X. 
`
`CONCLUSION ............................................................................................ 124 
`
`
`
`v
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
`
`I.
`
`INTRODUCTION
` My name is Stanley Shanfield Ph.D., and I am a Technical Director at
`
`Draper Laboratory in Cambridge, Massachusetts. I have prepared this report as an
`
`expert witness on behalf of Petitioner Intel Corporation (“Intel”). In this report, I
`
`will give my opinions as to whether claims 1-19 of U.S. Patent No. 7,149,867 (“the
`
`’867 patent”) (EX1001) are valid. I also provide herein the technical bases for
`
`these opinions, as appropriate. This report contains statements of my opinions
`
`formed to date, and the bases and rationale for these opinions. I may offer
`
`additional opinions based on further review of materials in this case, including
`
`opinions and/or testimony of other expert witnesses.
`
`
`
`For my efforts in connection with the preparation of this declaration, I
`
`have been compensated at my usual and customary rate for this type of consulting
`
`activity. My compensation is in no way contingent on the substance of my
`
`opinions or the results of this or any other proceedings relating to the ’867 patent.
`
`A. Educational and Work Background
`
`I am an expert in the fields of integrated circuit design, processing,
`
`manufacturing, and electronic module designs, among other fields. I have over 35
`
`years of experience as a practicing engineer. My qualifications generally are set
`
`forth in my curriculum vitae (including a list of selected publications, and the
`
`patents on which I am a named inventor), which is submitted as Attachment A.
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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` My academic training was at the University of California, Irvine,
`
`where I received my Bachelor of Science degree in 1977, in Physics. I received my
`
`Doctor of Philosophy degree from the Massachusetts Institute of Technology in
`
`1981, with a dissertation on high field superconductors. During my doctoral
`
`program at the Massachusetts Institute of Technology, I received a four-year
`
`scholarship from the Energy Research and Development Administration, which is
`
`now part of the Department of Energy. I taught courses on electronics design while
`
`in graduate school.
`
`
`
`Upon completing my Doctor of Philosophy, I worked until 1984 at
`
`Spire Corporation as a Staff Scientist, then later as a Senior Staff Scientist. There, I
`
`developed new methods for low temperature deposition of plasma-assisted CVD
`
`epitaxial silicon. I also built, operated, and characterized an ion-assisted deposition
`
`system for making coatings for semiconductors.
`
`
`
`In 1985, I joined Raytheon Corporation, where I began as Section
`
`Manager, Semiconductors and Integrated Circuits. My work involved developing
`
`processes and circuit designs for fabricating high speed multi-function integrated
`
`circuits. In 1992, I became Research Laboratory Manager, where I led a 90-
`
`employee team, in high performance semiconductor devices and circuits, including
`
`measurement and assembly. I participated in the design, layout and testing of
`
`specialized digital ASICs for airborne phased array radar and led a team that
`
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`designed multi-CPU digital signal processing ASICs for a millimeter-wave
`
`communications systems. I was part of a team that designed and demonstrated
`
`phased array control electronics that used reconfigurable memory allocation, and
`
`led a team that designed a series of experimental FPGA-based processor arrays,
`
`allowing for rapid reconfiguration needed in high speed target acquisition and
`
`missile guidance tasks.
`
`
`
`In 1996, I became Manager, Semiconductor Operations. In this
`
`capacity, I was involved with many aspects of CMOS-based IC fabrication, design
`
`and system integration. I was responsible for design and test of systems
`
`incorporating FPGAs to meet commercial requirements, including test beds for the
`
`Motorola Iridium satellite communication network.
`
`
`
`Following 14 years at Raytheon, I became a co-founder of AXSUN
`
`Technologies, where I became Vice President, Operations. Among other
`
`responsibilities, I managed the electronic system design of a real-time fiber-optic
`
`spectrum analyzer, incorporating FPGAs. I designed a complete facility for
`
`semiconductor processing, including establishing a fabrication facility in Belfast,
`
`Northern Ireland for producing thick oxide silicon-on-insulator components. I also
`
`raised $36 million in funding.
`
`
`
`In 2001, I joined Clarendon Photonics, where I was a Director.
`
`Clarendon Photonics began as a 30-person optical components startup company.
`
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`Among other accomplishments, I successfully led the electronic design team in
`
`developing microprocessor-based control electronics for fiber optic routing
`
`components.
`
`
`
`In 2003, I transitioned to the Draper Laboratory at the Massachusetts
`
`Institute of Technology (“Draper”), where I have held the position of Division
`
`Leader in the Advanced Hardware Development group, and am a Distinguished
`
`Member of Technical Staff and Technical Director. In my time at Draper, I have
`
`been responsible for in-house module and electronic system designs and have been
`
`involved in CMOS foundry implementation for multiple ASIC designs. I have led
`
`or been part of several programs and teams making use of reconfigurable
`
`processing and configurable memory systems. These systems are typically a part of
`
`state-of-the-art development work for the US defense and intelligence
`
`communities.
`
`
`
`I have been a member of many professional societies and electrical
`
`engineering industry groups over the years, such as the Institute of Electrical and
`
`Electronics Engineers (IEEE) and the American Physical Society (APS).
`
`
`
`I have received a number of academic awards and honors over the
`
`years, including awards and honors for the best Draper patent and most successful
`
`Draper development project.
`
`
`
`I have also authored or co-authored over 25 technical papers covering
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`various aspects of semiconductor devices, ICs, and portable electronics systems.
`
`
`
`I am a named inventor or co-inventor on more than nine (9) patents
`
`covering aspects of semiconductor devices, and system and circuit designs.
`
` Through the course of my educational and professional activities, I am
`
`familiar with the state of the field of digital ICs and semiconductor technologies
`
`from the early 1990s through at least 2010.
`
`
`
`I have considered information from various sources in forming my
`
`opinions. A list of materials considered is included in the list of exhibits that I
`
`understand Petitioner is filing. I may review additional documents filed in
`
`connection with this proceeding as they become available.
`
`B. Materials Considered
` The following is a listing of the materials I considered in forming the
`
`opinions set forth in this declaration:
`
` The ’867 patent and its prosecution file history (Exs. 1001, 1002);
`
` X. Zhang et al., Architectural Adaptation of Application-Specific
`
`Locality Optimizations, IEEE (1997) (EX1003);
`
` R. Gupta, Architectural Adaptation in AMRM Machines, IEEE (2000)
`
`(EX1004);
`
` A. Chien and R. Gupta, MORPH: A System for Robust Higher
`
`Performance Using Customization,” IEEE (1996) (EX1005);
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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` Amazon, Inc. v. FG SRC LLC, IPR2019-00103 (PTAB Oct. 19, 2018),
`
`Paper 1 (Amazon’s petition for IPR of the ’867 patent; Paper 20
`
`(Patent Owner’s Preliminary Response); Paper 22 (Decision Denying
`
`Institution); and Paper 24 (Decision Denying Rehearing on Denial of
`
`Institution);
`
` Holger Lange & Andreas Koch, Memory Access Schemes for
`
`Configurable Processors, Field-Programmable Logic and
`
`Applications: The Roadmap to Reconfigurable Computing (2000);
`
` Peixin Zhong & Margaret Martonosi, Using Reconfigurable Hardware
`
`to Customize Memory Hierarchies (1996);
`
` Clive Maxwell, The Design Warriors Guide to FPGAs: Devices,
`
`Tools and Flows, Mentor Graphics Corporation and Xilinx, Inc.,
`
`(2004); and
`
` J. Hennessy and D. Patterson, Computer Architecture: A Quantitative
`
`Approach, Morgan Kaufmann, (1990).
`
` With regard to the prior art textbooks listed above, I have examined
`
`them and have found them to be authoritative and representative of the knowledge
`
`of one of ordinary skill in the art at the time of their publication. Indeed, I am
`
`personally familiar with and have consulted various editions of Hennessy and
`
`Patterson during my education and career, particularly at Raytheon Commercial
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`Electronics and at Draper Laboratory (formerly MIT Instrumentation Lab).
`
`Additionally, I am aware of information generally available to, and relied upon by,
`
`persons of ordinary skill in the art at the relevant time, including technical
`
`dictionaries and technical reference materials (for example, textbooks, manuals,
`
`technical papers, articles, and relevant technical standards).
`
`II. UNDERSTANDING OF THE LAW
`
`I have applied the following legal principles provided to me by
`
`counsel in arriving at the opinions set forth in this report.
`
`A. Legal Standard for Prior Art
`
`I understand that a patent or other publication must first qualify as
`
`prior art before it can be used to invalidate a patent claim.
`
`
`
`I understand that a U.S. or foreign patent qualifies as prior art to an
`
`asserted patent if the date of issuance of the patent is prior to the invention of the
`
`asserted patent. I further understand that a printed publication, such as a book or an
`
`article published in a magazine or trade publication, qualifies as prior art to an
`
`asserted patent if the date of publication is prior to the invention of the asserted
`
`patent.
`
`
`
`I understand that a U.S. or foreign patent qualifies as prior art to an
`
`asserted patent if the date of issuance of the patent is more than one year before the
`
`filing date of the asserted patent. I further understand that a printed publication,
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`such as a book or an article published in a magazine or trade publication,
`
`constitutes prior art to an asserted patent if the publication occurs more than one
`
`year before the filing date of the asserted patent.
`
`
`
`I understand that a U.S. patent qualifies as prior art to the asserted
`
`patent if the application for that patent was filed in the United States before the
`
`invention of the asserted patent.
`
`
`
`I understand that to qualify as prior art, a reference must contain an
`
`enabling disclosure that allows one of ordinary skill to practice the claims without
`
`undue experimentation.
`
`
`
`I understand that documents and materials that qualify as prior art can
`
`be used to invalidate a patent claim as anticipated or as obvious.
`
`B.
`
`Legal Standard for Anticipation
`
`I understand that once the claims of a patent have been properly
`
`construed, the second step in determining anticipation of a patent claim requires a
`
`comparison of the properly construed claim language to the prior art on a
`
`limitation-by-limitation basis.
`
`
`
`I understand that a prior art reference “anticipates” an asserted claim,
`
`and thus renders the claim invalid, if all elements of the claim are disclosed in that
`
`prior art reference, either explicitly or inherently (i.e., necessarily present or
`
`implied).
`
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`
`
`I understand that a patent is anticipated if before such person’s
`
`invention thereof, the invention was made in this country by another inventor who
`
`had not abandoned, suppressed, or concealed it.
`
`
`
`I have written this report with the understanding that in an inter partes
`
`review anticipation must be shown by a preponderance of the evidence.
`
`C. Legal Standard for Obviousness
`
`I have been instructed by counsel on the law regarding obviousness,
`
`and understand that even if a patent is not anticipated, it is still invalid if the
`
`differences between the claimed subject matter and the prior art are such that the
`
`subject matter as a whole would have been obvious at the time the invention was
`
`made to a person of ordinary skill in the pertinent art.
`
`
`
`I understand that a person of ordinary skill in the art provides a
`
`reference point from which the prior art and claimed invention should be viewed.
`
`This reference point prevents a person of ordinary skill from using one’s insight or
`
`hindsight in deciding whether a claim is obvious.
`
`
`
`I also understand that an obviousness determination includes the
`
`consideration of various factors such as (1) the scope and content of the prior art,
`
`(2) the differences between the prior art and the challenged claims, (3) the level of
`
`ordinary skill in the pertinent art, and (4) the existence of secondary considerations
`
`such as commercial success, long-felt but unresolved needs, failure of others, etc.
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`
`
`I am informed that secondary considerations of non-obviousness may
`
`include (1) a long felt but unmet need in the prior art that was satisfied by the
`
`invention of the patent; (2) commercial success or lack of commercial success of
`
`processes covered by the patent; (3) unexpected results achieved by the invention;
`
`(4) praise of the invention by others skilled in the art; (5) taking of licenses under
`
`the patent by others; and (6) deliberate copying of the invention. I also understand
`
`that there must be a relationship between any such secondary indicia and the
`
`invention. I further understand that contemporaneous and independent invention by
`
`others is a secondary consideration supporting an obviousness determination.
`
`
`
`I understand that an obviousness evaluation can be based on a
`
`combination of multiple prior art references. I understand that the prior art
`
`references themselves may provide a suggestion, motivation, or reason to combine,
`
`but other times the link between two or more prior art references is simple
`
`common sense. I further understand that obviousness analysis recognizes that
`
`market demand, rather than scientific literature, often drives innovation, and that a
`
`motivation to combine references may be supplied by the direction of the
`
`marketplace.
`
`
`
`I understand that if a technique has been used to improve one device,
`
`and a person of ordinary skill in the art would recognize that it would improve
`
`similar devices in the same way, using the technique is obvious unless its actual
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`application is beyond his or her skill.
`
`
`
`I also understand that practical and common-sense considerations
`
`should guide a proper obviousness analysis, because familiar items may have
`
`obvious uses beyond their primary purposes. I further understand that a person of
`
`ordinary skill in the art looking to overcome a problem will often be able to fit the
`
`teachings of multiple publications together like pieces of a puzzle, although the
`
`prior art need not be like two puzzle pieces that must fit perfectly together. I
`
`understand that obviousness analysis therefore considers the inferences and
`
`creative steps that a person of ordinary skill in the art would employ under the
`
`circumstances.
`
`
`
`I understand that a particular combination may be proven obvious by
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`showing that it was obvious to try the combination. For example, when there is a
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`design need or market pressure to solve a problem and there are a finite number of
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`identified, predictable solutions, a person of ordinary skill has good reason to
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`pursue the known options within his or her technical grasp because the result is
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`likely the product not of innovation but of ordinary skill and common sense.
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`I understand that the combination of familiar elements according to
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`known methods may be proven obvious when it does no more than yield
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`predictable results. When a work is available in one field of endeavor, design
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`incentives and other market forces can prompt variations of it, either in the same
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`field or a different one. If a person of ordinary skill can implement a predictable
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`variation, obviousness likely bars its patentability.
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`It is further my understanding that a proper obviousness analysis
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`focuses on what was known or obvious to a person of ordinary skill in the art, not
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`just the patentee. Accordingly, I understand that any need or problem known in the
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`field of endeavor at the time of invention and addressed by the patent can provide a
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`reason for combining the elements in the manner claimed.
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`
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`I understand that a claim can be obvious in light of a single reference,
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`without the need to combine references, if the elements of the claim that are not
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`found explicitly or inherently in the reference can be supplied by the common
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`sense of one of skill in the art.
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`I understand that a person of ordinary skill could have combined two
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`pieces of prior art or substituted one prior art element for another if the substitution
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`can be made with predictable results, even if the swapped-in element is different
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`from the swapped-out element. The relevant question to obviousness is whether
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`prior art techniques are interoperable with respect to one another, such that a
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`person of skill would view them as a design choice, or whether a person of skill
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`could apply prior art techniques into a new combined system.
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`In sum, my understanding is that prior art teachings are properly
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`combined where a person of ordinary skill in the art having the understanding and
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,149,867
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`knowledge reflected in the prior art and motivated by the general problem facing
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`the inventor, would have been led to make the combination of elements recited in
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`the claims. Under this analysis, the prior art references themselves, or any need or
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`problem known in the field of endeavor at the time of the invention, can provide a
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`reason for combining the elements of multiple prior art references in the claimed
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`manner.
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`I have been informed and understand that the obviousness analysis
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`requires a comparison of the properly construed claim language to the prior art on
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`a limitation-by-limitation basis.
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`I have written this report with the understanding that in an inter partes
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`review obviousness must be shown by a preponderance of the evidence.
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`D. Legal Standard for Claim Construction
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`I have been instructed by counsel on the law regarding claim
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`construction and patent claims and understand that a patent may include two types
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`of clai