Applicatiom’Control Number: 10869200
`Art Unit: 2186
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`Page 8
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`and is optimized based on the memory needs of a specific program running on the reconfigurable
`
`processor}
`
`As per claims 3 and I4, Paulraj teaches in paragraph 23 that a Specific [cache] line size of
`
`contiguous data is not retrieved since the data line size is optimized-based on the memory needs
`
`of the program when executing on the reconfigurable processor. Refer also'to paragraph 29.
`
`Further, it is therefore inherent that the second memory have a charactersitic line size since
`
`Paulraj teaches in 11%22-23 that a best line size for the memory arrangement for a particular _
`
`program is determined and utilzied when that program is run. For example, a line-size
`
`characteristic would be ultized when transferring data from the L2 cache to the L1 cache.
`
`As per claim 4, Paulraj teaches that a loadfstore unit is used to access the caches (L1 -L3)
`in order to determine if cache data is present in the cache hierarchy (paragraph 6). Since the
`
`functional unit 102 (figure 6) is responsible for accessing the programmable memory unit 104,
`
`the Examiner-is therefore considering the loadfstore unit logic of the programmable memory unit
`
`that is reSponsible for for accessing the L1 and L2 caches (first and second memory types) to be
`
`a memory controller. It can be seen that the memory controller, as defined by the Examiner,
`
`controls the transfer of data between the memory (assuming second memory L2) and the data
`
`prefetch unit, since the memory controller (loadr’store unit logic) is responsible for retrieving the
`
`data from the cache if a hit occurs (paragraph 4).
`
`As per claim 5, as taught in paragraph 1, an external memory (element 18, figure 1) is
`
`general); coupled to a microprocessor and holds data to be used by the microcontroiler during
`
`program execution. The Examiner is considering the process'of writing data back to the external
`
`memory from the FPGA memory 104 containing the caches (on-board memory), such as during
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`Applicatiom'COntrol Number: 101869200
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`a write—back scheme as known in the art, to be performed by the data prefetch unit portion of the
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`functional logic as defined above by the Examiner. The data prefetch logic, as defined above, is
`
`responsible for all of the transfer of data into, out of, and between the FPGA memory 104. I
`
`As per claim 6, the Examiner is regarding a -—register-- in its broadest reasonable sense
`
`and it thus considering it be to be a unit of logic. Therefore, the portion of the function logic that
`
`is responsible for the movement of data (as defined above to be the data prefetch unit) is being
`
`considered by the Examiner as containing a --register-- portion of the reconfigurable processor
`
`since, for instance, the blocking factor and line size of the programmable memory I 12 can
`
`change, a --register-- or portion of the reconfigurable processor must be set in order to indicate
`
`the currnet line size and blocking factor when a given application is being run on the
`
`reconfigurable processor at a given point in time. Refer to paragraph 23. _
`
`As per claim 7, the Examiner is considering the process of "disassembling the data
`
`prefetch unit-- as modifying the data prefetch unit logic of the fucntion logic 102 every time the
`
`program being executed by the reconfigurable processor changes.
`
`It can be seen that the data
`
`prefetch unitchanges during these intervals since the cache line size, blocking factor, and
`
`associativity of the FPGA changes when optimal for the next program to be executed (refer-to-
`
`paragraph 23). Thus it can be seen that the data pre fetch unit logic is --disassembled-- when
`
`another program is executed by the reconfigurable processor of Paulraj.
`
`As per claim 8, as can be seen that the FPGa memory 112, that comprises the first and
`
`second memories (L1 and L2) and which is accessed by the data prefetch unit of the functional
`
`unit 102 as discussed above, is a «processor memory-- (part of Cpu 110). It can also be seen that '
`
`-
`
`the --second memory-- (L2) is also a -—processor memory-- since it is contained within
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`' ApplicationIControl Number: 10r869,200
`Art Unit: 2186
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`reconfigurable processor 1 10. Therefore, since the data pretech unit can access the L2 cache as.
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`discussed above in the rejection of claim 1, the data prefetch unit can retrive data from the L2
`
`portion of -—processor memoryul 12.
`
`I
`
`As per claim 9, as shown in figure 1 and taught in paragraph 1 of Paulraj, the system 10
`
`is actually a microprocessor, which contains a memory controller 14. The main difference
`
`between the prior art of figure 1 and the invention of Paulraj in figure 6 is that the memroy
`
`hierarchy is configurable and accessed by a fucntional unit in lieu of a separate memory
`
`controller logic (paragraph 9). Therefore, since the memory controller logic for accessing the
`
`cache hierarchy is still contained within cpu I 10 of figure 6, it can be seen that the cpu 110 is
`
`actually a microprocessor. It follows that the --processor memory-- 1 12 is therefore a
`
`;-microprocessor memory-—.
`
`As per claim 10, since the cpu 1 10 of figure 6 is a reconfigurable processor (able to
`
`reconfigure its memory heirarchy to match the needs of the application it is currently running), it
`
`can be seen that the epu memory 1 I2 is a reconfigurable processor memory.
`As per claim 1 l, Paulraj depicts a reconfigurable hardware system in figure 6. Paulraj
`
`further teaches in paragraph 26 that when a particular application is to be run by the
`
`reconfigrable processor 1 l0, a configuration vector is retrieved to program the programmable
`
`memory 1 12 (figure 6). As shown in figure 6, the step of accesing the configuration vector is
`
`executed outside ofthe reconfigurable processor 110. Therefore, the Examiner is considering
`
`the memory that contains the configuration vectors to be a--common memory-- and a data
`
`prefetch unit (reconfiguration unit 106 executing on the reconfigurable processor I 10) accessing
`
`the common memory in order to determine how to program the memory 1 12 (paragraph 29).
`
`153
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`Application/Control Number: 10/869,200
`Art Unit: 2186
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`_
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`Page 11
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`The data prefetch unit'106 is --configured~— by an application to be excuted on the sysem 110
`
`since when a new application is to be executed, the data prefctch unit is called upon (or
`
`configured) to access the configuration vector for the particular application.
`
`.
`
`The reconfigurable processor of Paulraj has the ability to collect memory usage statistics
`
`for a particular application and based on those statistics, create a configuration vector as taught in
`
`111123-24. This vector allows the programmable memory module 104 of Paulraj to be
`
`reconfigured to the most optimal memory configuration for that specific software program (flZ6).
`
`As defined by the Applicant in 1155 of the originally filed specification, a software program or
`
`application is a collection of “algorithms”; therefore, the configuration vector for a particular
`
`software program allows the system of Paulraj to instantiate a software program as hardware
`
`since the configuration vector represents optimal configuration of the hardware (programmable
`
`memory module 104 — element 112 of figure 6).
`
`As per claim 12, the Examiner is considering a «memory controller-- to be the system
`
`portion utilized when creating a new configuration vector for an application. Such a process
`
`occurs in figure 5 and taught in paragraghs 23—25 ofPaulraj. When a ncw configuration vector is
`
`created by analizing performance information that has been collected for the application. The
`
`Examiner is thereby considering the "memory controller«- to be the element of the
`
`reconfigurable hardware system that is associated with storing the new configuration vector into
`
`the common memory so that the vector can be accessed later when the same application is run
`
`again.
`
`As per claim 15, the Examiner is considering the reconfiguration module 106 of the -
`
`reconfigurable processsor 110, as comprising two distinct elements: a --computational unit» and
`
`154
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`ApplicationfCOntrol Number: 101869200
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`Page 12
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`Art Unit: 2186
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`a —-data access unit-—. The data access unit is the element that is responsible for accessing the
`
`configuration vector as taught in paragraph 29 of Paulraj; or in other words, the Examiner is
`
`considering the --data access unit-- to be the same as the --memory conitrolern defined in the
`
`rejection of claim 12. The Examiner is further considering the --computational unit-- of the
`
`rconfiguration module 106 to be the element that sets up the programmable memory module 104
`
`using the configuration vector that was accessed by the --data access unit-- (paragraph 29).
`
`As per claim 16, as taught by Paulraj in paragraph 29, the --data access unit-- supplies the
`
`configuration vector to the «computational unit-- in order to set up the programmable memory
`104 as required by the application to be run on the reconfurable processor 110.
`
`As per claim 17, the Examiner is considering a --data prefetch unit-- to be the
`
`reconfiguration unit 106 of reconfigurable processor 1 10 (figure 6). As taught in paragraph 26
`
`and 29 of Paulraj, the --data prefetch unit—- accesses a memory in order to determine if a
`
`configuration vector is known for a given application, and if so, the vector is retrieved (from the
`
`memory). If this "data“ (configuration vector) is not known then a simulation is performed with
`
`the application in order to collect performance information. The Examiner is considering the
`
`element that executes and collects the performance data as being a --computational unit-- and the
`
`element of Paulraj that stores the configuration vector, once determined, to be a --data access
`
`unit—- since it stores the vector into the --memory-- from which it can be later retrieved (step 212
`
`of figure 5).
`
`All of the computational, data access, and data prefetch units are configured by a
`
`program, as immediately discussed. As defined by the Examiner, the “computational unit” of
`
`Paul raj is being considered to be the element of the system of Paulraj that executes and collects
`
`155
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`155
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`ApplicationIControl Number: 10(869300
`Art Unit: 2186
`
`-
`
`Page 13
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`the performance data regarding how a specific application utilizes memory in order to determine
`
`an optimal memory configuration as discusses in 112?. Figure 5 of Paulraj shows a method for
`
`creating a configuration vector by using the --computational unit-- in steps 204-206. The
`
`Examiner is considering the inherent program that is being executed in order to perform the
`
`steps of figure 5 to be the program that configures the computational "unit. Therefore, it can be
`
`seen that Pauiraj suggests configuring the computational unit by a program. The program of
`
`figure 5 configures the computational unit to collect data for a specific application’s memory
`
`Iusage statistics in order to create a configuration vector that allows the system of Pauli-a] to
`
`optimally reconfigure the programmable memory module 104. Thus the computational unit can
`
`be configured to collect memory usage statistics for a plurality of applications that are to be
`
`executed by the recOnfigurable processor 100 of Paulraj (1123).
`
`The same reasoning applies to the data access and data prefetch units. The program that
`
`is'executing the steps of figure 5 (Le. running on the system of Paulraj that implements the
`
`method) configures the data access unit to retriever‘store a configuration vector (step 212) based
`
`on if a new configuration vector had to be created and further configures the data prefetch unit to
`
`search for a configuration vector and retrieve that vector if found (steps 200 and 212).
`
`As per claim 18, the --data-- (configuration vector) is transferred from the
`
`-«computational unit-- to the --data access unit-- when the configuration unit has created a
`
`_
`
`configuration vector (step 208 of figure 5). The --data-- is written to the memory --from-— the
`
`--data prefetch unit-- since the data prefetch unit (reconfiguration unit 106) is the element that
`
`executed the beginning of the configuration vector creation process (step 200 of figure 5). Refer
`
`156
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`156
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`

`

`ApplicationfControl Number: 101869300
`
`Art Unit: 2186
`
`Page 14
`
`'
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`to paragraph 26. Thus the Examiner is considering the data as being written --from-- the data
`
`prefetch unit.
`
`As per claim 19, as taught in paragraph 26, if the configuration vector is known, the
`
`vector is retrieved from the memory to the data prefetch unit (reconfiguration unit 106). The
`
`data is read directly from the data prefetch unit when a request to create a configuration vector is
`
`made for a new application as shown in figure 6 since the data prefetch unit is reSponsible for
`
`being the vector creation process. The data is directed from the data prefetch unit (reconfigure
`
`logic) to be read from the memory by the data access unit to‘the computational unit where it is
`
`processed to produce a configuration vector.
`
`As per claim 20, as stated above, the configuration vector (--data~-) is created by the
`
`computational unit via acquired simulation data. The configuration vector is the resultant
`
`product that is transferred from the memory to the data prefect unit when it is determined that the
`
`configuration vector for the application is available (paragraph 26). Thus --all-- of the data that
`
`is transferred is processed by the computational unit (aibcit before the transfer occurs) since the
`
`data prefetch unit required the entire configuration vector in order to set up the programmable
`
`memory 112.
`
`As per claim 21, Paulraj shows in paragraph 26 that an explicit request for the
`
`configuration vector for the current application results in the data (if it exists) selected for the
`
`optimal configuration of the programmable memory 112 for that application.
`
`- As per claim 22, the Examiner is not considering the data (configuration vector) to be the
`
`size of a complete cache line since the data is used to create a cache hierarchy.
`
`In other words,
`
`the caches (Ll-L3) of the programmable memory I 12 are not programmed when the data is I
`
`157
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`ApplicationfControl Number: 10!869,200
`Art Unit: 2186
`
`_
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`Page 15
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`transferred from the memory to the data prefetch unit; therefore, the data cannot be a complete
`
`cache line.
`
`As per claim 23, since the Examiner defined the portion of the reconfiguration unit that
`
`accesses the configuration file (data) from the memory, the Examiner is defining the logic that
`
`controls the actual transfer of that data to the data prefetch unit (portion of the reconfiguration
`
`unit that executes the fetch of the configuration vector and then programs the programmable
`
`memory 112) to be a --memory controller--. Thus the data access unit determines whether a
`
`cOnfiguration vector exists for an application and if so, the memory controller sends that data to
`
`the data prefetch unit.
`
`As per claim 24, Paulraj shows a reconfigurable processor in figure 6 that comprises a
`
`computation unit 1 10 and a data access unit (elements 120 and l 14, which comprise the
`
`reconfiguratiOn unit 106 of figure 4 - 1128). In figure 6, the data access unit can be seen as being
`coupled to the computational unit. The data access unit retrieves data (configuration vector)
`
`from a memory internal to the data access unit (Le. reconfiguration unit) and supplies the data to
`
`the computation unit in the form of modifications to the cache FPGA module -1 12. Refer to 1123.
`i The Examiner is considering the inherent program that is being exeCuted in order to
`
`perform the Steps of figure 5 to be the program that configures the computational unit.
`
`Therefore, it can .be seen that Paulraj suggests configuring the computational unit by a program.
`
`The program of figure 5 configures the computational unit to collect data for a specific
`
`application’s memory usage statistics in order to create a configuration vector that allows the
`
`system of Paulraj to optimally reconfigure the programmable memory module 104. Thus the
`
`158
`
`158
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`

`

`ApplicationfControl Number: 101369200
`Art Unit: 2186
`
`Page 16
`
`I
`
`computational unit can be configured to collect memory usage statistics for a plurality of
`
`applications that are to be executed by the reconfigurable processor 100 of Paulraj ($23).
`
`The data access unit (Specifically the memory portion used to store configuration profiles
`
`for the different application programs) is configured by the program that is responsible for
`
`running the method of figure 5 of Paulraj as discussed supra. When a new application is to be
`
`run, [as a result] the program performs the steps 204-206 to configure the reconfiguration unit to
`
`collect statistics regarding the memory usages (caches L1, L2, and 1.3) of the application and a
`configuration vector is associated with the respective application and'stored in the
`
`reconfiguration unit. Refer to “23—24. When an application is known, the program executing
`
`the method of figure 5 [as a result] configures the data access unit (reconfiguration unit) to
`
`retrieve the associated configuration vector-and apply it to the FPGA memory of the
`
`reconfi gurable processor (1R9).
`
`In other words, once the software program has been loaded into the computational unit, a
`
`variety of simulations are performed and memory usage statistics are gathered by the
`
`computational unit in order to create a configuration vector as taught in 1]1[23—24. This vector
`
`allows the programmable memory module 104 of Paulraj to be reconfigured to the most Optimal
`
`memory configuration for that specific software program (1&6). As discussed supra, a software
`
`program or application is a collection of “algorithms”; therefore, the configuration vector for a
`
`particular software program allows the system of Pauiraj to instantiate a sofiware program as
`
`hardware since the configuration vector represents optimal configuration of the hardware
`
`(programmable memory module 104 - element 1 12 of figure 6).
`
`159
`
`159
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`

`

`Applicatiom‘Control Number: 10869200
`Art Unit: 2186
`
`Page 17
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to Shane M. Thomas whose telephcine number is (571) 272-4188.
`
`The examiner can normally be reached on M-F 8:30 - 5:30.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Matt M. Kim can be reached on (571) 23'2-4182. The fax phone number for the
`
`organization where this application or proceeding is assigned is 571-273-8300
`
`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished I
`
`applications is available through Private PAIR only. For more information about the PAIR
`
`system, see httpjr'pair-direct.uspto.gov. Should you have questions on access to the Private PAIR
`
`system, contact the Electronic Business Center (EBC) at 866-217-919? (toll-free).
`
`in“
`
`Shane M. Thomas
`
`'
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`”a (”s—i
`
`HONGGI‘DNG KW _
`PRIMARY EXAMINER
`
`160
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`160
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`U.S. Patent and Trademark Office
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`Part of Paper No. 10152005
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`161
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`Search Notes
`
`ApplicationICIJntrol No.
`
`10369200
`Examiner
`
`Applicantisllpatent Iunder
`Reexamination
`
`POZNANOVIC ET AL.
`Art Unit
`
`Shane M. Thomas
`
`2186'
`
`'
`SEARCH NOTES
`(INCLUDING SEARCH STRATEGY}
`—-
`
`Updated East Search
`
`10:1 512005
`
`10’15'9005
`
`?1 11170-173 (te'xt search only - sea
`search printout)
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`
`
`US. Patent and Trademark Office
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`Part of Paper No. 10152005
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`162
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`162
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`Jan-054096
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`RECEIVED
`CENTRAL FAXCENTEI?!
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`JAN 05 2055
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`T-Blil Hal/HUB
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`emanates}
`Appmul hr use mmanammona. 0MB M16031
`PmTMENT 0F COMMERCE
`Palam an: Tndcrrw
`monkeys.“
`was: I: die .
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`- I wk. -
`2
`.1
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`
`
`ertificate of Transmission under 37 CFR 1.8
`
`Serial No. 10!869,200
`
`Application of: Daniei Poznancvic. David E. Caiiga. and Jeffrey Hammes
`
`Filed: June 16. 2004
`
`Art Unit: 2186
`
`Examiner. Thomas, Shane M.
`
`Attorney Docket No. SRCOZB
`
`- C
`
`SYSTEM AND METHOD OF ENHANCING EFFICIENCY AND UTILIZATION
`. For:
`OF MEMORY BANDWIDTH IN RECONFIGURABLE HARDWARE
`
`Confirmation No.: 5929
`
`Custorner No; 25235
`
`9225
`
`I hereby certify that this correspondence is being facsimile transmitted to the United
`States Patent and Trademark Office
`
`1. Amendment in response to the Office Action dated October 19, 2005.
`
`‘5
`
`mine
`
`Date
`
`9
`No. of Pages
`(incl. Govemhaei]
`
`to centralized fax number: 571-273-8300
`
`Julie Lgngg
`Typed or printed name of person signing Certificate
`
`Note: Each paper must have its own certificate of transmission, or its certificate must
`identify each submitted paper.
`
`Client Reference No. 804043031001
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`Fax No. 719-448—5922
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`“ICE . ”28? in
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`PM 10’ RCVD AT 100605057114 PM |Eastern Standard Time]‘ WkUSPTO-EFIRf-fiififl ‘ DiiiS:2?383iJfl ' CSJDrt" BURhTIOH (IIIn-sslilii-ii
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`163
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`163
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`

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`-
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`Jan |]5 ZIJUE
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`14:?
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`run
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`-HDEAIIIHART50II
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`RECEIVED
`CENTRAL FAX CENTER
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`JAN 0 5 2005
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`Client Matter No. 30404.0033301
`Via Facsimile
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Serial No. 10!869.200
`
`. Application of: Daniel Poznanovic. David E. caiiga,
`and Jeffrey Hammes
`Filed: June 16. 2004
`
`Art Unit: 2186
`
`Confirmation No.1 5929
`
`_
`Customer No.. 25235
`
`BANDWIDTH IN RECONFIGURABLE HARDWARE
`
`Examiner: Thomas. Shane M.
`
`Attorney Docket No. SRO-028
`
`SYSTEM AND METHOD OF ENHANCING
`For:
`EFFICIENCY AND UTILIZATION OF MEMORY
`
`AMENDME
`
`MAIL STOP AMENDMENT
`Commissioner for Patents
`PO. Box 1450
`Alexandria, VA 22313-1450
`
`Sir:
`
`In response to the office Communication maiied October 19, 2005. please
`
`amend the above-identified application as follows:
`
`Amendments to the Claims are reflected in the listing of claims which
`
`begins on page 2 of this paper.
`
`RemarkeIArguments begin on page 6 of this paper.
`
`“165- "283' u
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`PAGE 2ii' RCIID fiT Iiiilflfifi Iiiiiii PM [Eastern StandaId Timel‘ SVR:USPTO£FXRF-GI39‘ DIII‘SIZTSIMB ‘ CSIDH‘ DURATION (mm-ss):02-12
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`Jan-05-2G0614:ET
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`It
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`T-EIU
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`9003/00!
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`F-DIZ
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`Serial No. 10(369200
`Reply to Office Action of October 19, 2005
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`Amendments to the Claims:
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`This listing of claims witi replace all prior versions and listings of claims in the
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`application:
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`Ligfing of Claims:
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`1.
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`(Previously Presented) A reconfigurable processor that instantiates
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`an algorithm as hardware comprising:
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`a first memory having a first characteristic memory bandwidth andlor
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`memory utilization; and
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`a data prefetch unit coupled to the first memory, wherein the data prefetch
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`unit retrieves data from a second memory of second characteristic memory
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`bandwidth andror memory utilization and place the retrieved data in the first
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`memory and wherein at
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`least
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`the first memory and data prefetch unit are
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`configured by a program.
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`2.
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`3.
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`4,
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`(Cancelled)
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`(Cancelled)
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`(Previously Presented) The reconfigurable processor of claim 1.
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`wherein the data prefetch unit is coupled to a memory controller that controls the
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`transfer of the data between the second memory and the data prefetch unit.
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`5.
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`(Previously Presented) The reconfigurable processor of claim 1,
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`wherein the data prefetch unit receives processed data from on-processor
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`memory and writes the processed data to an external ofisproceSsor memory.
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`6.
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`(Original) The reconfigurable processor of claim 1. wherein the
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`data prefetch unit comprises at
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`ieast one register from the reconfigurable
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`processor.
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`7.
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`(Original) The reconfigurable processor of claim 1. wherein the
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`data prefetch unit is disassembled when another program is executed on the
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`reconfigurable processor.
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`8.
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`(Previously Precented) The reconfigurable processor of claim 1
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`wherein said second memory comprises a processor memory and said data
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`prefetch unit is operative to retrieve data from the processor memory.
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`9.
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`(Original) The reconfigurable processor of claim 8 wherein said
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`processor memory is a microprocessor memory.
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`10.
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`(Original) The reconfigurable processor of claim 8 wherein said
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`processor memory is a reconfigurable processor memory.
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`11.
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`(Previously Presented)
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`A reconfigurable hardware system.
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`comprising:
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`a common memory; and
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`one or more reconfigurable processors that can instantiate an algorithm
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`as hardware coupled to the common memory. wherein at least one of the
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`reconfigurabte processors includes a data prefetch unit to read and write data
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`between the data prefetch unit and the common memory. and wherein the data
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`prefetch unit is configured by a program executed on the system.
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`12.
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`(Original)
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`The reconfigurable hardware system of claim 11,
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`comprising a memory controller coupled to the common memory and the data
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`prefetch unit.
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`13.
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`(Cancelled)
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`14.
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`(Cancelled)
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`15.
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`(Previously Presented) The reconfigurable hardware system of
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`claim 11. wherein the at least one of the reconfigurable processors also includes
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`a computational unit coupled to a data access unit.
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`16.
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`(Original)
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`The reconfigurable hardware system of claim 15,
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`wherein the computational unit is supplied the data by the data access unit.
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`17.
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`(Prevlously Presented) A method of transferring data comprising:
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`transferring data between a memory and a data- prefetcn unit
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`in a
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`reconfigurable processor; and
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`transferring the data between a computational unit and a data access unit.
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`wherein the computational unit and the data access unit. and the data prefetch
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`unit are configured by a program.
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`13.
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`(Original) The method of claim 17. wherein the data is written to
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`the memory, said method comprising:
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`transferring the data from the computational unit to the data access unit;
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`and
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`writing the data to the memory from the data prefetoh unit.
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`19.
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`(Previously Presented) The method of claim 17, wherein the data
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`is read from the memory. said method comprising:
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`transferring the data from the memory to the data prefetch unit; and
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`reading the data directly from the data prefetch unit to the computational
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`unit through the data access unit.
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`20.
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`(Original) The method of claim 19, wherein all the data transferred
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`from the memory to the data prefelch unit is processed by the computational
`unit.
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`21-
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`(Original) The method of claim 19. wherein the data is selected by
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`the data prefetch unit based en an explicit request from the computational unit.
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`22.
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`(Original) The method of claim 17, wherein the data transferred
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`between the memory and the data prefetch unit is not a complete cache line.
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`23.
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`(Original) The method of claim 17, wherein a memory controller
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`coupled to the memoryr and the data prefetch unit, controls the transfer of the
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`data between the memory and the data prefetch unit.
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`24.
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`(Cancelled)
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`Serial No. 101869.200
`Reply to Office Action of October 19. 2005
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`REMARKSIARGUMENTS
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`Claims 1. 4—12. and 15-24 were presented for examination and are pending
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`in this application.
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`In an Official Office Action dated October 19, 2005. claims 1, 4-
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`12. and 15-24 were rejected. Claim 24 is canceled without prejudice and no new
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`claims are presently added. Claims 1. 4-12. and 15-23 remain pending. The
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`Applicants thank the Examiner for his consideration and address the Examiner's
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`comments concerning the claims pending in this application below.
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`Rejection of the Claims under 35 U.S.C. §102(e)
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`Claims 1. 3. 4. 7-10. and 12-18 were rejected under 35 U.S.C. §102(e) as
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`being anticipated by U.S. Patent Application Publication No. 2003!0084244
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`(“Paulraj”). Applicants respectfully traverse these rejections in light of the following
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`remarks.
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`MPEP §2131 provides:
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`“A claim is anticipated only if each and every element as set forth in
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`the claim is found. either expresslyr or inherently described. in a
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`single prior art reference.” Verdegall Bros. v. Union Oil Co. of
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`Califomie. 8'14 F26 6328. 631. 2 U.S.P.Q.2d 1051, 1053 (Fed.
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`Cir.198?). “The identical invention must be shown in as complete
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`detail as contained in the ctaim." Richardson v. Suzuki Motor Co..
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`863 F.2d 1226. 1236. 9 U.S-P.Q.2d 1913. 1920 (Fed. Cir. 1989).
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`Peuiraj fails to disclose each and every limitation recited in the claims. The
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`Examiner reasons that Paulraj discloses a system having a program that
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`reconfigures computational units. data access units. and pre-fetch units. The
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`Applicants disagree.
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`The Examiner's logic in making the above assertion ls faulty. Assume for
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`argument sake (as does the Examiner) that the computational unit Is the element of
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`the Paulrai system that executes and collects performance data regarding an
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`application to determine an optimal memory configuration. The program operating
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`on the Paulra} system depicted In Figure 5 of Paulraj "configures” the collection
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`process so as to ascertain information about a specific application.
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`In this sense
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`the Examiner uses the term configure to state that the program executed by the
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`Pauiraj system modifies, directs. andior controls the collection means (the
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`computational unit) to properly assess the target application so that the memory
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`can be optimally configured.
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`The Examiner man extends this argument to the data access units and pre-
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`fetch units. While such an extension is perhaps conceivable today given the
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`present invention, it is not, nonetheless, disclosed by Paulra]. Nor Is it reasonable
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`to conclude that such an extension would be apparent to one skilled in the art at the
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`time of the Applicants‘ invention.
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`As the Examiner points out. Paulral disctoses creating a “configuration vector
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`containing data relating to the optimal configuration to the necessary instruction for
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`programming the programmable memory module-" Pauirat [0024]. Paulraj also
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`discloses a reconfiguration module that uses the vector to configure the
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`programmable memory module. Once the Paulraj system collects information
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`about the target application and creates the configuration vector for optimal
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`memory module configuration, "the configuration vector is then retrieved (step 212),
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`used to program the FPGA module (step 214), and the application is executed with
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`the optimal memory configuration for that application (step 216).” Pautra] [0026].
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`The “program” that the Examiner considers to configure the computational
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`unit does not, according to Paulraj. ”configure” the data acce