IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`FG SRC LLC,
`
`Plaintiff,
`
`Case No. 1:20-cv-00601-LPS
`
`v.
`
`JURY TRIAL DEMANDED
`
`XILINX, INC.,
`
`Defendant.
`
`PLAINTIFF’SECOND AMENDED COMPLAINT FOR PATENT INFRINGEMENT
`
`Plaintiff FG SRC LLC (“SRC”) files this Second Amended Complaint for Patent
`
`Infringement (“Second Amended Complaint”) against Defendant Xilinx, Inc. (“Defendant”
`
`or “Xilinx”). Plaintiff alleges as follows:
`
`I.
`
`NATURE OF THE ACTION
`
`1. This is an action for infringement of U.S. Patent No. 9,153,311 (the “’311 patent”).
`
`2. SRC is a limited liability company incorporated in Delaware and is the successor to SRC
`
`Computers, LLC (“SRC Computers”).
`
`3. Xilinx, Inc. is a Delaware corporation with its principal place of business located at 2100
`
`Logic Drive, San Jose, California 95154.
`
`II.
`
`JURISDICTION
`
`4. This action arises under the Patent Laws of the United States, 35 U.S.C. § 1, et seq.,
`
`including 35 U.S.C. §§ 271, 281, 283, 284, and 285. This is a patent infringement lawsuit, over
`
`which this Court has subject matter jurisdiction under 28 U.S.C. §§ 1331 and 1338(a).
`
`5. This Court has general and specific personal jurisdiction over Defendant because it is
`
`present in and transacts and conducts business in and with residents of this District and the
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 1
`
`

`

`State of Delaware. Defendant is incorporated in the State of Delaware and has conducted and
`
`does conduct business therein. Defendant has purposefully and voluntarily availed itself of the
`
`privileges of conducting business in the United States and the State of Delaware by
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`continuously and systematically placing goods into the stream of commerce through a
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`distribution channel with the expectation that they will be purchased by consumers in
`
`Delaware. Plaintiff’s causes of action arise directly from Defendant’s business contacts and
`
`other activities in the State of Delaware.
`
`6. Upon information and belief, Defendant has committed acts of infringement in this
`
`District giving rise to this action and does business in this District, including making sales
`
`and/or providing services and support for its customers in this District. Defendant purposefully
`
`and voluntarily sold one or more of its infringing products with the expectation that they
`
`would be purchased by consumers in this District. These infringing products have been and
`
`continue to be purchased by consumers in this District.
`
`III. VENUE
`
`7. Venue is proper as to Defendant under 28 U.S.C. § 1400(b) in that Defendant is
`
`incorporated in Delaware and, therefore, resides in this District. TC Heartland LLC v. Kraft
`
`Foods Grp. Brands LLC, 137 S. Ct. 1514, 1521 (2017).
`
`IV.
`
`FG SRC LLC AND DEFENDANT’S PRODUCTS
`
`A. FG SRC LLC
`
`8. SRC Computers was co-founded by Seymour R. Cray, Jim Guzy, and Jon Huppenthal
`
`in 1996 to produce unique high-performance computer systems using Intel’s Merced
`
`microprocessor.
`
`9. SRC is the successor to SRC Computers.
`
`10. Jim Guzy is a co-founder of Intel Corporation and served on Intel’s board for 38 years.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 2
`
`

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`11. Mr. Guzy was named to Forbes Midas List, which surveys the top tech deal makers in
`
`the world, in 2006 and 2007.
`
`12. Seymour Cray was an American electrical engineer and supercomputer architect who
`
`designed a series of computers that were the fastest in the world for decades.
`
`13. Mr. Cray has been credited with creating the supercomputing industry.
`
`14. Unfortunately, Mr. Cray died shortly after founding SRC Computers.
`
`15. But his legacy was carried on by Jon Huppenthal and a talented team of engineers that
`
`worked with Mr. Cray and Mr. Huppenthal for decades.
`
`16. SRC Computers’ focus was creating easy-to-program, general-purpose reconfigurable
`
`computing systems.
`
`17. In early 1997, Mr. Huppenthal and his team realized that the microprocessors of the
`
`day had many shortcomings relative to the custom processing engines that they were used to.
`
`18. As a result, they decided to incorporate dedicated processing elements built from Field
`
`Programmable Gate Arrays (“FPGAs”) and that idea quickly evolved into a novel system
`
`combining reconfigurable processors and Central Processing Units (“CPUs”).
`
`19. SRC Computers’ heterogenous system had 100x performance, 1/50th of the operating
`
`expense, 1/100th of the power usage, and required 1/500th of the space of more traditional
`
`computer systems.
`
`20. SRC Computers’ proven systems are used for some of the most demanding military
`
`and intelligence applications, including the simultaneous real-time processing and analysis of
`
`radar, flight and mission data collected from a variety of aerial vehicles in over 1,000 successful
`
`counter-terrorism and counter-insurgency missions for the U.S. Department of Defense.
`
`21. SRC Computers offered its first commercial product in 2015 called the Saturn 1 server.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 3
`
`

`

`22. The Saturn 1 was 100 times faster than a server with standard Intel microprocessors
`
`while using one percent of the power.
`
`23. The Saturn 1 was designed to be used in HP’s Moonshot server chassis for data centers.
`
`24. SRC Computers has had over 30 U.S. patents issued for its innovative technology.
`
`25. SRC Computers’ patent portfolio covers numerous aspects of reconfigurable computing
`
`and has more than 2,090 forward citations.
`
`26. In February 2016, SRC Computers restructured into three new entities: a corporate
`
`parent FG SRC LLC, an operating company DirectStream, LLC (“DirectStream”), and a
`
`licensing entity SRC Labs, LLC (“SRC Labs”).
`
`B. Accused Products
`
`27. In this Second Amended Complaint, Plaintiff accuses the following Xilinx products
`
`(collectively “Accused Products”) of infringing the ’311 patent. For clarity, accused product
`
`families are listed, as are exemplary device names and/or part numbers or part number
`
`prefixes.
`
`Product Family
`
`Exemplary Device Names
`
`Alveo accelerator
`cards
`Kintex UltraScale+
`Evaluation Kit
`Virtex UltraScale+
`Evaluation Kit
`Zynq UltraScale+
`Evaluation Kits and
`Characterization Kits
`Kintex UltraScale
`Evaluation Kit
`Virtex UltraScale
`Evaluation Kit
`Virtex-7 Evaluation
`Kits and Connectivity
`Kits
`
`U25, U200, U250, U280,
`SN1022 (aka SN1000)
`KCU116
`
`VCU118
`
`ZCU102, ZCU104, ZCU106,
`ZCU111, ZCU208, ZCU216,
`ZCU1275, ZCU1285
`KCU105
`
`VCU108
`
`VC707, VC709
`
`Exemplary Part Numbers
`and/or Part Number Prefixes
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 4
`
`

`

`Product Family
`
`Exemplary Device Names
`
`Zynq-7000 Evaluation
`Kits
`Kintex UltraScale+
`FPGA devices
`
`Virtex UltraScale+
`FPGA devices
`
`Zynq UltraScale+
`MPSoC: CG devices
`
`Zynq UltraScale+
`MPSoC: EG devices
`
`Zynq UltraScale+
`MPSoC: EV devices
`Zynq Ultrascale+
`RFSoC devices
`
`Kintex UltraScale
`FPGA devices
`
`Virtex UltraScale
`FPGA devices
`
`Spartan 7-Series
`FPGA devices
`Artix 7-Series FPGA
`devices
`
`Kintex 7-Series FPGA
`devices
`
`ZC702, ZC706
`
`KU3P, KU5P, KU9P,
`KU11P, KU13P, KU15P,
`KU19P
`VU3P, VU5P, VU7P, VU9P,
`VU11P, VU13P, VU19P,
`VU23P, VU27P, VU29P,
`VU31P, VU33P, VU35P,
`VU37P, VU45P, VU47P,
`VU57P
`ZU2CG, ZU3CG, ZU4CG,
`ZU5CG, ZU6CG, ZU7CG,
`ZU9CG
`ZU2EG, ZU3EG, ZU4EG,
`ZU5EG, ZU6EG, ZU7EG,
`ZU9EG, ZU11EG, ZU15EG,
`ZU17EG, ZU19EG
`ZU4EV, ZU5EV, ZU7EV
`
`ZU21DR, ZU25DR,
`ZU27DR, ZU28DR,
`ZU29DR, ZU39DR,
`ZU42DR, ZU43DR,
`ZU46DR, ZU47DR,
`ZU48DR, ZU49DR
`KU025, KU035, KU040,
`KU060, KU085, KU095,
`KU115
`XCVU065, XCVU080,
`XCVU095, VCVU125,
`XCVU160, XCVU190,
`XCVU440
`
`
`
`
`
`
`Exemplary Part Numbers
`and/or Part Number Prefixes
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`XC7S6, XC7S15, XC7S25,
`XC7S50, XC7S75, XC7S100
`XC7A12T, XC7A15T,
`XC7A25T, XC7A35T,
`XC7A50T, XC7A75T,
`XC7A100T, XC7A200T
`XC7K70T, XC7K160T,
`XC7K325T, XCE7K325T,
`XC7K355T, XCE7K355T,
`XC7K410T, XCE7K410T,
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 5
`
`

`

`Product Family
`
`Exemplary Device Names
`
`Virtex 7-Series FPGA
`devices
`
`
`
`Zynq-7000 SoC
`devices
`
`Z-7007S, Z-7012S, Z-7014S,
`Z-7010, Z-7015, Z-7020,
`Z-7030, Z-7035, Z-7045,
`Z-7100
`
`
`
`28. Each of the Accused Products includes an FPGA.
`
`Exemplary Part Numbers
`and/or Part Number Prefixes
`XC7K420T, XCE7K420T,
`XC7K480T, XCE7K480T
`XC7V585T, XCE7V585T,
`XC7V2000T, XC7VX330T,
`XCE7VX330T, XC7VX415T,
`XCE7VX415T, XC7VX485T,
`XCE7VX485T, XC7VX550T,
`XCE7VX550T, XC7VX690T,
`XCE7VX690T, XC7VX980T,
`XCE7VX980T, XCVX1140T,
`XC7VH580T, XC7VH870T
`XC7Z007S, XC7Z012S,
`XC7Z014S, XC7Z010,
`XC7Z015, XC7Z020, XC7Z030,
`XC7Z035, XC7Z045,
`XC7Z100
`
`29. In contrast to a purpose-built chip which is designed with a single function in mind and
`
`then hardwired to implement it, an FPGA is more flexible.
`
`30. An FPGA can be programmed in the field, after it has been plugged into a socket on a
`
`PC board.
`
`31. FPGAs are based around a matrix of configurable logic blocks (“CLBs”) connected via
`
`programmable interconnects.
`
`32. FPGAs can be reprogrammed to desired application or functionality requirements after
`
`manufacturing. This feature distinguishes FPGAs from Application Specific Integrated
`
`Circuits (ASICs), which are custom manufactured for specific design tasks.
`
`33. Today’s FPGAs easily push the 500 MHz performance barrier.
`
`34. Programming an FPGA is a matter of connecting CLBs to create the desired logical
`
`functions (AND, OR, XOR, and so forth) or storage elements (flip-flops and shift registers).
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 6
`
`

`

`35. Unlike a CPU which is primarily serial (with a few parallel elements) and has fixed-size
`
`instructions and data paths (typically 32 or 64 bit), an FPGA can be programmed to perform
`
`many operations in parallel, and the operations themselves can be of almost any width, large
`
`or small.
`
`36. The highly parallelized model in FPGAs is ideal for building custom accelerators to
`
`process compute-intensive problems.
`
`37. An FPGA has the potential to provide a 30x or greater speedup to many types of
`
`genomics, seismic analysis, financial risk analysis, big data search, and encryption algorithms
`
`and applications.
`
`38. The Alveo U200 provides up to 90x higher performance than CPUs on key workloads
`
`at 1/3 the cost. See https://www.xilinx.com/publications/product-briefs/alveo-product-
`
`brief.pdf.
`
`39. The Alveo U280 provides up to 3,000 times higher throughput than CPUs on key
`
`workloads such as Key-Value-Store. See https://www.xilinx.com/publications/product-
`
`briefs/alveo-u280-product-brief.pdf.
`
`40. Defendant’s customers can use FPGAs to accelerate its applications more than 30x
`
`when compared with servers that use CPUs alone.
`
`41. The speed increases referenced in the prior four paragraphs are a result of the FPGAs
`
`handling compute-intensive, deeply pipelined, hardware-accelerated operations, which also
`
`allows for highly parallelized computing.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 7
`
`

`

`V. MARKING AND NOTICE
`
`A. Marking and Constructive Notice to Defendant.
`
`42. SRC Computers complied with 35 U.S.C. § 287 by (i) placing the required notice on all,
`
`or substantially all, of its products made, offered for sale, sold, or imported into the United
`
`States, or (ii) providing actual notice to Defendant.
`
`43. For example, SRC Computers placed notices such as the following on all, or
`
`substantially all, of its products since at least February 19, 2013:1
`
`
`44. The website listed in the notice, WWW.SRCCOMP.COM/
`
`TECHPUBS/PATENTEDTECH.ASP, stated the following:
`
`
`
`1
`E.g.,https://web.archive.org/web/20100930014237/http://www.srccomp.com/techpubs/pat
`entedtech.asp.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 8
`
`

`

`
`B. Actual Notice to Defendant.
`
`
`
`45. Xilinx is well-aware of the patent asserted in this action and that instrumentalities
`
`accused herein infringe that patent.
`
`46. On or around February 22, 2013, counsel for SRC Computers sent a notice letter to
`
`Xilinx advising that “Our client has recently become aware of Xilinx’ Zynq-7000 All
`
`Programmable SoC devices which are stated to integrate an ARM® dual-core Cortex™-A9
`
`CPU as an application processor unit in conjunction with programmable logic. From the
`
`information presently available to us, these devices may possibly involve SRC Computers’
`
`patented technology.”
`
`47. Between July 2015 and November 2015 SRC Computers and Xilinx communicated
`
`regarding a potential acquisition by Xilinx of SRC Computers and/or its intellectual property
`
`(“IP”). Persons involved on behalf of Xilinx included Greer Person, Ron Satori, Nate Gazdik,
`
`Michael White, and Ivo Bolsens. Persons involved on behalf of SRC Computers included
`
`Brandon Freeman and Jon Huppenthal.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 9
`
`

`

`48. A third party, 3LP Advisors, LLC (“3LP”), assisted with discussions on behalf of SRC
`
`Computers.
`
`49. In order to assist Xilinx with reviewing SRC Computers’ patent portfolio, 3LP
`
`provided Xilinx with a list of SRC Computers’ IP on or around October 1, 2015.
`
`50. On October 18, 2017, SRC Labs sued Amazon Web Services, Inc., Amazon.com, Inc.,
`
`and VADATA, Inc. (collectively the “Amazon Defendants”) alleging infringement of five
`
`patents, including the ’311 patent. SRC Labs, LLC v. Amazon Web Services, Inc., No. 1-17-cv-
`
`01227 (E.D. Va.). The complaint (the “Amazon Complaint”) filed in that case (the “Amazon
`
`Case”) alleged that the Amazon Defendants’ products infringed the ’311 patent based on usage
`
`of Xilinx FPGA products.
`
`51. Moreover, specifically, the Amazon Complaint included—as Exhibit J—a publicly-
`
`available claim chart showing how the Amazon Defendants’ product EC2 F1 Instance
`
`infringed the ’311 patent based on its usage of a Xilinx UltraScale+ FPGA. Plaintiff accuses
`
`that device of infringing the ’311 patent in this Second Amended Complaint and accused said
`
`device of infringement in its Original Complaint and First Amended Complaint.
`
`52. On or around January 8, 2018, SRC Labs, LLC served Xilinx with a subpoena in the
`
`Amazon Case. That subpoena explicitly referenced the ’311 patent, providing Xilinx with
`
`further notice of the patent.
`
`53. After learning of the ’311 patent, and that its products infringed that patent, on July 13,
`
`2018 Xilinx filed a petition for inter partes review, requesting that the Board of Patent Trials and
`
`Appeals cancel claims 1 through 5 and 8 through 10 of the ’311 patent. IPR2018-01395
`
`(hereinafter “the Xilinx IPR”), Paper No. 1. In its petition, Xilinx noted the complaint against
`
`the Amazon Defendants and admitted that “Amazon and Xilinx have a customer/supplier
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 10
`
`

`

`relationship” and that “Xilinx Ultrascale+ FPGAs and its Vivado Design Suite are referenced
`
`in the SRC Labs complaint . . .” That petition was denied on January 23, 2019.
`
`IPR201801395, Paper No. 17.
`
`54. The district court case against the Amazon Defendants was transferred to the Western
`
`District of Washington on March 1, 2018. SRC Labs, LLC et al v. Amazon Web Services, Inc., No.
`
`2-18-cv-00317 (W.D. Wa.).
`
`A. Asserted Patent is Owned by SRC.
`
`VI. THE PATENT
`
`55. On January 22, 2020, DirectStream assigned both the ’311 patent to SRC. The
`
`assignment was recorded with the USPTO on January 24, 2020 at Reel/Frame 051615/0344.
`
`56. All maintenance fees have been paid to the USPTO to keep the ’311 patent enforceable
`
`for its full term.
`
`B. Description of the Asserted Patent.
`
`57. The ’311 patent is entitled “System and method for retaining DRAM data when
`
`reprogramming reconfigurable devices with DRAM memory controllers” and issued on
`
`October 6, 2015.
`
`58. A true and correct copy of the ’311 patent is attached as Exhibit A.
`
`59. The ’311 patent is valid and enforceable.
`
`VII. COUNT ONE: DIRECT INFRINGEMENT OF THE ’311 PATENT
`
`60. Plaintiff incorporates by reference all paragraphs above as though set forth herein.
`
`61. Defendant has at no time, either expressly or impliedly, been licensed under the ’311
`
`patent.
`
`62. Defendant has and continues to directly infringe the ’311 patent by making, using,
`
`offering for sale, selling, and/or importing in or into the United States in violation of 35 U.S.C.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 11
`
`

`

`§ 271(a) the Accused Products. For example, on information and belief Defendant tests,
`
`manufactures, and uses each of the Accused Products in an infringing manner at least in order
`
`to (1) ensure that functionality such as that appearing in SRC’s claim charts attached hereto,
`
`including but not limited to those portions of the charts describing partial reconfiguration,
`
`works as described and (2) provide support regarding said reconfiguration to its customers,
`
`members of its Partner Program, such as its Premier Partners, Certified Partners, Alliance
`
`Partners, and Accelerator Partners (see https://www.xilinx.com/alliance.html) and members
`
`of its University Program (see https://www.xilinx.com/support/university.html).
`
`63. Defendant’s direct infringement of the ’311 patent by the Accused Products has caused,
`
`and will continue to cause, substantial and irreparable damage to Plaintiff. Plaintiff is therefore
`
`entitled to an award of damages adequate to compensate for Defendant’s infringement, but not
`
`less than a reasonable royalty, together with pre- and post-judgment interest and costs as fixed
`
`by the Court under 35 U.S.C. § 284.
`
`64. Plaintiff adopts, and incorporates by reference, as if fully stated herein, Exhibits B
`
`through E, which are claim charts that describe and demonstrate how the Accused Products
`
`infringe exemplary claims of the ’311 patent. These charts collectively show that Xilinx
`
`infringes at least claims 1, 3, 9, and 10 of the ’311 patent.
`
`VIII. COUNT TWO: INDIRECT INFRINGEMENT OF THE ’311 PATENT
`
`65. Plaintiff incorporates by reference all paragraphs above as though set forth herein.
`
`66. Defendant induces infringement under 35 U.S.C. § 271(b) by actively and knowingly
`
`aiding and abetting direct infringement by its users.
`
`67. As discussed in § V.B, Defendant received actual and constructive notice of the ’311
`
`patent.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 12
`
`

`

`68. Defendant learned of its infringement of the ’311 patent at least as a result of the filing
`
`of the Original Complaint and the First Amended Complaint in this case as well as the filing of
`
`this Second Amended Complaint.
`
`69. Defendant also learned that its products infringe the ’311 patent as a result of the
`
`Amazon Complaint and/or the Amazon Case.
`
`70. Through at least the filing of the Original Complaint, the First Amended Complaint,
`
`and this Second Amended Complaint, and the claim charts attached to those complaints,
`
`Defendant learned that its actions would result in users of the Accused Products infringing the
`
`’311 patent.
`
`71. For example, the claim charts attached to the complaints show how Defendant’s
`
`UltraScale Architecture-Based FPGA’s Memory IP v1.4 LogiCORE IP Product Guide,
`
`PG150 provides explicit instructions on using the ’311 Accused Products in an infringing
`
`manner, such as through partial reconfiguration.
`
`72. Defendant’s UltraScale Architecture-Based FPGA’s Memory IP v1.4 LogiCORE IP
`
`core described in its UltraScale Architecture-Based FPGA’s Memory IP v1.4 LogiCORE IP
`
`Product Guide, PG150 provides a complete solution for interfacing external DRAM memories
`
`to the user FPGA logic. One component of this Memory IP is a memory controller with a
`
`maintenance block – both are implemented as part of the reconfigurable processor (FPGA).
`
`One of the functions this maintenance block supports is “Self Refresh.” The “Self Refresh”
`
`feature keeps the DRAM in self-refresh mode; for instance, during partial reconfiguration.
`
`73. Moreover, Defendant provides guides such as that described above, as well as training
`
`and support to its customers, members of its Partner Program, such as its Premier Partners,
`
`Certified Partners, Alliance Partners, and Accelerator Partners (see
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 13
`
`

`

`https://www.xilinx.com/alliance.html) and members of its University Program (see
`
`https://www.xilinx.com/support/university.html).
`
`74. Xilinx teaches users to use the Accused Products in an infringing manner, such as that
`
`shown by partial reconfiguration in SRC’s claim charts.
`
`75. Xilinx actively provides support services for its products. An important part of Xilinx’s
`
`support services is the Xilinx Community Portal. See
`
`https://www.xilinx.com/community.html. Xilinx hosts forums where members can ask
`
`questions and receive support both from Xilinx engineers and fellow members.
`
`76. Defendant induces infringement of the ’311 patent by marketing the Accused Products
`
`and providing LogiCORE IP cores, documentation (i.e., the UltraScale Architecture-Based
`
`FPGA’s Memory IP v1.4 LogiCORE IP Product Guide, PG150), training, and support (i.e.
`
`through its Partner Program, and support for non-program members) on how to use said
`
`products in ways that infringe the ’311 patent.
`
`77. For example, Defendant induces infringement by providing Kits that allow users to
`
`develop, simulate, debug, and compile FGPA applications. Defendant actively provides
`
`support services for its Kits, and other products, directly and through its Community Forum, in
`
`which Xilinx engineers provide support to users.
`
`78. Defendant specifically intends for users of its products to infringe and knows that its
`
`acts will result in patent infringement.
`
`IX. COUNT SIX: WILLFUL INFRINGEMENT OF THE ’311 PATENT
`
`79. Plaintiff incorporates by reference all paragraphs above as though set forth herein.
`
`80. Defendant has and continues to willfully infringe the ’311 patent.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 14
`
`

`

`81. As discussed in § V.B herein, Defendant has long had knowledge of the ’311 patent and
`
`that its products infringe that patent.
`
`82. Even if Defendant had not had such knowledge previously, Defendant would learn of
`
`the ’311 patent and its infringement as a result of the filing of Plaintiff’s Original Complaint,
`
`the First Amended Complaint, and this Second Amended Complaint, and this district does not
`
`require pre-suit knowledge to establish willfulness. DermaFocus LLC v. Ulthera, Inc., 201 F.
`
`Supp. 3d 465, 473 (D. Del. 2016).
`
`83. Despite knowing of the ’311 patent, Defendant continued and continues making, using,
`
`offering for sale, and selling the Accused Products resulting in infringement as discussed in
`
`Counts One and Two herein. At least because of its knowledge of the ’311 patent and its
`
`claims, Defendant knew or should have known that its conduct resulted in infringement of
`
`several claims of the ’311 patent. Moreover, Defendant was provided information regarding its
`
`infringement in the Original Complaint, the First Amended Complaint, and this Second
`
`Amended Complaint.
`
`84. Defendant has continued its infringement of the ’311 patent despite its knowing that
`
`claims 1 through 5 and 8 through 10 of the ’311 patent were held valid on January 23, 2019 in
`
`the Xilinx IPR.
`
`85. Therefore, Defendant’s infringement was intentional or knowing. Defendant knows or
`
`should know that its continued activities result in infringement of the ’311 patent.
`
`86. Defendant’s actions have not been consistent with the standards of behavior in its
`
`industry.
`
`87. Defendant made no effort to avoid infringing the ’311 patent.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 15
`
`

`

`88. Defendant’s infringement of the ’311 patent is willful, deliberate, and/or consciously
`
`wrongful, and therefore Plaintiff should receive enhanced damages up to three times the
`
`amount of actual damages for Defendant’s willful infringement under 35 U.S.C. § 284.
`
`X.
`
`CONCLUSION
`
`89. Plaintiff is entitled to recover from Defendant the damages sustained by SRC as a result
`
`of Xilinx’s wrongful acts in an amount subject to proof at trial, which, by law, cannot be less
`
`than a reasonable royalty, together with interest and costs as fixed by this Court.
`
`90. Plaintiff has incurred and will incur attorneys’ fees, costs, and expenses in the
`
`prosecution of this action.
`
`91. Plaintiff reserves the right to amend, supplement, or modify its allegations of
`
`infringement as facts regarding such allegations arise during the course of this case.
`
`XI.
`
`JURY DEMAND
`
`92. Plaintiff hereby demands a trial by jury for all causes of action.
`
`XII. PRAYER FOR RELIEF
`
`Plaintiff requests the following relief:
`
`A. A judgment that Defendant has infringed and continues to infringe the ’311 patent;
`
`B. A judgment and order requiring Defendant to pay Plaintiff damages under 35 U.S.C.
`
`§ 284, including treble damages for willful infringement as provided by 35 U.S.C. § 284, and
`
`supplemental damages for any continuing post-verdict infringement up until entry of the final
`
`judgment with an accounting as needed;
`
`C. A judgment and order requiring Defendant to pay Plaintiff pre-judgment and post-
`
`judgment interest on the damages awarded;
`
`D. A judgment and order awarding a compulsory ongoing royalty; and
`
`E. Such other and further relief as the Court deems just and equitable.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 16
`
`

`

`Dated: March 18, 2021
`
`Respectfully submitted,
`
`/s/ Stamatios Stamoulis
`Stamatios Stamoulis (#4606)
`Richard C. Weinblatt (#5080)
`Two Fox Point Centre
`6 Denny Road, Suite 307
`Wilmington, DE 19809
`Tel: (302) 999-1540
`stamoulis@swdelaw.com
`weinblatt@swdelaw.com
`
`
`
`SHORE CHAN DEPUMPO LLP
`Michael W. Shore* (mshore@shorechan.com)
`Alfonso Garcia Chan* (achan@shorechan.com)
`Ari B. Rafilson* (arafilson@shorechan.com)
`William D. Ellerman* (wellerman@shorechan.com)
`Paul T. Beeler* (pbeeler@shorechan.com)
`
`901 Main Street, Suite 3300
`Dallas, TX 75202
`Tel: (214) 593-9110
`SHORE CHAN DEPUMPO LLP
`901 Main Street, Suite 3300
`Dallas, Texas 75202
`Telephone (214) 593-9110
`Facsimile (214) 593-9111
`
`
`
`Counsel for Plaintiff FG SRC LLC
`
` *
`
` Admitted pro hac vice
`
`
`
`
`
`
`
`
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 17
`
`

`

`
`
`
`
`
`EXHIBIT A
`
`
`
`
`
`
`EXHIBIT A
`
`Patent Owner FG SRC LLC
`
`lPR2021-00633, Ex. 2018, p. 18
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 18
`
`

`

`USOO91533llBl
`
`(12) Umted States Patent
`(10) Patent No.:
`US 9,153,311 B1
`
`Tewalt
`(45) Date of Patent:
`Oct. 6, 2015
`
`(54) SYSTEM AND METHOD FOR RETAINING
`DRAM DATA WHEN REPROGRAMMING
`RECONFIGURABLE DEVICES WITH DRAM
`MEMORY CONTROLLERS
`
`(71) Applicant: SRC Computers, LLC., Colorado
`Springs CO (US)
`’
`.
`Inventor: Tlmothy J. Tewalt, Larkspur, CO (US)
`.
`(73) A551gnee: SRC Computers, LLC, Colorado
`Springs, CO (US)
`
`(72)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U30 1540’) by 0 days
`
`6,941,539 132
`6,961,841 B2
`6,964,029 B2
`6,983,456 B2
`6,996,656 B2
`7,003,593 B2
`7,124,211 B2
`7,134,120 B2
`7,149,867 B2
`7,155,602 B2
`7,155,708 B2
`7,167,976 B2
`7,197,575 B2
`7,225,324 B2
`7,237,091 B2
`7’299’458 B2
`
`9/2005 Hammes
`11/2005 Huppenthal et a1.
`ll/2005 Poznanovic et a1.
`1/2006 Poznanovic et a1.
`2/2006 Burton
`2/2006 Huppenthal et a1.
`10/2006 Dickson et a1.
`11/2006 Hammes
`12/2006 Poznanovic et a1.
`12/2006 Poznanovic
`12/2006 Hammes et a1.
`1/2007 Poznanovic
`3/2007 Huppenthal et a1.
`5/2007 Huppenthal et a1.
`6/2007 Huppenthalet a1.
`11/2007 Hammes
`(Continued)
`OTHER PUBLICATIONS
`
`(21) APPI- N05 14/2883094
`(22)
`Filed:
`May 27, 2014
`
`Allan, Graham, “DDR IP Integration: How to Avoid Landmines in
`this uickl Chan in Landsca 6”, Chi Desi n, Jun/Jul. 2007,
`.
`2043
`y
`g g
`p
`p
`g
`pp
`
`(51)
`
`(2006.01)
`(2006.01)
`
`Int. Cl.
`GIIC 7/00
`GIIC 11/406
`(52) US. Cl.
`CPC ................................ G11 C 11/40615 (2013.01)
`(58) Field of Classification Search
`USPC .......................................................... 365/222
`See application file for complete search history.
`
`(Continued)
`
`Primary Examiner 7 Hoai V Ho
`(74) Attorney, Agent, or Firm 7 Peter J. Meza; William J.
`Kubida; Hogan Lovells US LLP
`
`ABSTRACT
`(57)
`A system and method for retaining dynamic random access
`memory (DRAM) data when reprogramming reconfigurable
`devices with DRAM memory controllers such as field pro-
`grammable gate arrays (FPGAs). The DRAM memory con-
`troller is utilized in concert with an internally or externally
`located data maintenance block wherein the FPGA drives the
`majority of the DRAM input/output (1/0) and the data main-
`tenance block drives the self-refresh command inputs. Even
`though the FPGA reconfigures and the majority ofthe DRAM
`.
`.
`d h d
`.
`bl k
`d
`inputs .are tn-state , t e
`ata malntenance
`oc
`prov1 es
`stable 1nput levels on the self-refresh command inputs.
`
`19 Claims, 2 Drawing Sheets
`
`)
`
`(56
`
`References Cited
`
`U’S' PATENT DOCUMENTS
`6,026,459 A
`2/2000 Huppenthal
`6,076,152 A
`6/2000 Huppenthal et al,
`652475110 B1
`6/2001 HuPpepthal et al.
`6,295,598 B1
`9/2001 Befiom et 31'
`6,339,819 B1
`1/2002 Huppenthal et a1.
`6,356,983 B1
`3/2002 Parks
`6,434,687 B1
`8/2002 Huppenthal
`6,594,736 B1
`7/2003 Parks
`6,836,823 B2
`12/2004 Burton
`
`1021
`
`
`
` DRAM
`
`g
`
`,
`
`11
`
`,5
`
`.1
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`w MHWWW m
`E
`E
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`E
`
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`7
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`2.”;22252»
`1
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`;2 G
`j
`l
`
`
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`
`
`
`“1711:? 1
`'j‘T11212‘:
`Fm,
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`120.3
`Cammnfl
`1
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`T116973
`\ 122
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`114 L
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`Block
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`LS
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`1
`11187
`V
`Q
`
`«
`Reconfigurable Logic Device
`104
`
`Patent Owner FG SRC LLC
`
`|PR2021-00633, Ex. 2018, p. 19
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 19
`
`

`

`US 9,153,311 B1
`Page 2
`
`(56)
`
`References Cited
`
`US. PATENT DOCUMENTS
`
`7,373,440
`7,406,573
`7,421,524
`7,424,552
`7,565,461
`7,620,800
`7,680,968
`7,703,085
`7,890,686
`
`B2
`B2
`B2
`B2
`B2
`B2
`B2
`B2
`B2
`
`5/2008
`7/2008
`9/2008
`9/2008
`7/2009
`11/2009
`3/2010
`4/2010
`2/2011
`
`Huppenthal et al.
`Huppenthal et al.
`Huppenthal et al.
`Burton
`Huppenthal et al.
`Huppenthal et al.
`Burton
`Poznanovic et al.
`Conner
`
`8,589,666 B2
`8,713,518 B2
`2012/0117318 A1
`2013/0157639 A1
`2014/0211579 A1*
`
`11/2013 Hammes
`4/2014 Pointer et a1.
`5/2012 Burton et al.
`6/2013 Huppenthal et al.
`7/2014 Lovelace ...................... 365/200
`
`OTHER PUBLICATIONS
`
`Wilson, Ron, “DRAM Controllers for System Designers”, Altera
`Corporation Articles, 2012, 8 pages.
`
`* cited by examiner
`
`Patent Owner FG SRC LLC
`
`|PR2021-00633, Ex. 2018, p. 20
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 20
`
`

`

`U.S. Patent
`
`Oct. 6, 2015
`
`Sheet 1 of 2
`
`US 9,153,311 B1
`
`DRAM
`
`
`
`w
`
`116 \\
`
`Refresh
`
`3‘
`
`
`
`,
`
`
`
`75‘—
`
`r
`
`Memory Controller
`Glue Logic
`
`
`
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`:RESET#
`
`
`Memory Controller and Physica
`
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`
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`
`ReconfigureRequestAck
`ReconfigureRequest
`WrData
`
`
`
`Data Maintenance
`Block
`
`m
`
`Fig. 1
`
`Config
`Config Done
`Config Date
`
`
`
`
`Primary System Logic
`
`Reconfigurable Logic Device
`
`Patent Owner FG SRC LLC
`
`|PR2021-00633, Ex. 2018, p. 21
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 21
`
`

`

`U.S. Patent
`
`Oct. 6, 2015
`
`Sheet 2 of 2
`
`US 9,153,311 B1
`
`
`
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`Patent Owner FG SRC LLC
`
`|PR2021-00633, Ex. 2018, p. 22
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2018, p. 22
`
`
`

`

`US 9,153,311 B1
`
`1
`SYSTEM AND METHOD FOR RETAINING
`DRAM DATA WHEN REPROGRAMMING
`RECONFIGURABLE DEVICES WITH DRAM
`MEMORY CONTROLLERS
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates, in general, to the field of
`reconfigurable computing systems. More particularly, the
`present invention relates to a system and method for retaining
`dynamic random access memory (DRAM) data when repro-
`gramming reconfigurable devices with DRAM memory con-
`trollers.
`
`The majority of today’s programmable logic designs
`include a DRAM based memory solution at the heart of their
`memory subsystem. Today’s DRAM devices are significantly
`faster than previous generation’s, albeit at the cost of requir-
`ing increasingly complex and resource intensive memory
`controllers. One example is in double data rate 3 and 4 (DDR3
`and DDR4) controllers which require read and write calibra-
`tion logic. This added logic was not necessary when using
`previous versions of DRAM (e.g. DDR and DDR2. As a
`result, companies are for