EXHIBIT B
`EXHIBIT B
`
`Patent Owner FG SRC LLC
`
`lPR2021-00633, Ex. 2010, p. 1
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 1
`
`

`

`FG SRC LLC,
`
`
`Plaintiff,
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`
`
`
`CIVIL ACTION NO. 1:20-CV-00834-ADA
`
`
`
`JURY TRIAL DEMANDED
`
`
`v.
`
`INTEL CORPORATION,
`
`
`Defendant.
`
`
`
`DECLARATION OF RYAN KASTNER, PH.D. IN SUPPORT OF FG SRC LLC’S
`OPENING CLAIM CONSTRUCTION BRIEF
`
`I hereby declare as follows:
`
`1.
`
`I have been asked by counsel for Plaintiff FG SRC LLC (“SRC”) to offer my
`
`opinions regarding claim construction for certain terms.
`
`2.
`
`In connection with the preparation of this Declaration, I have reviewed materials
`
`including the following:
`
`• U.S. Patent No. 7,149,867 (the “’867 patent”);
`
`• The file wrapper for the ’867 patent;
`
`• The parties’ respective claim constructions as set forth in SRC’s Opening Claim
`
`Construction Brief;
`
`• SRC’s Identification of Extrinsic Evidence for Claim Construction and materials cited
`
`therein;
`
`• Defendant Intel Corporation’s (“Intel”) Identification of Extrinsic Evidence for Claim
`
`Construction and materials cited therein; and
`
`• any additional materials cited herein or in SRC’s Opening Claim Construction Brief.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 2
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`

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`3.
`
`All of the opinions stated in this Declaration are based on my personal knowledge
`
`and professional judgment. I am over 18 years old and if called as a witness, I am prepared to
`
`testify competently about them. I declare that all statements made herein are within my knowledge
`
`and believed to be true and correct.
`
`I.
`
`EXPERIENCE AND QUALIFICATIONS
`
`4.
`
`I have over twenty (20) years of experience as a computer scientist and engineer,
`
`specifically in the areas of hardware acceleration, hardware design, and embedded systems. I have
`
`worked extensively on and with FPGAs and other systems for hardware implementation and
`
`acceleration of algorithms.
`
`5.
`
`I am currently a Professor in the Department of Computer Science and Engineering
`
`at the University of California San Diego. I co-direct the Wireless Embedded Systems Graduate
`
`Program, the Engineers for Exploration Program, and lead the Kastner Research group with the
`
`goal of developing accelerated computer systems using FPGAs for applications including
`
`computer vision, bioinformatics, and communication systems.
`
`6.
`
`I completed dual bachelor’s degrees in Electrical Engineering and Computer
`
`Engineering at Northwestern University and went on to receive a master’s degree in engineering
`
`from the same university. Afterward, I received my Ph.D. in Computer Science from the
`
`University of California Los Angeles, with a focus in embedded and reconfigurable systems.
`
`Following my doctoral degree, I became an Assistant Professor at the University of California
`
`Santa Barbara and established a research group to advance hardware research in reconfigurable
`
`computing, hardware security, and underwater sensor networks.
`
`7.
`
`In 2007 I began my current position as a professor at the University of California
`
`San Diego where I have continued my research into hardware acceleration, hardware security, and
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 3
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`

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`embedded systems. Our achievements have included developing systems for automated fish
`
`identification, cell sorting, optical cardiac imaging, fast 3D object reconstruction, and high-speed
`
`genome reconstruction.
`
`8.
`
`In addition to my work at UCSD, I co-founded Tortuga Logic, a hardware security
`
`company, in order to bring developments from my research group to market. The company has
`
`since achieved great success and been awarded contracts with the U.S. Department of Defense
`
`among many other clients.
`
`9.
`
`I am a named inventor on five U.S. patents for inventions relating to hardware
`
`design, security, and computer science generally, with two additional applications in the works.
`
`a. System and Method for Eliminating Common Subexpressions in a Linear
`
`System (with Farzan Fallah and Anup Hosangadi) (USPTO: 7,895,420, Feb.
`
`22, 2011).
`
`b. Designing Digital Processors Using a Flexibility Metric (with Ali Irturk),
`
`(USPTO: 8,812,285, Aug. 19, 2014).
`
`c. Method and Systems for Detecting and Isolating Hardware Timing
`
`Channels (with Jason Oberg, Sarah Meiklejohn, and Timothy Sherwood)
`
`(USPTO:9,305,166, Apr. 5, 2014).
`
`d. Method and System Providing Multi-Level Security to Gate Level
`
`Information Flow (with Jason Oberg, Wei Hu, Timothy Sherwood, and
`
`Mohit Tiwari), (USPTO: 10,083,305, Sep. 25, 2018).
`
`e. Generating Hardware Security Logic (with Jason Oberg, Jonathan
`
`Valamehr, and Timothy Sherwood) (USPTO: 10, 289,873, May 14, 2019).
`
`f. Method and System for Detecting Hardware Trojans and Unintentional
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 4
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`

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`Design Flaws (with Wei Hu and Jason Oberg) (USPTO Application No:
`
`2018/0032760, filed July 207, 2017).
`
`g. Techniques for Improving Security of Circuitry Designs Based on a
`
`Hardware Description Language (with Armaiti Ardenshiricham and Wei
`
`Hu) (USPTO Application No: 2019/0286763, filed Mar. 14, 2019).
`
`10.
`
`I have authored multiple books, including “Parallel Programming for FPGAs”
`
`published by ArXiv e-prints (arXiv: 1805.03648), “Handbook on FPGA Design Security”
`
`published by Springer (ISBN: 9789048191567), “Arithmetic Optimization Techniques for
`
`Hardware and Software Design” published by Cambridge University Press (ISBN:
`
`9780521880992), and “Synthesis Techniques and Optimizations for Reconfigurable Systems”
`
`published by Kluwer Academic Publishers (ISBN: 1402075983). I have authored or co-authored
`
`at least 61 refereed journal papers on numerous topics regarding hardware design, reconfigurable
`
`computing, security, and computer science generally. Additionally, my research group and I have
`
`authored or co-authored at least 158 refereed conference papers on similar topics. I have supervised
`
`doctoral dissertations and master’s theses on a broad range of topics across electrical and computer
`
`engineering, computer science, and data science. I have developed and taught courses regarding
`
`embedded systems, systems programming, hardware design, and robotics, among other topics.
`
`11.
`
`A more complete list of my qualifications and experience is set forth in my
`
`curriculum vitae, a true and correct copy of which is attached hereto as Exhibit 1.
`
`12.
`
`I am being paid for work in this matter. My compensation is in no way dependent
`
`upon the outcome of this litigation nor do I have a personal interest in the outcome of this litigation.
`
`II.
`
`LEVEL OF ORDINARY SKILL IN THE ART
`
`13.
`
`A person of ordinary skill in the art (“POSITA”) at the time of the filing of the ’867
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 5
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`

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`patent would typically have at least an MS Degree in Computer Engineering, Computer Science,
`
`or Electrical Engineering, or equivalent work experience, along with at least three years of
`
`experience related specifically to computer architecture, hardware design, and reconfigurable
`
`processors. In addition, a POSITA would be familiar with hardware description languages and
`
`design tools and methodologies used to program a reconfigurable processor.
`
`III. TECHNOLOGY BACKGROUND
`
`14.
`
`The ‘867 patent relates to the use of reconfigurable processors. One of the more
`
`common types of reconfigurable processors is a Field Programmable Gate Array (FPGA). An
`
`FPGA is an integrated circuit that contains an array of programmable logic blocks and memory
`
`elements connected via programmable interconnect. A user can program an FPGA to perform a
`
`specific function by configuring the logic blocks and interconnect. This enables the user to create
`
`a hardware accelerated implementation of an algorithm by programming the FPGA in a manner
`
`that efficiently executes the algorithm.
`
`15.
`
`Contrast this with implementing the algorithm in software on a CPU or
`
`microprocessor. A CPU executes the algorithm by performing a sequence of instructions (e.g.,
`
`arithmetic, logical, memory (load/store)) that implement the algorithm. A different algorithm can
`
`be implemented on the CPU by changing the instructions. The CPU is flexible; it can implement
`
`almost any algorithm. Because the CPU hardware is fixed, it cannot be customized towards the
`
`algorithm like an FPGA implementation. These customizations allow FPGA implementations to
`
`be orders of magnitude more efficient than implementing that algorithm as software on a CPU.
`
`16.
`
`Application-Specific Integrated Circuits (ASICs) are another option to implement
`
`an algorithm. ASICs use custom logic and are manufactured specifically to perform one
`
`application. Since an ASIC is purpose-built for that one application, it is very efficient -- often
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 6
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`orders of magnitude better than the same application implemented on an FPGA. However, since
`
`the customizations are hard-coded in the IC during manufacturing, an ASIC cannot be repurposed
`
`for another application. FPGAs on the other hand provide a greater deal of flexibility to users and
`
`can be used in any number of applications. Thus, FPGAs provide an attractive middle ground
`
`between CPUs and ASICs.
`
`
`
`17.
`
`An FPGA is configured by providing it with a bitstream. This bitstream is a binary
`
`file that describes how the configurable logic present in the FPGA should be programmed in order
`
`to execute a particular algorithm. Generally, designers specify the algorithm in a hardware
`
`description language and electronic design automation tools generate the bitstream. The tools
`
`synthesize (i.e., compile) the application specification into a bitstream, which can be stored in non-
`
`volatile memory and loaded into the FPGA upon startup. Loading different bitstreams changes the
`
`programmable logic and interconnect on the FPGA to implement a different algorithm.
`
`18.
`
`Computing systems including CPUs, FPGAs, and ASICs typically employ a
`
`memory hierarchy, which combines different types of memories in an attempt to ensure that data
`
`required for computation is immediately available when it is needed. There is a general trade-off
`
`between memory size and bandwidth. In general, larger memories have lower bandwidth, i.e., they
`
`can store a lot of data but the rate at which they can transfer this data (bits/second) is low. Smaller
`
`memories have much higher bandwidth. Thus, memory systems commonly use hierarchies of
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 7
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`progressively faster (higher bandwidth) but smaller memories.
`
`19.
`
`As an example, consider Figure 1.5 as taken from my book “Parallel Programming
`
`for FPGAs.” A true and correct copy of an excerpt from my book is being submitted concurrently
`
`with my Declaration as Exhibit C to Plaintiff’s Opening Claim Construction Brief. It shows that
`
`external memory, e.g., Dynamic Random Access Memory (“DRAM”) may be quite large (several
`
`gigabytes) with a total bandwidth on the order of GBytes/sec. On-chip memories like block RAMs
`
`(BRAMs) provide TBytes/sec of total bandwidth but much less storage capability. And flip-flops
`
`(FFs) have even more bandwidth but lower storage capability. BRAMs and FFs reside on-chip in
`
`FPGAs and are typically used to feed the reconfigurable processors. These would be potential
`
`elements that would be considered a “first memory” as described in the patent.
`
`
`
`20.
`
`Data located in larger external memory has limited bandwidth. This can become
`
`the bottleneck for the computation on the reconfigurable processor in cases where the
`
`computational unit is stalling (not performing any useful execution) while waiting for the data to
`
`be retrieved from the external memory. Instead of accessing the external memory each time data
`
`is needed, portions of the memory that are actively being worked on can be copied to on-chip
`
`memories (e.g., into BRAMs or FFs). On-chip memory bandwidth is significantly faster and thus
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 8
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`can provide substantial overall speedups in executing the algorithm. This general process is
`
`described in the patent as reading from a second memory (e.g., off-chip) to a first (e.g., on-chip)
`
`memory. CPUs, ASICs, and FPGAs are all subject to the performance impact of distant or slow
`
`memory.
`
`21.
`
`The ‘867 patent discusses memory in a number of contexts. Claim 1 mentions a
`
`“first memory” and “second memory” which are members of a memory hierarchy, with the first
`
`memory being faster and closer to the computational unit than the second memory. This is made
`
`evident by its use in the claim, where data is prefetched from the second memory and into the first
`
`memory. As discussed above, this indicates that the second memory is likely larger but has smaller
`
`bandwidth. In Claim 9, the same concept is discussed but instead with respect to a “common
`
`memory” which is shared by multiple processors including the reconfigurable processor.
`
`22.
`
`A simple (unoptimized) memory system would have a processor that requests data
`
`when it is required for computation. This can be problematic especially if the data resides in off-
`
`chip memory, which has a large latency or large number of cycles (e.g., hundreds or more) to
`
`retrieve the data. This requires the computational unit to stall or wait while the data is being loaded.
`
`23.
`
`A more efficient memory system employs techniques to transfer data from slower
`
`memory into the faster memory closer to the processor that requires that data. The patent provides
`
`“[t]wo measures of the gap between the [processor] and memory hierarchy are bandwidth
`
`efficiency and bandwidth utilization.” ’867 patent 1:34-36. The patent further states that
`
`“[b]andwidth efficiency refers to “the percentage of contributory data transferred between two
`
`points. Contributory data is data that actually participates in the recipients processing.” Id. 5:51-
`
`54. It additionally states that “[b]andwidth utilization refers to the amount of memory bandwidth
`
`that is utilized during a calculation. Maximum bandwidth utilization occurs when all available
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 9
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`memory bandwidth is utilized.” Id. 1:39-43. If optimized well, the memory system will provide
`
`the necessary data as required by the processor and dictated by the algorithm. And it will optimize
`
`the bandwidth utilization and/or bandwidth efficiency as it will transfer only the data required by
`
`the algorithm, i.e., it would not transfer data into memory that is never subsequently used for
`
`computation. There are different ways of optimizing a memory system for microprocessors,
`
`including caching and prefetching.
`
`24.
`
`Caching takes advantage of the fact that data requests typically exhibit spatial and
`
`temporal locality. To exploit spatial locality, caching will transfer the currently requested data and
`
`additional data that is stored nearby the requested data. Caches attempt to exploit temporal locality
`
`by keeping that data in on-chip (first) memory even after it is used (in hopes that it will be used
`
`again in the near future). Caching is a common optimization technique for CPUs. Different levels
`
`of cache (L0, L1, L2, …) exist depending on the number of processors and the size of the on-chip
`
`memory.
`
`25.
`
`Reconfigurable processors can use caching, but often they leverage more
`
`customized memory hierarchies and optimizations tailored more towards the algorithm being
`
`executed. The key concepts and ideas in the ‘867 patent relate to algorithm specific memory
`
`optimizations for reconfigurable processors.
`
`26.
`
`Prefetching initiates a request for data before that data is required. In an ideal case,
`
`the prefetch data arrives no later than when it is required. Generally speaking, there are two ways
`
`of prefetching data: 1) dynamically and 2) statically. Dynamic prefetching attempts to guess what
`
`future data is required by looking at past data access requests. For example, a dynamic prefetch
`
`unit may see a request for some data and prefetch the next N data elements located spatially nearby
`
`to the initial data (with the hopes that the algorithm will request this data in the future). Static
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 10
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`prefetching techniques insert explicit prefetch instructions into the computer system, e.g., a
`
`compiler will analyze the algorithm and insert prefetch data fetches before the data is computed
`
`upon. There are many types of prefetching techniques and customizing the prefetching technique
`
`to the algorithm can provide significant overall performance benefits.
`
`27.
`
`The ‘867 patent specifically discusses and claims a data prefetch unit of a
`
`reconfigurable processor. The patent describes the “data prefetch unit” as a specialized functional
`
`unit on a reconfigurable processor that initiates “a data transfer in advance of the requirement for
`
`data by computational logic.” ’867 patent 8:1-2. This data prefetch unit specifically seeks to reduce
`
`the overhead involved in prefetching data by avoiding transferring unnecessary data between
`
`memories, i.e., the prefetch unit copies only the data which are to be used in upcoming
`
`computations. The patent is clear in that the data prefetching unit moves computational data
`
`between two memories in a memory hierarchy. The data prefetch unit “conforms to the needs of
`
`the algorithm” to improve the performance of the reconfigurable processor and the overall
`
`computing system.
`
`IV. CLAIM CONSTRUCTION LEGAL STANDARDS
`
`28.
`
`I am not an attorney. I have been instructed that the following standards apply to
`
`claim construction.
`
`29.
`
`The words of a claim are to be given the plain and customary meaning that a
`
`POSITA would have understood the claim language to have, as of the effective filing date of the
`
`patent application, in light of the claims, specification, and prosecution history. A court should
`
`derive the meaning of a claim term by looking to the claim language, the specification, and the
`
`prosecution history. Claim construction always begins with the language of the claims themselves.
`
`A court may also consider evidence extrinsic to the patent, although such evidence is generally
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 11
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`less significant than the intrinsic record when determining the meaning of the claim language. A
`
`person of ordinary skill may act as his or her own lexicographer and define a term to have a
`
`particular meaning.
`
`30.
`
`There is a heavy presumption that a claim term carries its plain and ordinary
`
`meaning, and that a court need not construe a term, particularly when the plain and ordinary
`
`meaning of the term is sufficient. Instead, claim construction is necessary only when the meaning
`
`or scope of technical terms is unclear.
`
`V.
`
`OPINIONS REGARDING SPECIFIC TERMS
`
`A. “retrieves only computational data required by the algorithm from a second
`memory . . . and places the retrieved computational data in the first memory”
`(claim 1)
`
`31.
`
`The ‘867 patent describes a data prefetch unit which is configured to retrieve the
`
`computational data required by the algorithm from a second memory (e.g., off-chip) and place it
`
`in a first memory (e.g., on-chip). Most of the figures in the patent describe the operation of the
`
`prefetch unit.
`
`32.
`
`Figure 2 depicts a simple block diagram describing how arithmetic operations may
`
`be connected together to carry out a specific computation on input data. The diagram shows “A,”
`
`“B,” and “C” each of which represent the claimed “computational data,” which is provided as
`
`input. After the logic is executed, the results “A+B” and “A+B-(B*C)” are available as outputs in
`
`memories “ST_BANK_D” and “ST_BRAM”, respectively, as shown in Figure 3. Computational
`
`units like the arithmetic logic depicted in this figure operates very quickly, so if the computational
`
`data A, B, and C, were not available at the time that this logic was to be executed, the time incurred
`
`by stalling while the data is retrieved from a second memory could considerably slow the overall
`
`execution time of the algorithm. Arranging to have the data ready before or at the time it is needed
`
`avoids stalling and therefore makes the memory hierarchy more efficient.
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 12
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`33.
`
`One of the key features of the ‘867 patent is that the claimed device avoids
`
`retrieving more data than is actually needed when the data prefetch unit performs this anticipatory
`
`fetching, i.e., it does not perform unnecessary spatial prefetching or caching. A less advanced
`
`device might read an entire section of memory, including spatially adjacent data that is never used
`
`by the computational unit. Such spatial caching is a common optimization in CPU cache memory
`
`hierarchies. If the access patterns are predetermined by the algorithm/application, this spatial
`
`caching is not efficient. It requires a larger local memory to accommodate the extra data, and likely
`
`even more time to complete the movement of that data from the second to first memory. This
`
`invention specifically reads only the data required for computational by the algorithm, and thus
`
`does not read spatially adjacent data that will not be used by the algorithm. Figures 8-14 show
`
`different memory bandwidth gains are achievable by only transferring data required by the
`
`algorithm. Transferring any additional data would have a detrimental effect on both bandwidth
`
`efficiency and bandwidth utilization. The construction proposed by SRC captures this meaning
`
`because it specifically notes that no other computational data should be retrieved.
`
`34.
`
`Intel’s construction suggests that “no other data or instruction” is retrieved, which
`
`seems to exclude not just unnecessary “computational data” as described by the specification but
`
`also any “other data” or “instruction” completely. As discussed, the purpose of the data prefetch
`
`unit is to anticipate the needs of the algorithm. It requires information which configures the
`
`prefetch unit and enable it to identify the data which will be needed by the algorithm that is
`
`currently implemented on the reconfigurable processor. This sort of configuration information
`
`isn’t “computational data” though; rather it is necessary information required for the prefetch unit
`
`to do its job. A comparison might be made to a letter being mailed needing to be put in an envelope
`
`with an address so that a mail carrier knows where to deliver it. The address is not part of the letter
`
`Patent Owner FG SRC LLC
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`but it is necessary information in order to accomplish the goal of sending it.
`
`35.
`
`The patent focuses on how the data prefetch unit would be configured – that is, to
`
`retrieve required data required for computations by the algorithm from the second memory and
`
`nothing more – but does not detail the actual configuration process itself. However, it is clear that
`
`the data prefetch unit would need to be configured in some manner. This may be accomplished by
`
`a number of methods. This configuration information may be generated by the same tools which
`
`generate the bitstream for configuring the reconfigurable processor and stored somewhere in the
`
`memory hierarchy (FFs, BRAMs, or DRAM) depending on its size and the bandwidth
`
`requirements. Or it could be generated using computational units on the reconfigurable processor
`
`itself. In summary, the prefetch configuration information needs to be stored or generated
`
`somehow. One logical design choice would be to place it in a memory, and there is nothing in the
`
`patent in my opinion that states that such information could not be stored in the second memory.
`
`36.
`
`Additionally, Intel’s construction is unclear as to what it means when it says
`
`“instructions.” Conventionally, I think of an “instruction” in the context of a CPU are statements
`
`describing how the CPU should compute (e.g., which operation to perform, what registers to use,
`
`et.). This makes the choice to include the term “instruction” in Intel’s construction unusual since
`
`the ‘867 patent is directed towards reconfigurable processors and not CPUs. The term “instruction”
`
`is not well defined when referring to a reconfigurable processor, e.g., a reconfigurable processor
`
`is not typically thought of to have an Instruction Set Architecture (ISA) like a CPU. Finally, the
`
`term “instruction” is not used in any of the claims of the patent, and thus is unclear especially given
`
`that its plain and ordinary meaning applies to CPUs, but does not have a clear meaning with respect
`
`to reconfigurable processors.
`
`37.
`
`Accordingly, it is my opinion that this term should be construed as proposed by
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 14
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`

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`SRC to mean “retrieves from a second memory that computational data which is required by the
`
`algorithm and no other computational data … and places the retrieved computational data in the
`
`first memory.”
`
`B. “read and write only data required for computations by the algorithm between
`the data prefetch unit and the common memory” (claim 9)
`
`38.
`
`This term differs from the prior term as it recites “data required for computations”
`
`instead of “computational data.” In my opinion “data required for computations” can include both
`
`(1) configuration information required by the data prefetch unit so that it knows what data the
`
`algorithm needs, and (2) data used by the algorithm (i.e. A, B, and C, as shown in Figure 2).
`
`39.
`
`The primary issue in this term mirrors the one described above. In order to
`
`anticipate what data is needed for a computation, it may be necessary for the data prefetch unit to
`
`be supplied with configuration information describing the data required by the algorithm. Intel’s
`
`proposed construction here creates the same potential problem by implying that this sort of
`
`information could not be provided to the data prefetch unit. Additionally, the term “instruction”
`
`does not have a plain and ordinary meaning with respect to a reconfigurable processor.
`
`40.
`
`Accordingly, it is my opinion that this term should be construed as proposed by
`
`SRC to mean “retrieves from a second memory that computational data which is required by the
`
`algorithm and no other computational data … and places the retrieved computational data in the
`
`first memory.”
`
`logic blocks using the
`in parallel with
`independent of and
`C. “operates
`[computational data/computional [sic] data]” (claims 1, 9)
`
`41.
`
`Aside from the obvious typographical error, this term is easily understood by
`
`someone skilled in the art, so it does not need any construction other than a correction for
`
`“computional” to “computational”.
`
`42.
`
`Independent operation is a well-established concept in computing and is important
`
`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 15
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`for parallel computation. Generally, dependencies slow the execution of the algorithm and are
`
`avoided when possible. Dependencies are particularly troublesome for processors that leverage
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`parallel computation as is common in reconfigurable processors. Reconfigurable processors are
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`typically configured to operate in a parallel manner. Exposing parallelism amongst the
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`computational units is a key component of any efficient reconfigurable processor.
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`43.
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`The patent describes a scenario where the logic blocks in the reconfigurable
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`processor are performing computations while the data prefetch unit is independently interacting
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`with the memories to gather computational data that will be needed for subsequent computations
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`carried out by the logic blocks. A dependency between the computational units and the prefetch
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`unit would require these units to synchronize, transfer information, or otherwise communicate
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`between each other. This is clearly not required by the patent.
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`44.
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`The patent states the “independence of operation permits hiding the latency
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`associated with obtaining data for use in computation.” ’867 patent 39-42. A dependency would
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`imply that the logic blocks would be waiting on the data prefetch units in order to perform their
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`operation, and thus the latency would not be “hidden”.
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`45.
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`Intel’s proposed claim states the data prefetch unit “can initiate and carry out its
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`operations each of prior to, in parallel with, or after the requirement for the data input to the
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`computational logic”. This does not properly capture the patent’s description of the data prefetch
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`unit. For example, Intel’s proposed claim allows the data prefetch unit “to initiate after the
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`requirement for the data input”. But this is no longer data prefetching, i.e., this is requesting the
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`data on demand, like a simple (unoptimized) memory system as discussed in the background
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`section (paragraph 22).
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`46.
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`Regarding “computional,” it should be clear enough that what was intended to be
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`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 16
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`said was “computational.” Amusingly, when typing messages my iPhone would actually
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`automatically correct the misspelled word even when I was trying to write it as mistakenly written
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`in the claim, so it makes sense that SRC would want to fix this as well. A true and correct copy of
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`a screenshot I took showing this autocorrection is attached hereto as Exhibit 2.
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`47.
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`Accordingly, it is my opinion that this term should be construed as proposed by
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`SRC. More specifically, the term “computional” in claim 1 means “computational,” but otherwise
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`the term has its plain and ordinary meaning. I also agree with SRC’s alternative construction,
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`“executes a preconfigured operation without intervention of and in parallel with logic blocks using
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`the computational data/computional [sic] data.”
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`I declare under penalty of perjury that the foregoing is true and correct.
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`Executed in San Diego, California
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`11/17/2020____ _
`Date
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`______ _________________________________
`Ryan Kastner, Ph.D.
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`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 17
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`EXHIBIT 1
`EXHIBIT 1
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`Patent Owner FG SRC LLC
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`lPR2021-00633, Ex. 2010, p. 18
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`Patent Owner FG SRC LLC
`IPR2021-00633, Ex. 2010, p. 18
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`Ryan Kastner
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`address: 9500 Gilman Drive
`Department of Computer Science and Engineering
`University of California ¨ San Diego, CA 92093
`phone: 858.534.8908 ¨ fax: 858.534.7029
` webpage: http://kastner.ucsd.edu¨ email : kastner@ucsd.edu
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`Los Angeles, CA
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`Evanston, IL
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`Evanston, IL
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`2007 – present
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`2013 – present
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`2002 – 2007
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`2000 – 2002
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`1998 – 2000
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`Education
`University of California, Los Angeles
`Doctor of Philosophy in Computer Science, September 2002
`Thesis: Synthesis Techniques and Optimizations for Reconfigurable Systems
`Advisor: Professor Majid Sarrafzadeh
`Northwestern University
`Master of Science Degree in Computer Engineering, August 2000
`Thesis: Methods and Algorithms for Coupling Reduction
`Advisor: Professor Majid Sarrafzadeh
`Northwestern University
`Bachelor of Science in Computer Engineering, June 1999
`Bachelor of Science in Electrical Engineering, June 1999
`Experience
`UCSD Department of Computer Science and Engineering
`Full Professor – San Diego, CA
`Tortuga Logic
`Founder – San Diego, CA
`UCSB Department of Electrical and Computer Engineering
`Assistant, Associate Professor – Santa Barbara, CA
`UCLA Computer Science Department
`Research Assistant – Los Angeles, CA
`Northwestern University VLSI CAD Group
`Research Assistant – Evanston, IL
`Honors
`Best Paper Award: Quentin Gautier, Alric Althoff, and Ryan Kastner, “FPGA Architectures for Real-time
`Dense SLAM, IEEE International Conference on Application-specific Systems, Architectures and
`Processors, July 2019
`
`Intel and the Edison Innovation Foundation “Tommy” Award, Antonella Wilby, Ethan Slattery,
`Andrew Hostler, and Ryan Kastner, 2017
`
`Best Paper Nomination: Antonella Wilby, Ethan Slattery, Andrew Hostler, and Ryan Kastner,
`“Autonomous Acoustic Trigger for Distributed Underwater Visual Monitoring Systems”, ACM
`International Conference on Underwater Networks and Systems (WUWNet), October 2016
`
`Honorable Mention for IEEE Micro Top Pick: Xun Li, Vineeth Kashyap, Jason Oberg, Mohit Tiwari,
`Vasanth Rajarathinam