`(12) Patent Application Publication (10) Pub. No.: US 2003/0135766A1
`Zyskowski et al.
`(43) Pub. Date:
`Jul. 17, 2003
`
`US 2003O135766A1
`
`(54) METHOD AND APPARATUS TO CONTROL
`COMPUTER SYSTEM POWER
`(76) Inventors: Paul J. Zyskowski, Chandler, AZ (US);
`Greg E. Scott, Higley, AZ (US)
`Correspondence Address:
`CHARLES A MIHRO INTEL CORPORATION
`BLAKELY SOKOLOFFTAYLOR & ZAFMAN
`LLP
`12400 WILSHIRE BOULEVARD
`7TH FLOOR
`LOS ANGELES, CA 90025
`(*) Notice:
`This is a publication of a continued pros
`ecution application (CPA) filed under 37
`CFR 1.53(d).
`(21) Appl. No.:
`09/453,656
`
`(22) Filed:
`
`Dec. 3, 1999
`Publication Classification
`
`(51) Int. Cl." ....................................................... G06F 1/26
`(52) U.S. Cl. .............................................................. 713/300
`
`(57)
`
`ABSTRACT
`
`A System includes a power Supply adapted to Supply power
`to a device on a peripheral bus at least when the computer
`System is in a reduced power State. The System also includes
`a power control circuit adapted to receive a power control
`Signal from the device at least when the computer System is
`in the reduced power State. The power control circuit tran
`Sitions the computer System from the reduced power State as
`a result of receiving the power control Signal.
`
`
`
`
`
`
`
`
`
`
`
`
`
`PC WWe 2
`Corliko
`2 p.
`
`3/S
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 1 of 8
`
`
`
`Patent Application Publication
`
`Jul. 17, 2003. Sheet 1 of 3
`
`US 2003/0135766A1
`
`(2 St.
`9
`
`F. G.
`
`
`
`
`
`
`
`PROCE Sfo?2
`2 C2
`
`PC WWE 3
`Corliko
`
`(3R (DG
`2 (a
`
`
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 2 of 8
`
`
`
`Patent Application Publication
`
`Jul. 17, 2003. Sheet 2 of 3
`
`US 2003/0135766A1
`
`
`
`- G.
`
`3
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 3 of 8
`
`
`
`Patent Application Publication
`
`Jul. 17, 2003. Sheet 3 of 3
`
`US 2003/0135766A1
`
`Rc2 CA-
`Co Y MAND
`Rec e Veld
`
`to 2
`
`lot
`Powe a M :
`command
`M
`
`O
`1/ A. 6
`
`of 22
`Process. NG
`
`Y
`
`l08
`M
`N
`
`-- O
`
`Asseiz.1
`2 N
`
`---
`
`/412
`N
`22 Nd SEE,
`WYY
`TC2
`&rANP
`
`
`
`M 44
`
`329 a
`2. // A Nd
`
`---
`
`tu A 1 fo R
`dirhill
`
`1.
`4OO
`
`f G, 4
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 4 of 8
`
`
`
`US 2003/0135766 A1
`
`Jul. 17, 2003
`
`METHOD AND APPARATUS TO CONTROL
`COMPUTER SYSTEM POWER
`
`BACKGROUND
`
`0001) 1. Field
`0002 The invention relates to controlling the power state
`of an electronic device, and, more particularly, to controlling
`the power State of a computer System from a device on a bus.
`0003 2. Background Information
`0004. As used herein, a computer system is any device
`comprising a processor to execute instructions and a
`memory to Store the instructions. Computer Systems often
`interface with other devices, called peripheral devices, by
`way of a bus. AS described herein, a bus is one or more
`conductors for Sending and receiving Signals between elec
`tronic circuits, along with protocols associated with Sending
`and receiving the Signals. The buS may be internal or
`external to the physical casing comprising the circuits and
`other components of the computer System. An example of an
`internal bus is the Peripheral Component Interconnect (PCI)
`bus, as described for example in the PCI Local Bus Speci
`fication, Product Version, Revision 2.1, published June
`11995. An example of an external peripheral bus is the
`Universal Serial Bus (USB), as described for example in the
`Universal Serial Bus Specification, Revision 1.0, published
`January 1996.
`0005. In some environments the host device may enter a
`reduced power State in which the host consumes less power
`than in a fully-powered State. In this low power State, power
`consumption by certain components of the computer System
`may be curtailed in order to reduce overall power consump
`tion. For example, a mass Storage device Such as a hard drive
`within the computer System may have power curtailed in the
`reduced power State, in order to reduce overall System power
`consumption. When the host enters a low power State, it may
`also attempt to place devices on internal and external buses
`into a reduced power State as well. For devices on an
`external bus, this may involve the host Sending the devices
`a command or request to enter the reduced power State. This
`command or request may be sent over the external bus.
`Some implementations may even enable a device on an
`internal or external bus to Send a command or request to the
`host, in order to place the host in a reduced power consump
`tion State. For example, USB Supports Such a feature.
`0006 The host may have two sources of power for
`components, a primary power Source and a Standby power
`Source. ESSential components may derive power from the
`Standby power Source. Non-essential components, e.g. com
`ponents to whom power may be discontinued to place the
`host in a reduced power State, may derive power from the
`primary power Source. Placing the host in a reduced power
`consumption State may thus involve cutting off the primary
`power Source. The Standby power Source may remain avail
`able while the host is in the reduced power State. Restoring
`the primary power Source may cause the host to enter the
`fully power State again.
`0007. The host may transition from the reduced power
`consumption State to a fully-powered State (or Some power
`State between the reduced consumption State and the fully
`powered State) when an operation is carried out which
`employs a component to which power has been cut off. For
`
`example, power to the hard drive component may be cut off
`in the reduced consumption State. Power may be restored to
`the hard drive when the host performs an operation which
`employs the hard drive, Such as reading or writing data to a
`hard disk. Such restoration of power may be referred to as
`“waking up' the host. Throughout this document, the term
`“wake up” may be used interchangeably with the term
`“transition' to Signify the transitioning of the host from a
`reduced power State to another State in which the host
`consumes more power than in the reduced power State.
`0008 Abus device may be in a reduced power consump
`tion State when it receives a command which it cannot
`process in the reduced power State. To process the command
`(or Subsequent commands which are expected to follow), the
`device may “wake up” itself and the host to which it is
`coupled via the bus. For example, a bus device operating in
`a reduced power consumption State may receive a “power
`on' command from a remote control unit (much like a
`typical television remote control). The power on command
`may result from a perSon pressing a power toggle button on
`the remote control. The device may receive the power on
`command and transition to a fully-powered State. To process
`Subsequent commands which are expected to follow (for
`example, channel change commands if the device is a media
`player), the device may attempt to communicate with the
`host. However, if the host is operating in a reduced power
`State it may not be possible for the device to communicate
`with the host. Such communication may not be possible
`because, upon entering the reduced power consumption
`State, the host may have disabled transfer of Signals via the
`bus. The host may need to be woken up before signals may
`be exchanged between the device and the host over the bus,
`but the bus cannot be used to wake up the host because it is
`disabled. There therefore exists a continuing need for a
`mechanism whereby a bus device may wake up a host from
`a reduced power consumption State.
`
`SUMMARY
`0009. A system includes a power supply adapted to
`Supply power to a device on a peripheral bus at least when
`the computer System is in a reduced power State. The System
`also includes a power control circuit adapted to receive a
`power control Signal from the device at least when the
`computer System is in the reduced power State. The power
`control circuit transitions the computer System from the
`reduced power State as a result of receiving the power
`control Signal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0010. The subject matter regarded as the invention is
`particularly pointed out and distinctly claimed in the con
`cluding portion of the Specification. The invention, however,
`may be further understood by reference to the following
`detailed description read with reference to the accompany
`ing drawings.
`0011 FIG. 1 shows a block diagram illustrating one
`embodiment of a System in accordance with the present
`invention.
`0012 FIG. 2 shows a block diagram of an embodiment
`of a host computer System in accordance with the present
`invention.
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 5 of 8
`
`
`
`US 2003/0135766 A1
`
`Jul. 17, 2003
`
`0013 FIG. 3 shows an embodiment of device in accor
`dance with the present invention.
`0.014
`FIG. 4 shows an embodiment of a method in
`accordance with the present invention.
`
`DETAILED DESCRIPTION
`0.015 The embodiments described herein are merely
`illustrative, and one skilled in the art will appreciate that
`numerous modifications can be made which nonetheless fall
`within the Scope of the present invention.
`0016. In accordance with one embodiment of the present
`invention, a bus device operates from an independent Source
`of power, or from Standby power Supplied from the com
`puter System. A power control Signal path is established
`between the device and the computer System to enable to
`device to wake the computer System from a reduced power
`State.
`0017 FIG. 1 shows a block diagram illustrating one
`embodiment 100 of a system in accordance with the present
`invention. Host 104 is coupled to a bus device 106 by way
`of a bus 108. In one embodiment, host 104 is a computer
`System which may comprise a personal computer (PC),
`laptop computer, or handheld computer, among many poS
`sibilities. Device 106 may be virtually any electronic device,
`including mass Storage devices (hard drives, compact disk
`drives, digital video disk drives, etc.) and consumer elec
`tronic devices (video cassette recorders, music devices, etc.).
`In one embodiment, bus 108 is compliant with USB signal
`ing protocols and Specifications. USB Specifications typi
`cally specify four signal paths, a ground GRD, a power path
`S, and two data paths D1 and D2. The signal path between
`host 104 and device 106 may also comprise additional
`components not shown So as not to obscure the present
`discussion. For example, the Signal path may comprise
`well-known hub and repeater components.
`0.018. A remote control unit 110 may supply commands
`via infrared, radio, or other wireleSS technology to device
`106. Of course, commands need not be supplied by remote;
`button presses or other input techniques to device 106 may
`also be employed, including automatic and timer-based
`techniques. Device 106 may derive operating power from
`power path S from host 104. Unlike conventional USB
`devices, which may derive power from the primary power
`Source of the host 104, device 106 may derive power from
`the host’s standby power source via power path S. In other
`words, conventional USB implementations may couple
`power path S of bus to the host's primary power source. The
`present invention, however, may couple power path S to the
`hosts standby power source. Thus, even when the host 104
`has entered a reduced power state (in which primary power
`Source is cut off), device 106 may derive operating power
`from the host's Standby power Source.
`0.019
`Signal path Pon provides a path by which device
`106 may signal host 104 to wake host 104 from a reduced
`power state. On USB, device 106 may detect that the host
`104 is in a reduced power state by monitoring the state of
`one or both of the data paths D1 and D2. When the host 104
`is in a full power state, data lines D1 and D2 may be raised
`to a predefined DC voltage level, for example, 5 volts
`(Systems operating at lower Voltages might raise the data
`paths to 3 volts, 2 volts, or even less). When the host 104 is
`
`operating in a reduced power State, the data paths D1 and D2
`may be “floating (an electrical characteristic well known in
`the art) or grounded, or in Some other state wherein the
`predefined DC voltage level is not present on the paths. The
`device 106 may detect the power state of host 104 by
`detecting the presence or absence of the predefined DC
`voltage level on the data paths D1 and D2.
`0020 Device 106 may operate from standby power from
`power path S even when host 104 is in a reduced power
`state. Device 106 may receive commands from remote unit
`110 and may determine that to process the commands, host
`104 should be awakened from a reduced power state. Device
`106 may signal host 104 using signal path Pon to wake up
`the host 104. Once the host 104 is awake, data paths D1 and
`D2 become usable to communicate with host 104, and
`device 106 may use the data paths to request that host 104
`process the command.
`0021
`FIG. 2 shows a block diagram of an embodiment
`200 of a host computer system in accordance with the
`present invention. Embodiment 200 comprises a processor
`202 to execute instructions supplied from a bus 214. The
`executed instructions are stored in a memory 206 from
`which they are supplied to the processor 202 by the memory
`bus 214 for execution. The processor 202 may be imple
`mented using any Semiconductor fabrication technology and
`may execute any instruction Set including, but not limited to,
`instruction sets supported by an Intel Corporation Pentium(R)
`processor or compatible processor. Multiple processors may
`also be present in the system 200. The memory bus 214 may
`be implemented using technologies for propagating Signals
`including, but not limited to, electronic and optical conduc
`tors and may in fact comprise multiple busses. The memory
`206 may include random access memory (RAM), read-only
`memory (ROM), or any other form of memory capable of
`Storing instructions which may then be Supplied to the
`processor 202 by the memory bus 214 for execution. Of
`course, the invention is not limited in Scope to this particular
`embodiment. Computer system 200 may of course include
`other components as well, including a hard drive controller
`210 to control access to a machine-readable Storage medium,
`Such as a hard disk. The hard disk can Store Sequences of
`instructions which may be loaded into memory 206 from
`which they may be supplied to processor 202 for execution.
`The machine-readable Storage medium may include, but is
`not limited to, a hard drive, a floppy drive, and a CD-ROM
`or other optical disk.
`0022. To perform signal input/output, computer System
`200 may comprise an I/O bus 216 bridged to memory bus
`214 by way of a bus bridge circuit 208. I/O bus 216 may be
`implemented using the same general technologies (electri
`cal, optical, etc.) used to implement memory bus 214. Of
`course, other peripheral devices may be coupled to I/O bus
`216 as well. For example, a keyboard and/or a mouse may
`each be coupled to the I/O bus 216.
`0023 Computer system embodiment 200 further com
`prises a power control circuit 204. In this embodiment,
`power control circuit 204 is shown coupled to memory bus
`214, although this may not be essential to practice of the
`present invention. Power control circuit 204 may switch on
`or cut off primary power on Signal path P to other compo
`nents of the system 200 in response to a command from
`processor 202. Doing So places the System in a reduced
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 6 of 8
`
`
`
`US 2003/0135766 A1
`
`Jul. 17, 2003
`
`power consumption State. When in Such a State, Standby
`power of Signal path S is still available to other components
`of the computer system. For example, hard drive 210 is
`supplied by primary power path Pbut not by standby power
`path S. Processor 202, memory 206, and other “essential”
`components of the System are Supplied by Standby power
`path S. ESSential components are those which should receive
`power even in a reduced power consumption State. When
`primary power is cut off, hard drive 210 is not supplied with
`power, but the essential components still receive Standby
`power. Signal path Pon, described in FIG. 1, is coupled to
`power control 204. When device 106 asserts a power control
`Signal on Pon, power control 204 may restore primary power
`on signal path P(assuming, or course, that the System is in
`a reduced power consumption State when the power control
`signal is received). For example, device 106 coupled to the
`peripheral bus 108 may send a power control signal over
`Signal path Pon power control circuit 204. This signal may
`result in power control 204 restoring power on path P.
`Components which are supplied with power from path P.
`such as hard drive 210, may thus have power restored.
`0024 Computer system 200 further comprises a periph
`eral bus controller 212 coupled to I/O bus 216. In one
`embodiment, peripheral bus controller 212 comprises a USB
`controller (USBC). Peripheral bus 108 comprises signal
`paths D1, D2, S, and GND, as described in FIG. 1.
`0025 FIG.3 shows an embodiment 300 of device 106 in
`accordance with the present invention. Embodiment 300
`includes an infrared (IR) sensor 306 to sense infrared
`commands from remote unit 110. Infrared sensor 306 may
`be coupled to infrared receiver 304. Infrared commands
`received by Sensor 306 may be passed as electrical signals
`to receiver 304. Receiver in turn may be coupled to con
`troller 302 and may pass electrical command Signals to
`controller 302. Of course, device 106 need not receive
`commands via infrared. Front panel buttons and radio Sig
`nals are only a few of the other possible means by which
`device 106 could receive commands.
`0.026 Embodiment S may be supplied with power from
`power path S, coupled to Standby power Supply of the host
`104. Power path S may also be coupled to a power supply
`which is independent of host power. In either case, power
`path S supplies power to components of embodiment 300,
`including controller 302 and receiver 304, even when pri
`mary power from host 104 is cut off.
`0027. In response to receiving a power command (rep
`resenting, for example, the press of a power button on
`remote unit 110), controller 302 may attempt to detect
`whether host 106 is in a reduced power consumption state.
`Controller 302 may do so by monitoring the reference DC
`voltage level on one or both of data paths D2 and D1.
`Absence of a predetermined DC voltage level on these data
`paths may indicate that the host 104 is in a reduced power
`consumption State. Device 106 may then attempt to wake up
`the host 104 by Sending a power control Signal on Signal path
`Pon. Power control signal may take the form of raising the
`Voltage level on Pon to a predetermined level, Such as 5
`Volts. Of course, Signal may take other forms as well, Such
`as lowering the Voltage level on Pon or any combination of
`raising and lowering the Voltage.
`0028 FIG. 4 shows an embodiment 400 of a method in
`accordance with the present invention. At 402 a “local”
`
`command is received by the device 106. Herein the term
`“local” refers to commands which are not transmitted over
`the peripheral bus 108, but instead arrive at the device 106
`by other means (such as by infrared, front panel button
`presses, etc.). If at 404 the local command is not a power
`command, other processing not relevant to a discussion of
`the present invention may be performed. If at 404 the local
`command is a power command, a test may be performed at
`408 to determine whether the host 104 is awake. As previ
`ously described, this test may involve monitoring the Volt
`age level of the bus 108 data signal paths D1 and D2. If the
`host 104 is not awake, a signal is asserted on path Pon at 410.
`This signal may result is the host 104"waking up', e.g.
`transitioning from the reduced power consumption State to a
`State in which more components of the computer System are
`provided with power. Upon waking up, the host 104 may
`send a reset command to the device 106. Device 106 may
`wait for this reset command at 414. Upon receiving reset
`command, device 106 may perform a Self-reset, which may
`involve initializing various internal electrical States, or the
`device 106 may ignore the reset command. The device 106
`may then wait for a next local command at 416. If, at 408,
`the host 104 it is determined that the host 104 is awake (in
`a fully powered state), then the device 106 may send a sleep
`command to the host 104 by way of the bus 108. In other
`words, the power command may act as a power toggle for
`the host 104: if the host 104 is in a reduced power state, the
`local power command results in the host 104 waking up into
`a fully powered state; if the host 104 is fully powered, the
`local power command results in the host 104 entering a
`reduced power State.
`0029. Of course, the method embodiment 400 of FIG. 4
`is merely exemplary of possible applications of the present
`invention. Numerous other applications and embodiments
`may be employed which nonetheless fall within the scope of
`the present invention.
`0030. While certain features of the invention have been
`illustrated as described herein, many modifications, Substi
`tutions, changes and equivalents will now occur to those
`skilled in the art. It is, therefore, to be understood that the
`appended claims are intended to cover all Such embodiments
`and changes as fall within the true Spirit of the invention.
`What is claimed is:
`1. A System comprising:
`a power Supply adapted to Supply power to a device on a
`peripheral bus at least when the computer System is in
`a reduced power State; and
`a power control circuit adapted to receive a power control
`Signal from the device at least when the computer
`System is in the reduced power State, the power control
`circuit to transition the computer System from the
`reduced power State as a result of receiving the power
`control Signal.
`2. The system of claim 1 in which the bus is adapted to
`Support Signals which comply with a Universal Serial Bus
`Specification.
`3. A System comprising:
`a first circuit to Supply primary power to a first Set of
`components of the computer System;
`a Second circuit to provide Standby power to a Second Set
`of components of the computer System;
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 7 of 8
`
`
`
`US 2003/0135766 A1
`
`Jul. 17, 2003
`
`a peripheral bus controller to Send and receive data from
`a peripheral bus, the peripheral bus coupled to Standby
`power; and
`a power control circuit adapted to Supply primary power
`to the first Set of components of the computer System as
`a result of receiving a power control signal from a
`device coupled to the peripheral bus.
`4. The computer system of claim 3 in which the peripheral
`bus comprises a data Signal path, the power control circuit
`coupled to a power Signal path, the power Signal path
`Separate from the data Signal path and a power path to the
`Standby power.
`5. The computer system of claim 3 in which the peripheral
`bus is adapted to comply with a Universal Serial Bus
`Specification.
`6. A device comprising:
`an interface to a computer System to provide power to the
`device;
`a control circuit adapted to provide a signal to the com
`puter System by way of the interface, the Signal to
`transition the computer System from a reduced power
`State.
`7. The device of claim 6 in which the interface is adapted
`to couple to a Standby power Source of the computer System.
`8. The device of claim 6 in which the device further
`comprises:
`a remote Sensor to detect a remote command which results
`in the Signal.
`9. A method comprising:
`providing power to a device coupled to a peripheral bus
`of a computer System at least when the computer
`System is in a reduced power consumption State; and
`
`responsive to a command received from the device,
`transitioning the computer System from the reduced
`power consumption State.
`10. The method of claim 9 further comprising:
`Signaling the device in a manner compatible with a
`Universal Serial Bus specification.
`11. A method comprising:
`deriving power from a computer System by way of a
`peripheral bus at least when the computer System is in
`a reduced power consumption State; and
`providing a signal to the computer by way of the periph
`eral bus which results in the computer System transi
`tioning from the reduced power consumption State.
`12. The method of claim 11 further comprising:
`providing the Signal in response to a remote command.
`13. A System comprising:
`a computer System; and
`a device coupled to the computer System by way of a
`peripheral bus,
`wherein the computer System is adapted to provide power
`to the device at least while in a reduced power con
`Sumption State and to transition from the reduced power
`consumption State as a result of receiving a signal from
`the device.
`14. The system of claim 13 in which the peripheral bus is
`adapted to Support Signals compatible with a Universal
`Serial Bus specification.
`15. The system of claim 13 in which the device is coupled
`to a Standby power Source of the computer System.
`
`k
`
`k
`
`k
`
`k
`
`k
`
`Petitioners Ex. 1012
`IPR USP 7,834,586
`Page 8 of 8
`
`