(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2003/0095087 A1
`Libsch et al.
`(43) Pub. Date:
`May 22, 2003
`
`US 2003009.5087A1
`
`(54) DATA VOLTAGE CURRENT DRIVE
`AMOLED PXEL CIRCUIT
`
`(75) Inventors: Frank R. Libsch, White Plains, NY
`(US); James L. Sanford, Hopewell
`Junction, NY (US)
`
`Correspondence Address:
`Paul D. Greeley, Esq.
`Ohlandt, Greeley, Ruggiero & Perle, L.L.P.
`10th Floor
`One Landmark Square
`Stamford, CT 06901-2682 (US)
`(73) Assignee: International Business Machines Cor-
`poration
`(21) Appl. No.:
`10/287,937
`
`(22) Filed:
`
`Nov. 5, 2002
`
`
`
`Related U.S. Application Data
`(60) Provisional application No. 60/331,913, filed on Nov.
`20, 2001.
`Publication Classification
`
`(51) Int. Cl. .................................................. G09G 3/32
`(52) U.S. Cl. ................................................................ 345/82
`
`(57)
`
`ABSTRACT
`
`There is provided a circuit for driving an organic light
`emitting diode (OLED). The circuit includes a current
`Source for providing current to a first terminal of the OLED,
`and a generator for providing a variable Voltage Signal to a
`Second terminal of the OLED to facilitate control of the
`Current.
`
`Petitioner Samsung Ex. 1007 - Page 1 of 11
`
`

`

`Patent Application Publication May 22, 2003. Sheet 1 of 4
`
`US 2003/009,5087 A1
`
`
`
`FIG. 1
`
`Petitioner Samsung Ex. 1007 - Page 2 of 11
`
`

`

`Patent Application Publication May 22, 2003 Sheet 2 of 4
`
`US 2003/009,5087 A1
`
`frame time (16.66ms)
`
`Write data
`
`Data
`
`expose
`
`.
`:
`
`preset
`-> <- ti
`-> <- t2
`-G: C-t3
`:
`;
`:
`V
`Es data(max)
`:::: Vdata(min)-OV
`
`
`
`Volled
`
`:::
`OLED
`Luminance -
`Vgd
`
`
`
`VSd
`
`FIG. 2
`
`Petitioner Samsung Ex. 1007 - Page 3 of 11
`
`

`

`Patent Application Publication May 22, 2003. Sheet 3 of 4
`
`US 2003/009,5087 A1
`
`
`
`FIG.3
`
`Petitioner Samsung Ex. 1007 - Page 4 of 11
`
`

`

`Patent Application Publication May 22, 2003 Sheet 4 of 4
`
`US 2003/0095087 A1
`
`<
`frame time (16.66ms)
`< write data
`>< CXPOSC
`s preset
`.
`-> <- ti
`:
`-> <-
`tek
`
`.
`
`Vda
`ta(max)
`
`>
`
`Data
`
`GLO
`
`GL1
`
`Vca
`
`Vc
`
`Voled
`
`
`
`
`
`VSC
`
`FIG. 4
`
`Petitioner Samsung Ex. 1007 - Page 5 of 11
`
`

`

`US 2003/0095087 A1
`
`May 22, 2003
`
`DATA VOLTAGE CURRENT DRIVE AMOLED
`PXEL CIRCUIT
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`0001. The present application is claiming priority of U.S.
`Provisional Patent Application Serial No. 60/331,913, filed
`on Nov. 20, 2001.
`
`BACKGROUND OF THE INVENTION
`0002) 1. Field of the Invention
`0003. The present invention relates to a pixel circuit, and
`more particularly, to a data Voltage current-drive OLED
`pixel circuit. The circuit establishes a threshold Voltage of a
`current drive transistor operating in Saturation acroSS a
`Storage capacitor. Thereafter, the circuit writes a data Voltage
`into the Storage capacitor for controlling current through the
`OLED.
`0004 2. Description of the Prior Art
`0005 One method to achieve large size OLED (organic
`light emitting diode) displays is to use an active matrix thin
`film transistor (TFT) backplane. An active matrix consists of
`an array of rows and columns of pixels each having an active
`device such as a transistor. Row lines driven by row drivers
`are Sequentially Selected, one row line at a time, from top to
`bottom, while data for a Selected row is presented on data
`lines or column lines by data or column drivers. The Selected
`row turns on a pixel transistor that connects the data,
`typically in the form of a Voltage, to a pixel circuit. The row
`lines are connected to gates of the pixel transistors and are
`often referred to as gatelines. Typically, pixel Storage capaci
`tors are used to Store the data Voltage. Leakage currents
`require that the pixel voltages be refreshed or updated. The
`refresh or frame rate for driving OLEDs is typically 60 Hz.
`The maximum time available for writing data into each row
`is tiffn where t? is frame time and n is the number of rows in
`the display.
`0006 Some manufacturers are using amorphous silicon
`(a-si), as opposed to polysilicon (p-si), to make active matrix
`OLED displays. In order to achieve sufficient luminance
`uniformity, OLED pixels are driven with current and not
`Voltage. Amorphous Silicon does not have complimentary
`devices as do polysilicon or crystalline Silicon devices. Only
`n-type field effect transistors (NFETs) are available in amor
`phous silicon. Due to the manner in which the OLEDs are
`usually fabricated, i.e., having a common cathode for all
`pixels in the display, it is not normally possible to drive the
`OLEDs with a current source comprised of NFETs.
`0007. In typical active matrix addressing, voltage signals
`are written into each pixel to control the pixel luminance.
`The mobility and stability of amorphous silicon is suitable
`for driving twisted nematic liquid crystal, which is electri
`cally similar to a Small capacitive load and with which a data
`voltage is applied with a duty cycle in the range of 0.001%
`to 1%. However, for driving OLEDs requiring nearly con
`tinuous current for operation, the amorphous Silicon oper
`ating Voltages are non-Zero for a Substantially larger per
`centage of the time (duty cycles up to 100%). The higher
`voltage-time multiplier severely stresses the TFT. In par
`ticular, a gate to Source Voltage StreSS causes a threshold
`Voltage to vary due to trapped charge at a Semiconductor
`
`(a-si or p-si) gate insulator interface or in the gate insulator,
`and other effects Such as creation of defect States and
`molecular bond breakage at the gate insulator-to-Semicon
`ductor interface and in a semiconductor layer. As the TFT's
`threshold voltage varies, current though the TFT will varies.
`As the current varies so does the OLED brightness since the
`OLED light output is proportional to current. A typical
`human observer can detect a pixel to pixel light output
`variation of as little as 1%, however, a level of 5% lumi
`nance variation is typically considered as being unaccept
`able. AC voltages on TFT terminals tend to minimize effects
`of trapped charge and can prolong TFT lifetimes.
`0008 IBM Corporation, the assignee of the present appli
`cation, has considered a-Si TFT OLED current drive pixel
`circuit having three transistor pixel circuits that use current
`to write the pixel OLED current. The pixel circuits elimi
`nated any dependence of threshold voltage on the OLED
`current. The pixel current can Sink or Source current to the
`OLED.
`0009 Since current is either sourced into or sunk out of
`the data or column line, the pixel circuits previously dis
`closed may not be Suitable for high format displayS. AS the
`display format increases, the number of rows increase, thus
`increasing column line capacitance. To obtain a wide range
`of grey levels, the pixel current will need to vary between
`two and three orders of magnitude. The lower pixel currents
`may not be able to charge the column line in a line time due
`to the large capacitance. Higher level currents can be written
`and for a given luminance the OLED on time can be
`reduced proportionately. However, the higher currents
`require higher Voltage, and thus cause higher StreSS on the
`TFT. The higher currents also increase power Supply Voltage
`drops and current return voltage drops. At Some point with
`increasing display format, this approach may not be practi
`cal. In addition, current Source or Sink drivers for active
`matrix organic light emitting diodes (AMOLEDs) are not
`presently commercially available.
`0010) A problem is that although voltage data drivers are
`readily available, there are no amorphous Silicon pixel
`circuits that can convert the Voltage data to current for
`driving an OLED having a common cathode, without a
`threshold Voltage dependence.
`0011 Prior inventors, for example, see U.S. Pat. No.
`5,552,678 to Tang et al., have attempted to solve problems
`of OLED degradation. When a constant Voltage is applied,
`progressively lower current densities result. Lower current
`densities result in lower levels of light output with a constant
`applied Voltage. Tang et al. incorporates an AC drive Scheme
`of OLEDS, and claims that by applying an alternating
`Voltage across the anode and cathode improves the Stability
`and operating performance of the OLED.
`0012. A threshold voltage compensated current source
`pixel circuit using voltage data and polysilicon PMOS
`transistors has been described by R. M. A. Dawson et al.,
`“The Impact of the Transient Response of Organic Light
`Emitting Diodes on the Design of Active Matrix OLED
`Displays", IEDM, p875-878, 1998. The circuit incorporates
`4 PMOS transistors and two storage capacitors. The circuit
`requires custom designed row drivers and the circuit does
`not appear to be Suited for high-resolution displayS.
`0013 A current writing amorphous silicon pixel circuit
`has been described by Yi He, et al., “Current Source a-Si:H
`
`Petitioner Samsung Ex. 1007 - Page 6 of 11
`
`

`

`US 2003/0095087 A1
`
`May 22, 2003
`
`Thin-Film Transistor Circuit for Active Matrix Organic
`Light-Emitting Displays”, IEEE Electron Device Letters,
`Vol. 21, No. 12, p590–592, December 2000. The circuit
`incorporates four transistors and a storage capacitor. The
`circuit requires custom design current data line drivers and
`the circuit dissipates a Substantial amount of power as it
`incorporates two transistors in Series to Source current.
`SUMMARY OF THE INVENTION
`0.014. The present invention provides a circuit for driving
`a pixel of an active matrix OLED display. The circuit is
`implemented with relatively few TFTs, a minimal number of
`capacitors, and a minimal number of control lines. Such a
`circuit (1) minimizes an initial TFT threshold voltage shift,
`especially in a current drive TFT, (2) minimizes stress effects
`of the TFTs, especially the current drive TFT, that result in
`a time dependent threshold voltage shift, (3) has a data
`voltage write to the pixel, and (4) has a threshold voltage
`independent Voltage-to-current conversion, followed by
`pixel illumination.
`0.015 The circuit is compatible with voltage amplitude
`modulated data drivers and pulse width modulated drivers.
`Another aspect of the circuit is that it reverses or provides
`AC voltages on TFT terminals to prolong TFT operation. An
`additional aspect of the present invention is that it provides
`an OLED architecture that facilitates a reverse bias of a
`scanned OLED array. Since OLEDs are thin film devices,
`charge can build up when driven normally in a forward bias
`manner. Reversing the Voltage acroSS the OLED removes
`built up charge and helps to maintain low voltage operation.
`0016. An embodiment of the present invention is a circuit
`for driving an OLED. The circuit includes a current source
`for providing current to a first terminal of the OLED, and a
`generator for providing a variable Voltage Signal to a Second
`terminal of the OLED to facilitate control of the current.
`0.017. Another embodiment of the present invention is a
`circuit for driving an OLED, where the circuit includes (a)
`a current drive transistor for providing current to a first
`terminal of the OLED, (b) a capacitor for Storing a preset
`Voltage and a data Voltage, to control the current drive
`transistor, wherein the capacitor is connected to the first
`terminal, (c) a data transistor for adding the data voltage
`onto the capacitor, and (d) a generator for providing a
`variable voltage signal to a second terminal of the OLED to
`facilitate the control of the current drive transistor.
`0.018. Because of the OLED impedance characteristics,
`prior art active matrix OLED pixel circuits, which store data
`in a capacitance, attempt to isolate the data Storage capaci
`tance from the OLED. In addition, no previous pixel circuit
`or driving methods apply a multilevel Voltage Signal to a
`terminal of an OLED.
`BRIEF DESCRIPTION OF THE DRAWINGS
`0.019
`FIG. 1 is a schematic diagram of a voltage data
`current drive AMOLED pixel circuit in accordance with the
`present invention.
`FIG. 2 is a timing diagram for the pixel circuit of
`0020
`FIG. 1.
`FIG. 3 is a schematic diagram of a voltage data
`0021
`current drive AMOLED pixel circuit using the previous gate
`or row line for presetting.
`0022 FIG. 4 is a timing diagram of the circuit of FIG.3.
`
`DESCRIPTION OF THE INVENTION
`0023. An embodiment of the present invention is a circuit
`for driving an OLED. In a frame time, there is a preset time
`interval, a write data time interval and an expose time
`interval. During the preset time interval, the circuit Sets a
`preset Voltage on a Storage capacitor. The preset Voltage is
`a threshold Voltage of a current drive transistor that provides
`current to the OLED. During the write data time interval,
`data in the form of a data Voltage is added to the preset
`Voltage on the Storage capacitor. During the expose time
`interval, the current provided by the current drive transistor
`is dependent only on the data Voltage on the Storage capaci
`tor, and it is independent of threshold Voltage of the current
`drive transistor.
`0024 FIG. 1 is a schematic diagram of an embodiment
`of circuit 100 for driving an OLED 105 in accordance with
`the present invention. Circuit 100 employs a method that
`includes providing a current to the anode of OLED 105, and
`applying a variable Voltage Signal to the cathode of OLED
`105 to facilitate control of the current. Such facilitation of
`current control includes applying a voltage to the cathode of
`OLED 105 to turn off OLED 105, applying a voltage to the
`cathode of OLED 105 to set a drive current for OLED 105,
`and applying a voltage to the cathode of OLED 105 to allow
`luminance of OLED 105.
`0025) Circuit 100 includes NMOS transistors 101, 102
`and 103, a storage capacitor 104, which operate collectively
`as a current Source for providing a current to the anode of
`OLED 105. Circuit 100 has a data or column line 110 into
`which a data Signal is input, a preset input 115 for a preset
`Signal, and a gate (GL) 130 input for a gate line signal.
`Circuit 100 also includes a generator 140 for providing a
`variable voltage Signal, i.e., cathode Voltage (Vca) 120, to
`the cathode of OLED 105 to facilitate control of the drive
`Current.
`0026 Cathode voltage (Vca) 120 may also be regarded as
`a multilevel Voltage Signal. That is, generator 140 can Set
`cathode voltage (Vca) 120 to any one of a plurality of
`discrete Voltage levels.
`0027 NMOS transistor 101 functions as a data voltage
`sampling transistor. When NMOS transistor 101 is on it
`provides a path for data in the form of a Voltage from data
`line 110 to node 107.
`0028 NMOS transistor 102 functions as a data voltage
`reference-switching transistor. The source of NMOS tran
`Sistor 102 is connected to node 107. When NMOS transistor
`102 is on, it provides a path for a voltage from its drain to
`its Source. In the embodiment shown in FIG. 1, the data
`Voltage reference is circuit ground.
`0029 NMOS transistor 103 functions as an OLED cur
`rent drive transistor. NMOS transistor 103 converts the
`voltage on storage capacitor 104 to a drive current for OLED
`105.
`0030 Storage capacitor 104 is large (~500 nF) compared
`to a parasitic capacitance of NMOS transistors 101, 102 and
`103 (-50 nF), but small when compared to a capacitance
`(-10 pF) of OLED 105. The capacitance of OLED 105 is
`represented by an OLED capacitance 106 drawn in dashed
`lines.
`
`Petitioner Samsung Ex. 1007 - Page 7 of 11
`
`

`

`US 2003/0095087 A1
`
`May 22, 2003
`
`Although storage capacitor 104 is represented as a
`0.031
`discrete component, it may be implemented as a capacitance
`characteristic of an element of circuit 100 that is not nec
`essarily a discrete capacitor. For example, Storage capacitor
`104 may implemented as a gate to Source capacitance of
`NMOS transistor 103, or as a capacitance formed by an
`overlap of circuit nodes, e.g., circuit nodes 107 and 125.
`0.032
`Circuit 100 is one of a plurality of such circuits
`configured in a pixel array to provide an image on a display.
`Preset input 115 may be common to all pixels in the array.
`Cathode voltage (Vca) 120 may also be common to all pixel
`circuits in the array.
`0.033
`FIG. 2 is a timing diagram for the pixel circuit of
`FIG.1. Images on a display are typically updated Sixty times
`a Second. A time period from one image update to a next is
`called a frame time. In FIG. 2, the frame time is shown as
`16.66 milliseconds. The frame time is broken up into 3 time
`periods, namely a preset time period, a write date time
`period and an expose time period. The preset time period is
`composed of three Smaller time periods, namely t1, t2 and
`t3.
`0034 Presetting is a drive technique that establishes a
`preset Voltage, acroSS a Storage capacitor, for an OLED
`current drive transistor while the OLED is off. The preset
`Voltage level is controlled to be the same as a threshold
`voltage level of the current drive transistor. An OLED is off
`when the OLED's anode to cathode voltage is the voltage for
`onset of luminance or exponential current conduction. The
`onset voltage is typically 2 V. When the OLED is off, the
`OLED's capacitance dominates the OLED's impedance.
`The Storage capacitor is connected acroSS gate and Source
`terminals of the OLED current drive transistor. As a thresh
`old Voltage is established acroSS the Storage capacitor, the
`positive terminal of the Storage capacitor is referenced to
`ground. When writing a positive data Voltage onto the
`positive terminal of the Storage capacitor, the OLED capaci
`tance maintains the negative terminal Voltage of the Storage
`capacitor. Cathode voltage of the OLED is subsequently
`changed to allow the OLED to emit light in accordance with
`the stored data voltage. An OLED drive current from the
`OLED current drive transistor is proportional to Vdata'
`where Vdata is a written positive data Voltage.
`0.035
`Referring again to FIG. 1, a preset voltage is
`applied to Storage capacitor 104 during a preset time period.
`The preset voltage is a threshold voltage of NMOS transistor
`103. During a write time period, a data Voltage is added to
`the preset Voltage on Storage capacitor 104. During an
`expose time period, a current through OLED 105, which is
`also the current through NMOS transistor 103, is propor
`tional to (Vdata), where Vdata is the data voltage stored on
`Storage capacitor 104. During the expose time period,
`NMOS transistor 103 operates in Saturation. The current
`through NMOS transistor 103 is ~(Vgs-Vt) where Vgs is
`the gate to source voltage of NMOS transistor 103 and Vt is
`a threshold voltage of NMOS transistor 103. The data
`voltage is written onto circuit node 107, i.e., the positive
`Voltage terminal of Storage capacitor 104. OLED capaci
`tance 106 maintains the Voltage at a circuit node 125, i.e., at
`the anode of OLED 105, which is also the negative terminal
`of Storage capacitor 104, while the data Voltage is written.
`Thus, by maintaining the voltage at circuit node 125, OLED
`capacitance 106 allows the data voltage to be added to the
`preset Voltage during the write data time interval.
`
`0036 With amorphous silicon thin film transistors, a
`threshold voltage of NMOS transistor 103 may initially be
`~2.5V. However, after being electrically stressed, the thresh
`old voltage of NMOS transistor 103 may increase to ~10V.
`Circuit 100 can accommodate such a change in threshold
`Voltage.
`0037. The cathode of OLED 105 is connected to genera
`tor 140 and its anode is connected to circuit node 125. OLED
`layers are deposited over the entire array of pixels, where
`each pixel has an anode contact. The OLED cathode is
`formed by depositing a conducting metal, often transparent,
`such as indium tin oxide, over the OLED layers. An elec
`trical connection is made to a common cathode outside the
`array.
`0038. The presetting of storage capacitor 104 between
`circuit nodes 107 and 125 is achieved by operations of preset
`input 115 and generator 140, which sets cathode voltage
`(Vca) 120 through a sequence of Voltage levels.
`0039) Referring to FIG. 2, the threshold voltage of
`NMOS transistor is preset on storage capacitor 104 during
`the preset time period. Just after applying power to pixel
`circuit 100, the voltage across storage capacitor 104 and
`OLED 105 may be OV. Recall that the preset time period is
`composed of time periods t1, t2 and t3, and that cathode
`voltage (Vca) 120 is a multilevel voltage signal.
`0040 Time period t1 occurs just after applying power to
`pixel circuit 100. Time period t1 occurs at the beginning of
`a first occurrence of a frame time, but it is not required for
`Subsequent frames. In time period t1, preset input 115 is Set
`high (i.e., to 1) turning on NMOS transistor 102 while
`generator 140 sets cathode voltage (Vca) 120 to V1. V1 is
`a voltage more negative than -1.05*Vt 103(max), where
`Vt103(max) is a maximum end of life threshold voltage of
`NMOS 103. Since OLED capacitance 106 is -20x larger
`than the capacitance of Storage capacitor 104, a Voltage V5
`is developed across storage capacitor 104. V5 is
`-Vt103(max).
`0041. In time period t2, preset input 115 is set low (i.e.,
`to 0) turning off NMOS transistor 102, and generator 140
`sets cathode voltage (Vca) 120 to V2. OLED 105 is thus
`turned off, and its impedance appears as a capacitance. V2
`is a voltage greater than Vt103(max)-Vt103(min)-Vole
`d(onset), where Vt103(min) is the minimum threshold volt
`age for NMOS transistor 103 and where Voled(onset) is the
`OLED Voltage for onset of light emission and exponential
`increase in current. The gate voltage of NMOS transistor
`103 with respect to ground is high which turns NMOS
`transistor 103 on. After a period of time, the voltage of
`circuit node 125 is at ground, putting a Voltage V8 acroSS
`OLED 105. V8 is a voltage less than or more negative than
`+Vt103(min)-Vt103(max)+Voled(onset).
`0042. In time period t3, preset input 115 is set high while
`generator 140 sets cathode voltage (Vca) 120 to V3. V3, in
`cooperation with the preset Voltage, establishes a Voltage on
`storage capacitor 104 that is a threshold voltage of NMOS
`transistor 103. V3 is a voltage more positive than
`-Vt103(min)-Voled(onset). NMOS transistor 103 dis
`charges storage capacitor 104 and OLED capacitance 106
`until the Voltage acroSS Storage capacitor 104 is V6, which
`is the threshold voltage of NMOS transistor 103, i.e., a
`voltage between Vt103(min) and Vt103(max). The voltage
`
`Petitioner Samsung Ex. 1007 - Page 8 of 11
`
`

`

`US 2003/0095087 A1
`
`May 22, 2003
`
`across OLED 105 is less than V9, or V6-V3, or Voled(on
`set)+Vt103(min)-Vt103. At the end of time period t3, preset
`input 115 is set low turning off NMOS transistor 102.
`0043. At the beginning of the write data time period,
`circuit node 107 is OV. Cathode voltage (Vca) of V3 enables
`the addition of the data Voltage to Storage capacitor 104.
`Because OLED capacitance 106 is substantially greater than
`Storage capacitor 104, the Voltage at circuit node 125 is
`maintained by OLED capacitance 106. Thus OLED capaci
`tance 106 facilitates the Sorting of the preset Voltage and the
`data Voltage on Storage capacitor 104. Data Voltage from
`data line 110 is written to circuit 100 when gate line 130 is
`brought high. Data line 110 Voltage is in a range between
`Vdata(min) and Vdata(max). For example, Vdata(min) may
`be OV and Vdata(max) may be 10V. Since OLED capaci
`tance 106 is not infinitely large, the data Voltage acroSS
`storage capacitor 104 will be decreased by ~5%. The voltage
`across storage capacitor 104 is V7 or 0.95*Vdata-Vt103.
`The voltage of OLED capacitance 106 increases slightly by
`0.05*Vdata.
`0044) At the beginning of the expose time period, gen
`erator 140 sets cathode voltage (Vca) 120 to V4. V4 allows
`OLED 105 to illuminate as a function of the data voltage that
`was added onto Storage capacitor 104. V4 is a Voltage more
`negative than-Vt103(max)-Voled(max), where Voled(max)
`is maximum voltage across OLED 105 when producing
`maximum luminance. NMOS transistor 103 operates in its
`Saturation current regime, Vds>VgS-Vt. The current flowing
`through NMOS transistor 103 and OLED 105 will be
`proportional to (0.95*Vdata+Vt-Vt) or proportional to
`(Vdata). Thus, a data voltage to current transfer function is
`threshold voltage independent. The voltage across OLED
`105 is V10. V10 is equal to or greater than Voled(onset) and
`depends upon current through NMOS transistor 103. The
`luminance of OLED 103 is L1. L1 is proportional to current
`through NMOS transistor 103.
`004.5
`FIG. 3 is a schematic diagram of another embodi
`ment of a pixel circuit in accordance with the present
`invention. FIG. 3 shows a circuit 300, i.e., a voltage data
`current drive AMOLED pixel circuit, that is similar to circuit
`100 of FIG. 1 in that circuit 300 includes NMOS transistors
`101, 102 and 103, storage capacitor 104, data line 110,
`OLED 105, generator 140 and circuit nodes 107 and 125,
`and is one of a plurality of Such circuits configured in a pixel
`array to provide an image on a display.
`0046) In contrast with circuit 100, circuit 300 has two
`gateline inputs, namely GLO and GL1. Presetting of circuit
`300 is controlled by a signal that is applied to gateline GL0
`from a previous row, adjacent pixel circuit (not shown).
`Thus, GL0 is also referred to as a previous gate line. GLO
`controls the Storage of the preset Voltage onto Storage
`capacitor 140. GL1 controls the writing of the data voltage
`onto Storage capacitor 140 and is referred to as a present gate
`line. GL1 also serves as a previous gateline (GLO) for a next
`pixel circuit (not shown).
`0047 FIG. 4 is a timing diagram of the circuit of FIG.3.
`A frame time is broken up into a preset time period, a write
`date time period and an expose time period, and the preset
`time period is composed of three Smaller time periods,
`namely til, t2 and t3.
`0.048. In time period t1, an initial presetting of circuit 300
`occurs before the array is addressed. Time period t1 occurs
`
`at the beginning of a first occurrence of a frame time, but it
`is not required for Subsequent frames. The Voltage of data
`line 110 is set to 0 V while gate lines GL0 and GL1 are
`brought high, and generator 140 sets cathode Voltage (Vca)
`120 to a voltage of V1. This results in a voltage V5 across
`storage capacitor 104 and --OV across OLED 105.
`0049. In time period t2, gate lines GL0 and GL1 are low
`while generator 140 sets cathode voltage (Vca) 120 to V2.
`A voltage V8 is across OLED 105. At the end of time period
`t2, generator 140 Switches cathode voltage (Vca) 120 to a
`voltage V3.
`0050 Time period t3 for an individual pixel occurs when
`the previous gate line GL0 is brought high. The completion
`of presetting of circuit 300 occurs during time period t3, just
`before data is to be written to circuit 300. NMOS transistor
`102 is turned on connecting circuit node 107 to ground. The
`Voltage acroSS Storage capacitor 104 goes to a preset Voltage
`V6, i.e., the threshold voltage of NMOS 103.
`0051). In circuit 300, after GLO goes low, and while GL1
`is set high, data is written to circuit 300, that is the data
`Voltage is added to the preset Voltage on Storage capacitor
`104. NMOS transistor 102 is turned off and NMOS transis
`tor 101 is turned on. The data voltage on data line 110 is
`written onto circuit node 107. Ideally, the resultant voltage
`acroSS Storage capacitor 104 will be equal to the Sum of the
`preset Voltage and the data Voltage. However, in practice, the
`actual resultant Voltage acroSS Storage capacitor 104 will be
`equal to the preset Voltage plus 0.95 (data Voltage). This
`difference between the ideal voltage and the actual voltage
`is due to the charging current through Storage capacitor 104
`into OLED capacitance 106 causing a slight increase of the
`voltage at circuit node 125.
`0052. During the expose time interval, generator 140 sets
`cathode voltage (Vca) 120 V4. NMOS transistor 103 oper
`ates in the Saturation current regime, Vds>VgS-Vt. Current
`flowing through NMOS transistor 103 into OLED 105 will
`be proportional to (0.95*Vdata+Vt-Vt) or proportional to
`(Vdata).
`0053 FIG. 4 shows waveforms for an individual pixel
`circuit 300 that is one of a plurality of Such pixel circuits in
`a row of an array. Although the write data time period is
`shown as overlapping a portion of the preset time interval,
`that actual writing of the data Voltage onto Storage capacitor
`104 for circuit 300 occurs just after time period t3 of the
`preset time period. The write data time period is shown as
`overlapping the preset time interval because other pixel
`circuits that are located nearer the top of the array will have
`data written to their respective Storage capacitors before
`pixel circuit 300. Accordingly, the actual writing of the data
`voltage to pixel circuit 300 occurs somewhere in the middle
`of the write data interval, as shown in FIG. 4.
`0054 For example, assume that pixel circuit 300 is a
`pixel circuit in the 100" row. Also assume that GL0, and
`GL1 are gate lines for an n" row. As such, the gate lines for
`pixel circuit 300 would be designated as GL0,
`and
`GL11oo. For a pixel circuit in the top row, GL0 (preset of
`the first pixel) pulses high in a time period t3 that is very near
`to the beginning of the preset time interval, and GL1 (write
`to the first pixel) pulses high very near the beginning of the
`write data interval. The write gate line of the first row pixel
`(GL1) also serves as the preset gate line for a second row
`
`Petitioner Samsung Ex. 1007 - Page 9 of 11
`
`

`

`US 2003/0095087 A1
`
`May 22, 2003
`
`pixel (GLO). AS Such, a Second row pixel is preset by GL0.
`concurrently with the writing of data to a first row pixel by
`GL1. This sequence of presetting and writing propagates
`through the row of pixels. Such that the writing of data to the
`99" row pixel by GL1so is coincident with the presetting of
`the 100" row pixel by GL0,oo. Accordingly, the writing of
`data to the 100" row pixel circuit by GL11oo occurs well into
`the write data interval.
`0.055 The first row pixel is in a row that is not preceded
`by any pixel circuit. AS Such, there is, theoretically, no
`previous gate line to serve as a GLO. Accordingly, GL0
`receives a dummy pulse.
`0056. In both of circuits 100 and 300, an initial voltage is
`established acroSS Storage capacitor 104 at the beginning of
`a first occurrence of a frame time. For example, with
`reference to FIG. 2, in time interval til, the preset voltage is
`Set high, thus establishing a Voltage V5 acroSS Storage
`capacitor 104. Similarly, referring to FIG. 4, in time interval
`t1, GL0 is set high to establish voltage V5 across storage
`capacitor 104. Note also in FIG. 4, that during time interval
`t1, GL1 is set high, because it serves as a GLO for a pixel
`circuit in a next row. For Subsequent frames, time interval t1
`is not required because the Voltage acroSS Storage capacitor
`104 is assured to be equal to or greater than Vt due to a
`previous preset voltage, and NMOS transistors 101 and 102
`drain to Source leakage currents.
`0057 Apolarity reversal of voltage on the source to drain
`and gate to drain terminals of the NMOS transistor 103
`Serves to remove trapped charge from theses regions,
`thereby minimizing the effects of electrical stress on NMOS
`transistor 103. In FIG. 2 and FIG. 4, the voltage polarity
`changes of the gate to drain terminal and Source to drain
`terminals of NMOS transistor 103 are shown as Vsd and
`Vgd, respectively. During the t1 and t3 time intervals, Vgd
`is at OV. Vgd is positive during the t2 time interval and
`during the write time interval after data has been written.
`Vgd is negative during the expose interval. At the beginning
`of the t2 time interval, Vsd voltage is positive. Vsd is at OV
`at the end of the t2 time interval. Vsd is a negative Voltage
`during all other time intervals.
`0.058
`Circuits 100 and 300 are current sources for driving
`an anode of OLED 105, where OLED 105 is configured with
`a common cathode. That is, the common cathode is the
`connection to Vca Signal generator 140, which is also
`connected to the cathodes of all OLEDs in the display.
`0059 Circuits 100 and 300 can be implemented with
`PMOS transistors where the cathode of OLED 105 is driven
`and the anode of OLED 105 is common. In such a configu
`ration, the circuit forms and Voltages are complimentary to
`those of FIGS. 1-4.
`0060. The pixel circuits of the present invention offers
`Several advantages that are worth noting:
`0061 (1) The present invention substantially reduces
`threshold Voltage variations and the undesirable effects
`of