IPR2021-00591
`U.S. Patent No. 7,868,880
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
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`
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`SAMSUNG ELECTRONICS CO., LTD., AND
`SAMSUNG ELECTRONICS AMERICA, INC.
`Petitioners
`
`v.
`
`SOLAS OLED LTD.
`Patent Owner.
`______________________________________________
`Case No. IPR2021-00591
`U.S. Patent No. 7,868,880
`______________________________________________
`
`
`PETITIONERS’ REPLY
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`

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`TABLE OF CONTENTS
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`Page
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`B.
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`C.
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`
`I.
`INTRODUCTION .......................................................................................... 1
`CLAIM CONSTRUCTION ........................................................................... 1
`II.
`III. ANTICIPATION AND SINGLE-REFERENCE OBVIOUSNESS
`GROUNDS ..................................................................................................... 1
`A.
`“Vicinities of Intersections” (Limitations 1.1, 2P, 3.1, 25P) ............... 1
`1. Morosawa ................................................................................... 2
`2. Miyazawa ................................................................................... 3
`“Drive Control Unit” (Limitations 1.7.1, 3.5.1, 5, 7) ........................... 3
`1. Morosawa ................................................................................... 5
`2. Miyazawa ................................................................................... 8
`“Setting … display pixels to the non-display operation state”
`(Limitations 2.4.1, 25.4) ..................................................................... 12
`1. Morosawa ................................................................................. 12
`2. Miyazawa ................................................................................. 12
`“Bias lines,” “state setting unit,” “setting specific bias state,”
`“eliminate bias state set” (Limitations 1.2, 1.6, 1.7.3, 2.4.3, 6.1,
`6.2, 27, 28, 30) .................................................................................... 15
`1. Morosawa ................................................................................. 16
`2. Miyazawa ................................................................................. 25
`“Discharges electric charges” (Claims 14, 30) .................................. 28
`1. Morosawa ................................................................................. 28
`2. Miyazawa ................................................................................. 29
`IV. MOROSAWA + SHIRASAKI ..................................................................... 31
`A.
`POSA would have been motivated to combine Morosawa and
`Shirasaki ............................................................................................. 31
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`D.
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`E.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`B. Morosawa and Shirasaki render obvious claims 18-24 and 34-
`40 ........................................................................................................ 31
`V. MOROSAWA + SHIRASAKI + KOYAMA .............................................. 32
`VI. MOROSAWA + HECTOR .......................................................................... 33
`VII. CONCLUSION ............................................................................................. 33
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`LIST OF EXHIBITS
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`Ex-1001
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`U.S. Patent No. 7,868,880
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`Ex-1002
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`Claim Listing
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`Ex-1003
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`Declaration of Dr. Miltiadis Hatalis
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`Ex-1004
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`Curriculum Vitae of Dr. Miltiadis Hatalis
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`Ex-1005
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`Prosecution History of U.S. Patent No. 7,868,880
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`Ex-1006
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`U.S. Patent Pub. No. 2005/0083270 (“Miyazawa”)
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`Ex-1007
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`U.S. Patent Pub. No. 2003/095087 (“Libsch”)
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`Ex-1008 WIPO Pub. No. WO 2004/040543 (“Morosawa”)
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`Ex-1009 WIPO Pub. No. WO 2004/086347 (“Shirasaki”)
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`Ex-1010
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`U.S. Patent No. 7,564,433 (“Hector”)
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`Ex-1011
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`U.S. Patent Pub. No. 2003/0197664 (“Koyama”)
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`Ex-1012
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`reserved
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`Ex-1013
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`Public Hearing Transcript USITC Hearing 337-TA-1243 (excerpts)
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`Ex-1014
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`Deposition Transcript of Thomas Credelle
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`iii
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`I.
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`INTRODUCTION
`Solas challenges the prior art’s disclosure of only a few limitations that cut
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`across several of the ’880 Patent’s 40 claims. But Solas’s distinctions are based on
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`its expert Mr. Credelle’s misreading the prior art and on his apparent insistence
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`that the prior art must meet a far higher standard of disclosure than does the ’880
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`Patent itself. As Mr. Credelle’s deposition made clear, the proper application of
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`the prior art demonstrates all 40 claims of the ’880 Patent are invalid.
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`II. CLAIM CONSTRUCTION
`Certain terms of the ’880 Patent were construed in the related ITC case.
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`POR, 12-13; Ex-2004. Mr. Credelle confirmed that whether one applied plain
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`meaning or the constructions from the ITC case would make no difference. Ex-
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`1014, 18:5-12; Ex-2001, ¶71.
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`III. ANTICIPATION AND SINGLE-REFERENCE OBVIOUSNESS
`GROUNDS
`Solas challenges only a few claim elements in its POR. But each is clearly
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`disclosed by both Miyazawa and Morosawa, as described below.
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`A.
`“Vicinities of Intersections” (Limitations 1.1, 2P, 3.1, 25P)
`Each independent claim requires “display pixels” be “arranged . . . in
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`vicinities of [respective] intersections of” scanning lines and data lines. Solas
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`incorrectly argues this limitation is not disclosed by either Morowasa or
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`Miyazawa. POR, 14, 18, 21, 29, 34, 49, 53, 63. Mr. Credelle asserts prior-art
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`1
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`figures showing pixels located near intersections of scanning and data lines do not
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`disclose distances and do not show that pixels are located “entirely within areas
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`defined by” these intersections. E.g., Ex-2001, ¶¶15, 51. Yet Mr. Credelle
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`admitted at deposition that the ’880 Patent also discloses neither distances between
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`pixels and intersections nor that pixels are located entirely within areas defined by
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`the intersections, and he further agreed that “in vicinities of” simply means “near”
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`or “in proximity to.” Ex-1014, 20:21-21:13, 22:15-23:9. Both Morosawa and
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`Miyazawa disclose this limitation.
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`1. Morosawa
`In addition to Figures 13, 14, and 16 of Morosawa, which Dr. Hatalis
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`explained show pixels located near intersections of scanning and data lines, (e.g.,
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`Ex-1003, ¶¶146-47), Mr. Credelle admitted that Morosawa further discloses “an
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`array of display pixels…arranged near each of the intersecting points of the signal
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`lines and in the direction of the scanning lines….” (Ex-1008, 2:16-20; Ex-1014,
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`24:3-20), and “display pixels with optical elements arranged near the intersecting
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`the intersecting point of the plurality of signal lines and the plurality of scanning
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`lines” (Ex-1008, 6:12-18; Ex-1014, 24:21-25:9), and “in FIG. 16,…the pixel driver
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`circuits DCx, near the intersecting point in which the scanning lines SL and the
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`2
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`signal lines DL are arranged…” Ex-1008, 57:23-58:2; Ex-1014, 27:4-28:1. 1 Thus,
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`Morosawa discloses this limitation.
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`2. Miyazawa
`In addition to Figure 1 of Miyazawa, which Dr. Hatalis explained shows
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`pixels located near intersections of scanning lines Y and data lines X (e.g., Ex-
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`1003, ¶57), Miyazawa also discloses “a group of pixels are arranged in a matrix (in
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`a two-dimensional plan view)…and pixels 2 (pixel circuits) are arranged
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`corresponding to intersections of the scanning lines and the data lines.” Ex-1006,
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`¶88. Mr. Credelle admitted Miyazawa “does show schematically that they are
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`located as described.” Ex-1014, 28:17-29:20. Thus, Miyazawa also discloses this
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`limitation.
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`B.
`“Drive Control Unit” (Limitations 1.7.1, 3.5.1, 5, 7)
`The ’880 Patent uses the term “drive control unit” synonymously with
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`“system controller,” and this term was so construed in the ITC. Ex-1014, 31:21-
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`32:20; Ex-1001, 6:8-9 (“a system controller (a drive control unit) 150”); Ex-2004,
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`69. Claims 1 and 3 require a “drive control unit” that “controls the power source
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`drive unit […] to set the display pixels to a non-display operation state” and that
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`controls “the scanning drive unit” to set “the display pixels to the selection state.”
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`1 Throughout, emphasis is added unless otherwise indicated.
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`3
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`Ex-1001, claims 1, 3. The ’880 Patent discloses such a system controller (150) in
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`Figure 1, below. Ex-1001, Fig. 1.
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`“System controller” 150 outputs a “scanning control signal” to control the
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`“scanning driver” 120 and a “power source control signal” for controlling “power
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`source driver” 130. The ’880 Patent further explains:
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` The system controller 150 operates each of the drivers at a
`predetermined timing by generating and outputting a scanning
`control signal, a power source control signal and a data control signal
`at least to each of the Scanning driver 120, the power source driver 130
`and the data driver 140 as timing control signals for controlling an
`operation state and generates and outputs a scanning signal Vsel and a
`drive Voltage Vsc having a predetermined Voltage level as well as a
`gradation signal (a gradation current Idata) corresponding to the display
`data.
`Ex-1008, 10:11-26.
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`While the drive control unit of the ’880 Patent controls those other units at a
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`predetermined timing by generating and outputting a scanning control signal, a
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`power source control signal, and a data control signal, Solas incorrectly argues
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`that Morosawa and Miyazawa do not disclose such a drive control unit (claims 1,
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`3, 5) (POR 16, 22, 47, 56), or that is controls a state setting unit (claim 7) (POR,
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`25, 60), even though both prior-art references disclose a system controller that
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`generates and outputs those same signals and controls those same blocks.
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`1. Morosawa
`Morosawa’s Figure 13 is essentially identical to ’880 Patent’s Figure 1.:
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`A system controller (150) outputs a “voltage control signal” to control “voltage
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`driver” 140 and a “scanning control signal” to control “scanning driver” 120A.
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`See also Ex-1003, ¶¶156-57 (citing Ex-1008, 52:23-53:14, 54:5-55:10, 59:2-5,
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`5
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`60:9-15, Figs. 13, 19). Moreover, Figure 14 shows the voltage control signal
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`comprises a VCLK and VSTR signal and the scanning control signal comprises a
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`SCLK and SSTR signal, and Morosawa notes that as a result of the system
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`controller’s “generating and outputting” VCLK, VSTR, SCLK, and SSTR, “each
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`driver operates to a predetermined timing.” Ex-1008, 54:4-13. That timing is
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`depicted in Figure 19, which, as Dr. Hatalis explained, shows that the voltage is set
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`to a low value to set the pixels to a non-display operation state and that during that
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`time, the scanning driver goes high to set the pixels to the selection state. Ex-1008,
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`Fig. 19; Ex-1003, ¶¶156-57. Thus, Morosawa discloses claim elements 1.7.1 and
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`3.5.
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`Claim 5 further requires that the drive control unit also controls the power
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`source drive unit to supply a voltage to set the pixels to a display (on) state. Figure
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`19 shows that the “power supply voltage Vsc” is also controlled to drive high to
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`turn the pixel on, defining the “light generation operation period Tnse.” Ex-1008,
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`Fig. 19; Ex-1003, ¶¶156-57, 179-83.
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`Claim 7 requires that the drive control unit control the state-setting unit to
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`drive the bias lines for resetting the pixels. Dr. Hatalis explains that Morosawa
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`discloses “[a] high-level reset control signal RST is provided via the reset line RL
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`from the system controller 150,” and the reset line is what Dr. Hatalis identifies as
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`the claimed bias line (see also Section III.D, below). Ex-1003, ¶¶186, 190; Ex-
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`1008, 142:16-20. Mr. Credelle admitted that the “reset must come from the
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`driver…and that driver is controlled by timing that’s related to the data driver and
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`the system controller,” and further, that Morosawa’s “system controller is the
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`mother of the timing generation…there is timing from the system controller that
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`has to organize all the…lines.” Ex-1014, 109:6-25. Thus, Morosawa discloses
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`claim 7. Therefore, Morosawa discloses all of the “drive control unit” limitations
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`Solas contends are missing.
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`2. Miyazawa
`Miyazawa similarly discloses, in Figure 1, a “control circuit” 5 that is
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`expressly shown to supply control signals to a “scanning line driving circuit” 3, a
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`“data line driving circuit” 4, and a “power line control circuit” 6. This “control
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`circuit 5 synchronously controls a scanning line driving circuit 3, a data line
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`driving circuit 4 and a power line control circuit 6.” Ex-1006, ¶90; Ex-1003, ¶¶63-
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`64.
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`U.S. Patent No. 7,868,880
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`This “synchronous[] control” is illustrated in the timing diagram of
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`Miyazawa’s Figure 10, annotated below, showing power line control circuit 6 is
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`controlled to drive voltage line VLa from Vdd to Vss at time t2’ and to hold it at
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`Vss during t2’ to t3 and from t0 to t2 to set the pixel to a non-display state. Ex-
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`1006, ¶90, Fig. 16; Ex-1003, ¶¶63-64. During that non-display state, the scanning
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`line driving circuit 3 is controlled to drive select line SEL1 high from t1 to t2 to set
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`the pixels to the selection state during the non-display period. Id.
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`9
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`Claim 5 requires the drive control unit to control the power source drive unit
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`to supply a voltage to set the pixels to a display (on) state. Figures 9 and 10 show
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`the power supply voltage is driven high (Vdd) at time t2 to turn the pixel on. Ex-
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`1006, ¶¶127-29, Figs. 9, 10; Ex-1003, ¶¶86-89. At time t2, the drive control unit
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`controls the power line control circuit to drive Vla to Vdd, which allows the OLED
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`to be forward biased through T3 and T5 and turned on. Id. Thus, Miyazawa
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`discloses claim 5.
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`10
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`Claim 7 requires that the drive control unit control the state-setting unit to
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`drive the bias lines for resetting the pixels. Dr. Hatalis explains that Miyazawa
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`discloses that the “control circuit” 5 controls the “scanning line driving circuit” 3,
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`wherein each output Y comprises four outputs Ya, Yb, Yc, and Yd, and wherein
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`Yb and Yc drive signals SEL2 and SEL3, which are responsible for setting a
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`specific bias state and eliminating the previous bias state set, as the annotated
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`excerpts of Figures 1 and 9, below, show. Ex-1003, ¶¶62, 66-68, 95; Ex-1006, ,
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`¶¶126, 129, Figs. 1, 9. Thus, Miyazawa also discloses claim 7.
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`Therefore, Miyazawa also discloses all of the “drive control unit” limitations
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`Solas contends are missing.
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`C.
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`“Setting … display pixels to the non-display operation state”
`(Limitations 2.4.1, 25.4)
`1. Morosawa
`Solas does not challenge Morosawa’s disclosure of this element.
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`2. Miyazawa
`Solas alleges, incorrectly, that Dr. Hatalis must combine two embodiments
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`of Miyazawa to disclose this limitation. Ex-2001, ¶¶81-83. But Figures 9 and 10
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`both depict Miyazawa’s fourth embodiment. Ex-1006, ¶¶85-86. From those
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`figures, annotated below, when VLa is driven low (to Vss), the OLED is turned
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`12
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`off, setting the pixel to a non-display operation state.
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`13
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`In particular, because the cathode of the OLED is at Vss (Ex-1006, ¶124
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`(“To the cathode of the organic EL element OLED, the reference voltage Vss is
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`fixedly applied.)), it is impossible to forward bias the OLED if VLa is also set to
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`Vss. The only other way a voltage above Vss could possibly be applied to the
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`OLED would be when VLb goes high during t0 to t1. But from the timing diagram
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`of Figure 9, SEL4 is low during that time, so T5 is off and there is no path from
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`VLb to the OLED’s anode. Thus, the OLED is turned off when VLa is set to Vss.
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`Ex-1003, ¶75; Ex-1006, ¶127. Mr. Credelle does not dispute this:
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`Q: [A]t time t2’, the OLED turns off when VLa goes from Vdd to Vss;
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`U.S. Patent No. 7,868,880
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`is that right?
`A: It should be off, yes, even though there’s—still a signal—even
`though there’s still a signal on the capacitor.
`Ex-1014, 64:20-24.
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`While paragraph 115 of Miyazawa discloses that the pixel circuit of the third
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`embodiment is also set to a display-off state when VLa is set to Vss (Ex-1006,
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`¶115), such disclosure is unnecessary to understanding Miyazawa’s disclosure of
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`how the fourth embodiment operates.
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`Figure 9 also shows that SEL1 goes high during the non-display period,
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`turning on transistor T1, such that the non-display period includes “a period in
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`which the display pixels are set to a selection state,” as the claims require. Thus,
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`Miyazawa’s fourth embodiment, by itself, discloses these elements of claims 2 and
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`25.
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`D.
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`“Bias lines,” “state setting unit,” “setting specific bias state,”
`“eliminate bias state set” (Limitations 1.2, 1.6, 1.7.3, 2.4.3, 6.1, 6.2,
`27, 28, 30)
`This series of interrelated limitations relates to the claimed reset operation
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`by which a “state setting unit” drives a reset signal on a “bias line” to “eliminate
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`the bias state set” (i.e., eliminate the prior data value) and to apply a “specific bias
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`state,” which certain claims (14, 28, 30) specify is either a no-voltage (ground, or
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`0V) or reverse-bias voltage state. Solas incorrectly asserts that Morosawa and
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`Miyazawa do not disclose these limitations.
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`1. Morosawa
`Morosawa’s Figure 16 discloses a pixel circuit (identical to Figures 3, 6, and
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`7 of the ’880 Patent) that does not include a separate bias (or reset) transistor. Ex-
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`1008, Fig. 16:
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`But Morosawa discloses an alternative pixel circuit at Figure 38 that includes a
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`reset circuit comprising a transistor Tr85 controlled by a reset line (RL, in red). Ex-
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`1008, 140:8-21; Fig. 38.
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`16
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`Morosawa expressly teaches applying the Tr85 reset mechanism to Figure 16; it
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`states that although Figure 38 shows the reset circuit applied to the pixel circuit of
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`Figure 21 (Ex-1008, 139:22-140:2), “other circuit arrangements can be applied, for
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`example, the pixel driver circuit shown in FIG. 16.” Ex-1008, 140:2-7. This is
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`illustrated below. Ex-1003, ¶¶139-43, 148-51; Ex-1008, 139:22-140:7.
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`IPR2021-00591
`U.S. Patent No. 7,868,880
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`Solas argues incorrectly that these interrelated claim limitations are not met
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`because (1) Morosawa does not teach adding the reset circuit of Figure 38 to the
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`pixel circuit of Figure 16, and (2) Morosawa discloses no “state setting unit” for
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`driving that reset line.
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`a. Mr. Credelle admits added reset line is not even
`necessary for certain claims
`Before addressing adding the reset mechanism to Figure 16, Petitioner notes
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`that certain claims—2, 27, 28, and 30—do not require a state setting unit and bias
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`or reset line but only “setting a specific bias state” and “eliminating the bias state
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`set corresponding to the gradation signal.” Mr. Credelle admitted that Morosawa’s
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`Figure 16 by itself, even without adding the Tr85 reset circuit, already meets these
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`U.S. Patent No. 7,868,880
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`limitations:
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`Q. Okay. So then it's your—it’s your opinion that Morosawa's Figure
`16 unmodified with any additional reset circuit from Figure 38, for
`example, would already be capable of eliminating the prior bias state
`by using that alternative data line reset mechanism?
`A. It certainly would remove most if not all of it by that design of the
`data driver, in my opinion.
`Q. So that—that data line reset would be capable of eliminating the
`prior bias state?
`A. Effectively yes, as I described.
`Q. And it would do by setting a certain bias state, for example, ground?
`A. It would—it would set a voltage on the data line. For example,
`ground, that would be, basically, discharge the capacitor Cx because
`Tr71 is also turned on and connected to ground.
`Q. And would that operation set a specific bias state of the capacitor?
`A. It—it would set a specific bias state on the capacitor.
`Ex-1014, 78:8-79:4. Thus, Solas’s challenge to claim elements 2.4.3, 27, 28, and
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`30, which depends entirely on attacking the addition of Tr85 to Figure 16, should
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`be disregarded in light of Mr. Credelle’s admissions above.
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`Regardless, Mr. Credelle is also incorrect that Morosawa does not teach
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`adding the Tr85 reset mechanism to Figure 16, as described below.
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`b. Morosawa teaches adding the reset circuit to Figure 16’s
`pixel circuit
`Despite the express disclosure discussed above and other evidence cited by
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`Dr. Hatalis (Ex-1003, ¶¶ 138-143, 148-151), Mr. Credelle argues that when
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`Morosawa states “other circuit arrangements can be applied, for example, the pixel
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`driver circuit shown in FIG. 16,” he does not really mean Figure 16’s pixel
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`circuit, but rather, some “modification of Fig. 21 pixel circuit with a pixel circuit
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`that has other changes such as changing p-type transistors to n-type transistors or
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`the elimination of Tr81, for example.” Ex-2001, ¶126. But Morosawa would not
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`have referred to Figure 16’s pixel circuit if he actually meant to refer to some other
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`pixel circuit, and Mr. Credelle has no plausible explanation for this.
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`(1) Tr85 reset circuit not limited to “current
`application” pixels
`Mr. Credelle asserts that “the application of the reset circuit of Fig. 38 can
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`only be applied to pixel circuits that are ‘write-in’ or current application circuits,”
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`and that Figure 16 is not a “write-in” pixel circuit. Ex-2001, ¶126 (emphasis
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`original). But Morosawa expressly refers to Figure 16’s programming current as a
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`“write-in current.” Ex-1008, 59:10-11 (“negative polarity current is supplied as
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`the write-in current Ipix…”), demonstrating Mr. Credelle is wrong.
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`Moreover, just before Morosawa introduces the Tr85 reset circuit of Figure
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`38, he refers to the “sixth through eighth embodiments mentioned above” and
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`states “this invention is not limited to these configurations and can be made to
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`achieve the technical concept that performs a reset operation according to the
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`configuration of the pixel driver circuits…Hereinafter, explained in detail.” Ex-
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`1008, 138:16-139:5. Morosawa then proceeds to describe the Tr85 reset circuit
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`IPR2021-00591
`U.S. Patent No. 7,868,880
`shown in Figure 38 in this context. Ex-1008, 139:8-141:18. While the sixth
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`embodiment is a “current application”-type pixel circuit (Ex-1008, 16:22-17:7), the
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`seventh embodiment is a “current sinking”-type pixel circuit (Ex-1008, 17:8-14),
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`as Mr. Credelle admits. Ex-1014, 104:9-19. Thus, Morosawa teaches applying the
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`Tr85-type reset circuit to both “current application” and “current sinking” pixel
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`circuits.
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`(2) Tr85 reset circuit is not superfluous
`Mr. Credelle argues incorrectly that the Tr85 reset circuit would be
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`superfluous because “the ‘reset’ of the voltage on the capacitor provided by this
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`mechanism already occurs by the normal operation of Figure 16.” Ex-2001, ¶130.
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`This argument is belied by the fact the ’880 Patent discloses, in Figures 3, 6A, 6B,
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`and 7, a pixel circuit identical to that of Figure 16 of Morosawa, and which Mr.
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`Credelle admits is also programmed using the “current sinking” method. Ex-1001,
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`Figs. 3, 6A, 6B, 7; Ex-1008, Fig. 16; Ex-1014, 71:22-72:1; 72:19-22. Mr. Credelle
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`further admitted:
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`Q. …So in your opinion, the—the circuit of figure 6B, this would also
`be cleared just by the normal operation the pixel circuit because it’s also
`using a current sinking-type programming arrangement?
`A. That—that depends on the design of the data driver, but generally
`that would be correct.
`Ex-1014, 73:5-11. Yet the ’880 Patent nevertheless introduces an improved
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`embodiment in Figure 11 with an added reset or “bias” transistor within the pixel
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`circuit to improve the reset performance by reducing threshold voltage shift:
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`Q. And is—is that your understanding that the adding the bias transistor
`helps to address that issue of a threshold voltage shift?
`A. That—that is what the inventors claim.
`Ex-1014, 75:5-8. Thus, a reset circuit located in the pixel itself is not superfluous,
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`but has other benefits, as even the ’880 Patent itself admits.
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`(3) Tr85 reset circuit is functional in Figure 16
`Mr. Credelle incorrectly argues the Tr85 reset circuit would not be
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`functional when added to Figure 16. Ex-2001, ¶¶136-37. But Mr. Credelle
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`intentionally misinterprets its operational timing. While Dr. Hatalis and Mr.
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`Credelle agree that the reset line driving Tr85 goes high at the same time as the
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`select signal, Mr. Credelle alleges that the reset remains high for the entire duration
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`of the select period, thereby interfering with the data programming operation. Ex-
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`2001, ¶137. Besides being completely counterintuitive—a POSA would not try to
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`hold the circuit in reset while also trying to program it—Dr. Hatalis was clear that
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`the reset is asserted only at the beginning of the selection period, before the writing
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`of the new data current takes place:
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`Q. So is the circuit you discuss that combines elements of Figure 16
`with elements of Figure 38, that would require a different timing
`diagram than what’s shown in Morosawa 19, correct?
`A. Well, it would requires to—to add the timing of the—of the bias
`lines….So then as for the teaching of Morosawa, the reset operation
`would—will take place with the pixel at the selected state before the
`writing of the new current.
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`Ex-2003, 108:4-20; see also Ex-1008, 144:18-21 (“this configuration comprises a
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`reset mechanism (the Nch transistor Tr85 and the reset line RL) for discharging the
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`stored charge in advance of the write-in operation of the gradation currents…”).
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`Mr. Credelle argues that while both the reset and select lines are on, only a
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`portion of the programming current Ipix would flow through Tr73, thereby failing
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`to properly program the pixel. Ex-2001, ¶137. But Mr. Credelle admits once Tr85
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`turns off, the modified Figure 16 operates just like the original figure 16. Ex-1014,
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`111:20-24. Thus, the programming proceeds normally after the reset completes.
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`Mr. Credelle admitted he did not analyze this case in forming his opinion:
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`Q. Okay. So but you did—you did not analyze the case where the reset
`line shown here that would drive Tr85 was held high for that—
`essentially that same period of time and then be low for the remainder
`of the select period?
`A. I—I didn’t analyze that because I don’t think that solution was
`proposed by Dr. Hatalis.
`Ex-1014, 122:14-20.
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`Thus, Morosawa teaches adding the Tr85 reset mechanism to Figure 16; the
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`reset circuit is not superfluous or the ’880 Patent would not have also taught
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`improving the identical pixel circuit by adding a reset transistor; and the Tr85 reset
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`circuit in the Figure 16 pixel circuit is functional, as described by both Morosawa
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`and Dr. Hatalis.
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`c. Morosawa discloses a state setting unit
`According to the ’880 Patent, the “reverse bias driver” that drives the bias
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`(or reset) line under control of the system controller 150 is the claimed “state
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`setting unit.” Ex-1001, 18:35-38 (“Furthermore, the configuration thereof
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`comprises a reverse bias driver (a state setting unit) 170 for applying a bias signal
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`(a set signal) Vbs having a predetermined voltage level to the display pixels EM in
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`each row.”) See id., Fig. 9 (System Controller 150 controls Reverse Bias Driver
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`170 to drive the bias (reset) lines to each pixel).
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`
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`Dr. Hatalis explained that, while Morosawa does not illustrate a top-level
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`block diagram with a state setting unit, a POSA would understand that the “reset
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`control signal RST” from the “system controller 150” (Ex-1008, 141:9-18) would
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`be applied to each row of pixels by driver logic that would comprise the “state
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`setting unit.” Ex-1003, ¶155. Mr. Credelle admitted there must be such a driver
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`that applies that reset signal under control of the system controller:
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`Q. But in Figures 38 and 39 they’re describing alternative reset
`operation to that data driver reset; is that right?
`A. Yes, that's right. So they’ve added a reset. And the reset must
`come from the driver. I don't think they specify it. And that driver is
`controlled by timing that's related to the data driver and the system
`controller. So—that's all I remember at this point.
`Q. Okay. So there—but there's some kind of driver that drivers the
`reset line according to timing provided by the system controller; is that
`a fair statement?
`A. System controller is the mother of the timing generation. That
`timing goes through other circuits. So how it gets there, I don't know,
`but there is timing from the system controller that has to organize all
`the—the—the—the lines.
`Ex-1014, 109:6-25.
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`These drivers that drive the reset (bias) lines to apply RST to each pixel row
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`under the control of the system controller 150 comprise the claimed “state setting
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`unit.” Thus, Morosawa discloses the disputed claim limitations 1.2, 1.6, 1.7.3,
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`2.4.3, 6.1, 6.2, 27, 28, 30.
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`2. Miyazawa
`a. Miyazawa discloses “state setting unit” (claims 1.6, 1.7.3,
`6.2)
`Solas does not dispute Miyazawa’s disclosure of a reset transistor for setting
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`a specific bias state and eliminating the bias state set, but argues Miyazawa does
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`not disclose a state setting unit because the “scanning line drive circuit 3” (Fig. 1)
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`is already identified as the claimed “scanning drive unit.” Ex-2001, ¶¶78, 93, 95.
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`But Dr. Hatalis points out that each of the “Y” outputs of the “scanning line
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`driving circuit 3” in Figure 1 is actually four outputs Ya, Yb, Yc, and Yd in Figure
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`9, which Mr. Credelle admits. Ex-1006, ¶123 (“one scanning line Y shown in FIG.
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`1 includes four scanning lines Ya to Ya to which scanning signals SEL1 to SEL4
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`are respectively supplied…”); Ex-1003, ¶¶62, 93; Ex-1014, 61:11-62:6.
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`
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`Figure 10 shows that the driver that sources the SEL1 signal to put the pixel
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`in a selection state (by turning on T1) has a different waveform from SEL2 and
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`SEL3, which drive the bias transistors T2 and T4 for eliminating the prior bias
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`state, thus demonstrating that these signals are driven by independent drivers,
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`which Mr. Credelle admits. Ex-1006, Figs. 9, 10; Ex-1003, ¶62; Ex-1014, 62:7-16.
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`Thus, the set of drivers that drive SEL2 and SEL3 for each row of pixels comprise
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`the claimed “state setting unit” and are distinct from the drivers that drive SEL1
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`and comprise the “scanning drive unit,” even though all the drivers are housed
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`within the “scanning line driving circuit 3” block.
`
`
`b. Miyazawa discloses “setting specific bias state” and
`“eliminating bias state set” (claims 1.7.3, 2.4.3)
`The voltage between nodes N1 and N2 sets the programmed data current
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`through the OLED. Ex-1014, 50:4-7 (Q. So the voltage between node N1 and N2
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`in Figure 9, that’s what sets the brightness of the OLED during the emission phase;
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`is that correct? A. Yes”). Mr. Credelle also agreed that traces V1 and V2 in Figure
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`10 correspond to the voltages at nodes N1 and N2 in Figure 9. Id., 51:2-4.
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`Mr. Credelle further admitted that at time t2’, when SEL3 goes high, the bias
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`state represented by V1-V2 changes as V2 drops from a data voltage to a reverse
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`bias voltage Vrvs, as shown in Figure 10, and applying that specific bias state
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`eliminates the prior bias state set:
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`Q. So at t2', the—the operation of SEL3 going high eliminates the bias
`voltage—the prior bias—bias voltage from the circuit; is that right?
`A. It—it does re—it does eliminate that based on also the setting of—
`of VL