(12) United States Patent
`Hector et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,564.433 B2
`Jul. 21, 2009
`
`US007564433B2
`
`(54) ACTIVE MATRIX DISPLAY DEVICES
`(75) Inventors: Jason R. Hector, Redhill (GB); Mark J.
`Childs, Wootton Bassett (GB); David A.
`Fish, Haywards Heath (GB); Mark T.
`Johnson, Veldhoven (NL)
`(73) Assignee: Koninklijke Philips Electronics N.V.,
`Eindhoven (NL)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 362 days.
`10/542,903
`
`(21) Appl. No.:
`
`(*) Notice:
`
`(22) PCT Filed:
`(86). PCT No.:
`
`Jan. 20, 2004
`PCT/B2004/OOO156
`
`S371 (c)(1),
`Jul. 20, 2005
`(2), (4) Date:
`(87) PCT Pub. No.: WO2004/066249
`PCT Pub. Date: Aug. 5, 2004
`Prior Publication Data
`US 2006/OO77134A1
`Apr. 13, 2006
`Foreign Application Priority Data
`(30)
`Jan. 24, 2003
`(GB) ................................. O3O1659.9
`Apr. 11, 2003
`(GB) ................................. O3O8396.1
`
`(65)
`
`(51) Int. Cl.
`(2006.01)
`G09G 3/32
`(2006.01)
`G09G 3/30
`(52) U.S. Cl. ........................................... 345/82: 345/76
`(58) Field of Classification Search ................... 345/76
`345/82, 83, 60-100: 315/1693
`See application file for complete search history.
`
`
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`6/2006 Inoue et al. ................... 345/76
`7,061.452 B2
`3/2002 Hacket al. .................... 345.82
`2002/0030647 A1
`2002/0038998 A1* 4/2002 Fujita et al. ................. 313,495
`2002fOO54003 A1
`5, 2002 Kodate
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`O717446 A1
`
`6, 1996
`
`(Continued)
`OTHER PUBLICATIONS
`
`Joon-Chul Goh, et al: A New Pixel Circuit for Active Matrix Organic
`Light Emitting Diodes, IEEE, vol. 23, No. 9, Sep. 2002, pages.
`(Continued)
`Primary Examiner Amare Mengistu
`Assistant Examiner Robert R Rainey
`(57)
`ABSTRACT
`
`An active matrix display device uses an amorphous silicon
`drive transistor for driving a current through an LED display
`element. First and second capacitors are connected in series
`between the gate and source of the drive transistor, with a data
`input to the pixel provided to the junction between the first
`and second capacitors. The second capacitor is charged to a
`pixel data Voltage, and a drive transistor threshold Voltage is
`stored on the first capacitor. This pixel arrangement enables a
`threshold voltage to be stored on the first capacitor, and this
`can be done each time the pixel is addressed, thereby com
`pensating for age-related changes in the threshold Voltage.
`
`34 Claims, 10 Drawing Sheets
`
`Petitioner Samsung Ex. 1010 - Page 1 of 20
`
`

`

`US 7,564.433 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`2002fOO89496 A1*
`2003/0052843 A1*
`2003/0098828 A1*
`2005, 0104814 A1*
`2005/O156829 A1*
`
`T/2002
`3, 2003
`5/2003
`5/2005
`7/2005
`
`Numao ....................... 345.204
`Yamazaki et al. ............. 345/82
`Hunter et al. ................. 345/76
`Choi et al. .....
`... 345/76
`Choi et al. .................... 345/76
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`WO
`
`WO9636959 A1
`
`11, 1996
`
`OTHER PUBLICATIONS
`Yumoto A. et al: Pixel-Driving Methods for Large-Sized Poly-SI
`AM-OLED Displays, IDW. vol. Conf. 21/8, Oct. 2001, pp. 1395
`1398.
`
`Yi He, et al: Four-Thin Film Transistor Pixel Electrode Circuits for
`Active-Matrix Organic Light-Emitting Displays, vol. 40, No.3A Part
`1, Mar. 2001, pp. 1199-1208.
`HeY, et al.: Current Source A-Si-H Thin-FilmTransistor Circuit for
`Active-Matrix Organic Light-Emiting Displays, IEEE Inc, vol. 21.
`No. 12, Dec. 2000, pp. 590-592.
`S. R. Forest, et al: Electrophosphorescent Organic Light Emitting
`Devices: 52.1 SID, May 2002, pp. 1357-1359.
`J. P. J. Markham: Highly Efficient Solution Processible Dendrimer
`LED's, L-8 SID, May 2002, pp. 1032-1035.
`
`* cited by examiner
`
`Petitioner Samsung Ex. 1010 - Page 2 of 20
`
`

`

`U.S. Patent
`U.S. Patent
`
`Jul. 21, 2009
`Jul. 21, 2009
`
`Sheet 1 of 10
`Sheet 1 of 10
`
`US 7,564.433 B2
`US 7,564,433 B2
`
`9
`
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`
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`acdicic
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`
`FIG. 1 prior art
`
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`
`
`
`FIG.2 prion art
`
`Petitioner Samsung Ex. 1010 - Page 3 of 20
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`Petitioner Samsung Ex. 1010 - Page 3 of 20
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`

`

`U.S. Patent
`
`Jul. 21, 2009
`
`Sheet 2 of 10
`
`US 7,564.433 B2
`
`26
`
`2
`
`32
`
`
`
`
`
`28
`
`FIG.3
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`24
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`al
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`
`Petitioner Samsung Ex. 1010 - Page 4 of 20
`
`

`

`U.S. Patent
`U.S. Patent
`
`Jul. 21, 2009
`
`Sheet 3 of 10
`
`US 7,564.433 B2
`US 7,564,433 B2
`
`ROWN
`
`bata (X_NANH
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`
`FIG.5
`
`Blanking Pulse
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`ar
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`a
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`a. s XX X XX as S X
`d S.
`35
`
`C
`
`FIG.6
`
`Petitioner Samsung Ex. 1010 - Page 5 of 20
`
`Petitioner Samsung Ex. 1010 - Page 5 of 20
`
`
`
`

`

`U.S. Patent
`U.S. Patent
`
`Jul. 21, 2009
`Jul. 21, 2009
`
`Sheet 4 of 10
`Sheet 4 of 10
`
`US 7,564.433 B2
`US 7,564,433 B2
`
`26
`26
`
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`A4 (n-1)
`
`32
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`C
`
`T
`
`D
`
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`A4({n)
`
`M
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`i P
`
`
`
`etitioner Samsung Ex. 1010 - Page 6 of 20
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`Petitioner Samsung Ex. 1010 - Page 6 of 20
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`

`

`U.S. Patent
`
`Jul. 21, 2009
`
`Sheet 5 of 10
`
`US 7,564.433 B2
`
`
`
`FIG.9
`
`Cathode
`
`Cathode
`
`Data
`
`x8 S.
`XX
`
`FIG.10
`
`Petitioner Samsung Ex. 1010 - Page 7 of 20
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`

`

`U.S. Patent
`
`Jul. 21, 2009
`
`Sheet 6 of 10
`
`US 7,564.433 B2
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`POWer
`
`
`
`X 8 &
`
`as
`
`s
`
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`al
`
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`ses
`X X
`S ay
`X
`
`Petitioner Samsung Ex. 1010 - Page 8 of 20
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`

`

`U.S. Patent
`
`Jul. 21, 2009
`
`Sheet 7 of 10
`
`US 7.564.433 B2
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`26
`
`32
`
`24
`
`FIG.13
`
`28
`
`26
`
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`
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`
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`
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`
`FIG.14
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Petitioner Samsung Ex. 1010 - Page 9 of 20
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`

`

`U.S. Patent
`
`Jul. 21, 2009
`
`Sheet 8 of 10
`
`US 7,564.433 B2
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`
`
`Data ( X X X X NXN+X X )
`FIG.15
`
`A23 - - - - - - -
`
`27
`
`FIG.16
`
`Petitioner Samsung Ex. 1010 - Page 10 of 20
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`

`

`U.S. Patent
`U.S. Patent
`
`Jul. 21, 2009
`Jul. 21, 2009
`
`Sheet 9 of 10
`Sheet 9 of 10
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`US 7,564.433 B2
`US 7,564,433 B2
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`26
`26
`
`2
`
`32
`32
`
`
`
`FIG.17
`FIG.17
`
`28
`28
`
`Ay
`
`A23
`
`s+<x
`
`Petitioner Samsung Ex. 1010 - Page 11 of 20
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`Petitioner Samsung Ex. 1010 - Page 11 of 20
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`
`

`

`U.S. Patent
`
`Jul. 21, 2009
`
`Sheet 10 of 10
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`US 7,564.433 B2
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`RoWN
`
`
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`Data ( X X X X NXN+1X X )
`FIG.19
`
`Petitioner Samsung Ex. 1010 - Page 12 of 20
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`

`

`1.
`ACTIVE MATRIX DISPLAY DEVICES
`
`US 7,564,433 B2
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`10
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`2
`and 200 nm. Typical examples of suitable organic electrolu
`minescent materials which can be used for the elements 2 are
`known and described in EP-A-0 717446. Conjugated poly
`mer materials as described in WO96/36959 can also be used.
`FIG. 2 shows in simplified schematic form a known pixel
`and drive circuitry arrangement for providing Voltage-pro
`grammed operation. Each pixel 1 comprises the EL display
`element 2 and associated driver circuitry. The driver circuitry
`has an address transistor 16 which is turned on by a row
`address pulse on the row conductor 4. When the address
`transistor 16 is turned on, a Voltage on the column conductor
`6 can pass to the remainder of the pixel. In particular, the
`address transistor 16 Supplies the column conductor Voltage
`to a current source 20, which comprises a drive transistor 22
`and a storage capacitor 24. The column Voltage is provided to
`the gate of the drive transistor 22, and the gate is held at this
`Voltage by the storage capacitor 24 even after the row address
`pulse has ended. The drive transistor 22 draws a current from
`the power supply line 26.
`To date, the majority of active matrix circuits for LED
`displays have used low temperature polysilicon (LTPS)
`TFTs. The threshold voltage of these devices is stable in time,
`but varies from pixel to pixel in a random manner. This leads
`to unacceptable static noise in the image. Many circuits have
`been proposed to overcome this problem. In one example,
`each time the pixel is addressed the pixel circuit measures the
`threshold voltage of the current-providing TFT to overcome
`the pixel-to-pixel variations. Circuits of this type are aimed at
`LTPS TFTs and use p-type devices. Such circuits cannot be
`fabricated with hydrogenated amorphous silicon (a-Si:H)
`devices, which is currently restricted to n-type devices.
`The use of a-Si:H has however been considered. The varia
`tion in threshold Voltage is Small in amorphous silicon tran
`sistors, at least over short ranges over the Substrate, but the
`threshold Voltage is very sensitive to Voltage stress. Applica
`tion of the high voltages above threshold needed for the drive
`transistor causes large changes in threshold Voltage, which
`changes are dependent on the information content of the
`displayed image. There will therefore be a large difference in
`the threshold Voltage of anamorphous silicon transistor that is
`always on compared with one that is not. This differential
`ageing is a serious problem in LED displays driven with
`amorphous silicon transistors.
`Generally, proposed circuits usinga-Si:HTFTs use current
`addressing rather than Voltage addressing. Indeed, it has also
`been recognised that a current-programmed pixel can reduce
`or eliminate the effect of transistor variations across the sub
`strate. For example, a current-programmed pixel can use a
`current mirror to sample the gate-source Voltage on a sam
`pling transistor through which the desired pixel drive current
`is driven. The sampled gate-source Voltage is used to address
`the drive transistor. This partly mitigates the problem of uni
`formity of devices, as the sampling transistor and drive tran
`sistor are adjacent each other over the Substrate and can be
`more accurately matched to each other. Another current sam
`pling circuit uses the same transistor for the sampling and
`driving, so that no transistor matching is required, although
`additional transistors and address lines are required.
`The currents required to drive conventional LED devices
`are quite large, and this has meant that the use of amorphous
`silicon for active matrix organic LED displays has been dif
`ficult. Recently, OLEDs and solution-processed OLEDs have
`shown extremely high efficiencies through the use of phos
`phorescence. Reference is made to the articles Electrophos
`phorescent Organic Light Emitting Devices, 52.1 SID 02
`Digest, May 2002, p 1357 by S. R. Forrest etal, and Highly
`Efficient Solution Processible Dendrimer LEDs, L-8 SID 02
`
`This invention relates to active matrix display devices,
`particularly but not exclusively active matrix electrolumines
`cent display devices having thin film Switching transistors
`associated with each pixel.
`Matrix display devices employing electroluminescent,
`light-emitting, display elements are well known. The display
`elements may comprise organic thin film electroluminescent
`elements, for example using polymer materials, or else light
`emitting diodes (LEDs) using traditional III-V semiconduc
`tor compounds. Recent developments in organic electrolumi
`nescent materials, particularly polymer materials, have dem
`onstrated their ability to be used practically for video display
`devices. These materials typically comprise one or more lay
`ers of a semiconducting conjugated polymer Sandwiched
`between a pair of electrodes, one of which is transparent and
`the other of which is of a material suitable for injecting holes
`or electrons into the polymer layer.
`The polymer material can be fabricated using a CVD pro
`cess, or simply by a spin coating technique using a solution of
`a soluble conjugated polymer. Ink-jet printing may also be
`used. Organic electroluminescent materials exhibit diode
`like I-V properties, so that they are capable of providing both
`a display function and a Switching function, and can therefore
`be used in passive type displays. Alternatively, these materials
`may be used for active matrix display devices, with each pixel
`comprising a display element and a Switching device for
`controlling the current through the display element.
`Display devices of this type have current-driven display
`elements, so that a conventional, analogue drive scheme
`involves supplying a controllable current to the display ele
`ment. It is known to provide a current source transistor as part
`of the pixel configuration, with the gate Voltage Supplied to
`the current source transistor determining the current through
`the display element. A storage capacitor holds the gate Volt
`age after the addressing phase.
`FIG. 1 shows a known pixel circuit for an active matrix
`addressed electroluminescent display device. The display
`device comprises a panel having a row and column matrix
`array of regularly-spaced pixels, denoted by the blocks 1 and
`comprising electroluminescent display elements 2 together
`with associated Switching means, located at the intersections
`between crossing sets of row (selection) and column (data)
`address conductors 4 and 6. Only a few pixels are shown in the
`45
`Figure for simplicity. In practice there may be several hun
`dred rows and columns of pixels. The pixels 1 are addressed
`via the sets of row and column address conductors by a
`peripheral drive circuit comprising a row, Scanning, driver
`circuit 8 and a column, data, driver circuit 9 connected to the
`ends of the respective sets of conductors.
`The electroluminescent display element 2 comprises an
`organic light emitting diode, represented here as a diode
`element (LED) and comprising a pair of electrodes between
`which one or more active layers of organic electrolumines
`cent material is sandwiched. The display elements of the
`array are carried together with the associated active matrix
`circuitry on one side of an insulating Support. Either the
`cathodes or the anodes of the display elements are formed of
`transparent conductive material. The Support is of transparent
`material Such as glass and the electrodes of the display ele
`ments 2 closest to the Substrate may consist of a transparent
`conductive material such as ITO so that light generated by the
`electroluminescent layer is transmitted through these elec
`trodes and the support so as to be visible to a viewer at the
`other side of the support. Typically, the thickness of the
`organic electroluminescent material layer is between 100 nm
`
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`10
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`3
`Digest, May 2002, p 1032, by J. P. J. Markham. The required
`currents for these devices are then within the reach of a-Si
`TFTs. However, additional problems come into play.
`The extremely small currents required for phosphorescent
`organic LEDs result in column charging times that are too 5
`long for a large display. A further problem is the stability
`(rather than the absolute value) of the threshold voltage of the
`TFTs. Under constant bias, the threshold voltage of a TFTs
`increases, therefore simple constant current circuits will
`cease to operate after a short time.
`Difficulties therefore remain in implementing an address
`ing scheme Suitable for use with pixels having amorphous
`silicon TFTs, even for phosphorescent LED displays.
`According to the invention, there is provided an active
`matrix device comprising an array of display pixels, each
`pixel comprising:
`a current driven light emitting display element;
`an amorphous silicon drive transistor for driving a current
`through the display element;
`first and second capacitors connected in series between the
`gate and Source or drain of the drive transistor, a data input to
`the pixel being provided to the junction between the first and
`second capacitors thereby to charge the second capacitor to a
`Voltage derived from the pixel data Voltage, and a Voltage 25
`derived from the drive transistor threshold voltage being
`stored on the first capacitor.
`This pixel arrangement enables a threshold Voltage to be
`stored on the first capacitor, and this can be done each time the
`pixel is addressed, thereby compensating for age-related 30
`changes in the threshold Voltage. Thus, an amorphous silicon
`circuit is provided that can measure the threshold voltage of
`the current-providing TFT once perframe time to compensate
`for the aging effect.
`In particular, the pixel layout of the invention can over- 35
`come the threshold Voltage increase of amorphous silicon
`TFT, whilst enabling Voltage programming of the pixel in a
`time that is sufficiently short for large high resolution
`AMOLED displays.
`Each pixel may further comprise an input first transistor
`connected between an input data line and the junction
`between the first and second capacitors. This first transistor
`times the application of a data Voltage to the pixel, for storage
`on the second capacitor.
`Each pixel may further comprise a second transistor con
`nected between the gate and drain of the drive transistor. This
`is used to control the supply of current from the drain (which
`may be connected to a power Supply line) to the first capacitor.
`Thus, by turning on the second transistor, the first capacitor
`can be charged to the gate-source Voltage. The second tran
`sistor may be controlled by a first gate control line which is
`shared between a row of pixels.
`In one example, the first and second capacitors are con
`nected in series between the gate and source of the drive ss
`transistor. A third transistor is then connected across the ter
`minals of the second capacitor, controlled by a third gate
`control line which is shared between a row of pixels. The
`second and third gate control lines comprise a single shared
`control line.
`Alternatively, the first and second capacitors can be con
`nected in series between the gate and drain of the drive tran
`sistor. A third transistor is then connected between the input
`and the source of the drive transistor. This third transistorican
`be controlled by a third gate control line which is shared 65
`between a row of pixels. Again, the second and third gate
`control lines can comprise a single shared control line.
`
`45
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`In each case, the third transistor is used to short out the
`second capacitor so that the first capacitor alone can store the
`gate-source Voltage of the drive transistor.
`Each pixel may further comprise a fourth transistor con
`nected between the drive transistor Source and a ground
`potential line. This is used to act as a drain for current from the
`drive transistor, without illuminating the display element,
`particularly during the pixel programming sequence. The
`fourth transistor can also be controlled by a fourth gate con
`trol line which is shared between a row of pixels. The ground
`potential line may be shared between a row of pixels and
`comprise the fourthgate control line for the fourth transistors
`of an adjacent row of pixels.
`In another arrangement, the capacitor arrangement is con
`nected between the gate and Source of the drive transistor, and
`the source of the drive transistoris connected to a ground line.
`The drain of the drive transistor is connected to one terminal
`of the display element, the other terminal of the display ele
`ment being connected to a power Supply line. This provides a
`circuit with reduced complexity, but the circuit elements are
`on the anode side of the display element.
`Each pixel further may further comprise a second transistor
`connected between the gate and drain of the drive transistor,
`a shorting transistor connected across the terminals of the
`second capacitor, a charging transistor connected between a
`power Supply line and the drain of the drive transistor, and a
`discharging transistor connected between the gate and drain
`of the drive transistor.
`In some circuits of the invention, the terminal of the display
`element opposite to the drive transistor may be connected to
`a Switchable Voltage line. This may be a common cathode line
`which is shared between a row of pixels. The ability to change
`the voltage on this line requires it to be "structured, in par
`ticular into separate conductors for separate rows.
`In order to avoid the need to provide a structured electrode,
`and to allow all pixels of the array to share a common display
`element electrode opposite the drive transistor, each pixel
`may further comprise a second drive transistor. The second
`drive transistor may be provided between a power supply line
`and the first drive transistor, or else between the first drive
`transistor and the display element. In each case, the second
`drive transistor provides a way of preventing illumination of
`the display element during an addressing phase, and without
`needing to change the Voltages on a power Supply line or on a
`common display element terminal.
`The display element may comprise an electroluminescent
`(EL) display element. Such as an electrophosphorescent
`organic electroluminescent display element.
`The invention also provides a method of driving an active
`matrix display device comprising an array of current driven
`light emitting display pixels, each pixel comprising an dis
`play element and an amorphous silicon drive transistor for
`driving a current through the display element, the method
`comprising, for each pixel:
`driving a current through the drive transistorto ground, and
`charging a first capacitor to the resulting gate-source Voltage;
`discharging the first capacitor until the drive transistor
`turns off, the first capacitor thereby storing a threshold volt
`age.
`charging a second capacitor, in series with the first capaci
`tor between the gate and source or drain of the drive transistor,
`to a data input Voltage; and
`using the drive transistor to drive a current through the
`display element using a gate Voltage that is derived from the
`Voltages across the first and second capacitors.
`This method measures a drive transistor threshold voltage
`in each addressing sequence. The method is for an amorphous
`
`Petitioner Samsung Ex. 1010 - Page 14 of 20
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`

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`silicon TFT pixel circuit, particularly with an n-type drive
`TFT, so that a short pixel programming must be achieved to
`enable large displays to be addressed. This can be achieved in
`this method via threshold Voltage measurement in a pipelined
`addressing sequence (namely with the address sequence for
`adjacent rows overlapping in time) or by measuring all
`threshold voltages at the beginning of the frame in the blank
`ing period.
`In the pipelined address sequence, the step of charging a
`second capacitor is carried out by Switching on an address
`transistor connected between a data line and an input to the
`pixel. The address transistor for each pixel in a row is
`Switched on simultaneously by a common row address con
`trol line, and the address transistors for one row of pixels are
`turned on Substantially immediately after the address transis
`tors for an adjacent row are turned off.
`In the blanking period sequence, the first capacitor of each
`pixel is charged to store a respective threshold Voltage of the
`pixel drive transistor at an initial threshold measurement
`period of a display frame period, a pixel driving period of the
`frame period following the threshold measurement period.
`The invention will now be described by way of example
`with reference to the accompanying drawings, in which:
`FIG. 1 shows a known EL display device;
`FIG. 2 is a schematic diagram of a known pixel circuit for
`current-addressing the EL display pixel using an input drive
`Voltage;
`FIG. 3 shows a schematic diagram of a first example of
`pixel layout for a display device of the invention;
`FIG. 4 is a timing diagram for a first method of operation of
`the pixel layout of FIG.3:
`FIG. 5 is a timing diagram for a second method of opera
`tion of the pixel layout of FIG.3:
`FIG. 6 is a timing diagram for a third method of operation
`of the pixel layout of FIG.3:
`FIG. 7 shows a schematic diagram of a second example of
`pixel layout for a display device of the invention;
`FIG. 8 shows example component values for the circuit of
`FIG.3 or 7:
`40
`FIG. 9 shows a schematic diagram of a third example of
`pixel layout with threshold voltage compensation of the
`invention;
`FIG.10 is a timing diagram for operation of the pixel layout
`of FIG.9;
`45
`FIG. 11 shows a schematic diagram of a fourth example of
`pixel layout with threshold voltage compensation of the
`invention;
`FIG. 12 is a timing diagram for operation of the pixel layout
`of FIG. 11.
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`FIG. 13 shows a schematic diagram of a fifth example of
`pixel layout with threshold voltage compensation of the
`invention;
`FIG. 14 is a timing diagram for a first method of operation
`of the pixel layout of FIG. 13.
`FIG. 15 is a timing diagram for a second method of opera
`tion of the pixel layout of FIG. 13.
`FIG.16 is a modification to the timing diagram of FIG. 15:
`FIG. 17 shows a schematic diagram of a sixth example of
`pixel layout with threshold voltage compensation of the
`invention;
`FIG. 18 is a timing diagram for a first method of operation
`of the pixel layout of FIG. 17.
`FIG. 19 is a timing diagram for a second method of opera
`tion of the pixel layout of FIG. 17; and
`FIG. 20 is a modification to the timing diagram of FIG. 18.
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`The same reference numerals are used in different figures
`for the same components, and description of these compo
`nents will not be repeated.
`FIG.3 shows a first pixel arrangement in accordance with
`the invention. In the preferred embodiments, each pixel has an
`electroluminescent (EL) display element 2 and an amorphous
`silicon drive transistor T, in series between a power supply
`line 26 and a cathode line 28. The drive transistor T, is for
`driving a current through the display element 2.
`First and second capacitors C and C are connected in
`series between the gate and source of the drive transistorT.
`A data input to the pixel is provided to the junction 30
`between the first and second capacitors and charges the sec
`ond capacitor C to a pixel data Voltage as will be explained
`below. The first capacitor C is for storing a drive transistor
`threshold Voltage on the first capacitor C.
`An input transistor A is connected between an input data
`line 32 and the junction 30 between the first and second
`capacitors. This first transistor times the application of a data
`Voltage to the pixel, for storage on the second capacitor C.
`A second transistor A is connected between the gate and
`drain of the drive transistor T. This is used to control the
`supply of current from the power supply line 26 to the first
`capacitor C. Thus, by turning on the second transistor A, the
`first capacitor C can be charged to the gate-source Voltage of
`the drive transistor T.
`A third transistor A is connected across the terminals of
`the second capacitor C. This is used to short out the second
`capacitor so that the first capacitor alone can store the gate
`source Voltage of the drive transistor T.
`A fourth transistor A is connected between the source of
`the drive transistor T, and ground. This is used to act as a
`drain for current from the drive transistor, without illuminat
`ing the display element, particularly during the pixel pro
`gramming sequence.
`The capacitor 24 may comprise an additional storage
`capacitor (as in the circuit of FIG. 2) or it may comprise the
`self-capacitance of the display element.
`The transistors A to A are controlled by respective row
`conductors which connect to their gates. As will be explained
`further below, some of the row conductors may be shared. The
`addressing of an array of pixels thus involves addressing rows
`of pixels in turn, and the data line 32 comprises a column
`conductor, so that a full row of pixels is addressed simulta
`neously, with rows being addressed in turn, in conventional
`a.
`The circuit of FIG. 3 can be operated in a number of
`different ways. The basic operation will first be described,
`and the way this can be extended to provide pipelined
`addressing is then explained. Pipelined addressing means
`there is some timing overlap between the control signals of
`adjacent rows.
`Only the drive transistor T, is used in constant current
`mode. All other TFTs A to A in the circuit are used as
`switches that operate on a short duty cycle. Therefore, the
`threshold voltage drift in these devices is small and does not
`affect the circuit performance. The timing diagram is shown
`in FIG. 4. The plots A to A represent the gate Voltages
`applied to the respective transistors. Plot “28” represents the
`voltage applied to cathode line 28, and the clear part of the
`plot “DATA represents the timing of the data signal on the
`data line 32. The hatched area represents the time when data
`is not present on the data line32. It will become apparent from
`the description below that data for other rows of pixels can be
`applied during this time so that data is almost continuously
`applied to the data line 32, giving a pipelined operation.
`
`Petitioner Samsung Ex. 1010 - Page 15 of 20
`
`

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`US 7,564,433 B2
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`The circuit operation is to store the threshold voltage of the
`drive transistorT, on C, and then store the data Voltage on C
`so that the gate-source of T is the data Voltage plus the
`threshold voltage.
`The circuit operation comprises the following steps.
`The cathode (line 28) for the pixels in one row of the
`display is brought to a voltage sufficient to keep the LED
`reversed bias throughout the addressing sequence. This is the
`positive pulse in the plot “28 in FIG. 4.
`Address lines A and As go high to turn on the relevant
`TFTs. This shorts out capacitor C. and connects one side of
`capacitor C to the powerline and the other to the LED anode.
`Address line A, then goes high to turn on its TFT. This
`brings the anode of the LED to ground and creates a large
`gate-source Voltage on the drive TFT T. In this way C is
`charged, but not C as this remains short circuited.
`Address line A, then goes low to turn off the respective
`TFT and the drive TFT T, discharges capacitor C until it
`reaches its threshold voltage. In this way, the threshold volt
`age of the drive transistorT is stored on C. Again, there is no
`Voltage on the second capacitor C.
`A is brought low to isolate the measured threshold voltage
`on the first capacitor C, and A is brought low so that the
`second capacitor C is no longer short-circuited.
`Aa is then brought high again to connect the anode to
`ground. The data Voltage is then applied to the second capaci
`tor C, whilst the input transistoris turned on by the high pulse
`on A.
`Finally. A goes low followed by the cathode been brought
`downto ground. The LED anode then floats up to its operating
`point.
`The cathode can alternatively be brought down to ground
`after A and As have been brought low and before A is taken
`high.
`The addressing sequence can be pipelined so that more
`than one row of pixels can be programmed at any one time.
`Thus, the addressing signals on lines A to A and the row
`wise cathode line 28 can overlap with the same signals for
`different rows. Thus, the length of the addressing sequence
`does not imply long pixel programming times, and the effec
`tive line time is only limited by the time required to charge the
`second capacitor C when the address line A is high. This
`time period is the same as for a standard active matrix
`addressing sequence. The other parts of the addressing mean
`45
`that the overall frame time will only be lengthened slightly by
`the set-up required for the first few rows of the display. How
`ever this set can easily be done within the frame-blanking
`period so the time required for the threshold voltage measure
`ment is not a problem.
`Pipelined addressing is shown in the timing diagrams of
`FIG. 5. The control signals for the transistors A to A have
`been combined into a single plot, but the operation is as
`described with reference to FIG. 4. The “Data' plot in FIG.5
`shows that the data line 32 is used almost continuously to
`provide data to Successive rows.
`In the method of FIGS. 4 and 5, the threshold measurement
`operation is combined with the display operation, so that the
`threshold measurement and display is performed for each row
`of pixels in turn.
`FIG. 6 shows timing diagrams for a method in which the
`threshold Voltages are measured at the beginning of the frame
`for all pixels in the display. The plots in FIG. 6 correspond to
`those in FIG. 4. The advantage of this approach is that a
`structured cathode (namely different cathode lines 28 for
`different rows, as required to implement the method of FIGS.
`4 and 5) is not required, but the disadvantage is that leakage
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`currents may result in some image non-uniformity. The cir
`cuit diagram for this method is still FIG. 3.
`As shown in FIG. 6, the signals A. As A and the signal for
`cathode line 28 in FIG. 6 are supplied