(12) United States Patent
`Casebolt et al.
`
`USOO6625790B1
`(10) Patent No.:
`US 6,625,790 B1
`(45) Date of Patent:
`*Sep. 23, 2003
`
`(54) METHOD AND APPARATUS FOR
`DETECTING THE TYPE OF INTERFACE TO
`
`5,644,790 A 7/1997 Li et al. ..................... 395/883
`5,754,890 A 5/1998 Holmdahl et al. .......... 395/883
`
`(*) Notice:
`
`S. A R. M - - - - - - - - - - - - - - - - - - - - - - - - - - SS
`2Y-1-12
`aO . . . . . . . . . . . . . . . . . . . . . . . . . . .
`5,832,244. A 11/1998 Jolley et al. ................ 395/309
`5. A YE Hashmi et al. ............ 3.
`5,935,224A
`8/1999 Svancareket al... 71063
`6,006,295 A 12/1999 Jones et al. .........
`... 710/62
`6,460,094 B1 10/2002 Hanson et al. ................. 710/8
`
`FOREIGN PATENT DOCUMENTS
`O 860 781 A2
`2/1998
`W 2..
`E.
`f
`f
`OTHER PUBLICATIONS
`Universal Serial Bus Specification, Rev. 1.1, Section 7.1.5:
`Device speed identification, pp. 113 and 114, Sep. 23, 1998.
`
`WHICH A PERPHERAL DEVICE IS
`CONNECTED
`(75) Inventors: Mark W. Casebolt, Seattle, WA (US);
`Lord Nigel Featherston, Redmond,
`WA (US)
`(73) Assignee: Microsoft Corporation, Redmond, WA
`(US)
`EP
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35 W
`U.S.C. 154(b) by 0 days.
`This patent is Subject to a terminal dis-
`claimer.
`(21) Appl. No.: 09/409,683
`(22) Filed:
`Oct. 1, 1999
`
`* cited by examiner
`
`Related U.S. Application Data
`(63) Continuation-i
`t of application No. 09/112,171, filed
`Ola O--a O a
`CaO NO
`2
`, Illed on
`Jul. 8, 1998, inEE Pat. SEP 6,460,094.
`(51) Int. Cl. .................................................. G06F 9/45
`(52) U.S. Cl. ................................. 716/8; 716/9; 716/10;
`71.6/11
`(58) Field of Search ............................. 716/4, 8; 712/1,
`712/230; 710/8, 26, 63, 108, 262, 269,
`305,306; 379/142.15
`
`Primary Examiner Vuthe Siek
`ASSistant Examiner Naum Levin
`(74) Attorney, Agent, or Firm Joseph R. Kelly; Westman,
`Champlin & Kelly, P.A.
`(57)
`ABSTRACT
`A peripheral device is connectable to a computer having one
`of a first interface and a Second interface. The first interface
`communicates with the peripheral device over a differential
`data connection having a first data conductor and a Second
`data conductor. The Second interface communicates with the
`peripheral device over a clock conductor and a Single ended
`References Cited
`data connection which includes a data conductor. The
`U.S. PATENT DOCUMENTS
`peripheral device includes an interface detection component
`a
`coupled to at least one of first and Second communication
`4,500.933 A 2/1985 Chan - - - - - - - - - - - - - - - - - - - - - - - - - - - 360/69
`conductors used to communicate between the peripheral
`4,785,469 A 11/1988 Joshi et al. ................. 375/110
`5's A
`E. RE al."
`s: device and the computer. The interface detection component
`ade el all. . . . . . . . . . . . . . . . . .
`: -
`2 :
`is configured to detect which of the first and Second inter
`5,481,696 A 1/1996 Lompet al. ......
`... 395/500
`5,548,782. A 8/1996 Michael et al. .............
`faces the peripheral device is connected to.
`5,577,213 A 11/1996 Avery et al. ................ 395/280
`5,612,634 A 3/1997 MacKenna ................... 326/62
`33 Claims, 7 Drawing Sheets
`
`(56)
`
`142
`
`\.
`
`WCC
`
`1
`
`ps2
`
`ADAER
`
`INTERFACE CONTROL
`SHOWN NOWSPEED CONFIGURATION
`
`150
`
`144
`
`USBSE
`INTERFACENGINE
`
`
`
`
`
`
`
`PS2
`COMMUNICATIONS
`
`56
`
`
`
`
`
`PS2 DATAUSB
`
`PS2COCKUSB
`
`158
`
`O
`COMputer
`20
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 1 of 15
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 1 of 7
`
`US 6,625,790 B1
`
`-
`OPTICAL
`DISK
`31
`
`REMOVABLE
`STORAGE
`29
`
`
`
`VIDEO ADAPTER
`48
`
`30
`
`Magnetic Disk
`Drive 28
`
`HARD DRIVE 27
`
`R
`MONITOR
`47
`COMPUTER 20
`
`ROM 24
`BOS 26
`
`OPERATING
`SYSTEM 35
`APPLICATION
`PROGRAMS 36 PROGRAM DATA 38
`
`PROGRAM
`MODULE 37
`
`PS2/USB
`PORT 45
`
`SERIAL
`PORT
`INTERFACE
`46
`
`NETWORK
`ADAPTER 53
`
`use.
`
`KEYBOARD MOUSE
`40
`42
`
`REMOTE
`COMPUTER 49
`
`MEMORY 50
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 2 of 15
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 2 of 7
`
`US 6,625,790 B1
`
`USB
`INTERFACE 92
`
`COMPUTER 20
`
`HIGH SPEED USB
`PERPHERAL DEVICE
`
`HOST
`PROCESSOR
`
`
`
`
`
`
`
`
`
`
`
`LOWSPEED USB
`PERIPHERAL DEVICE
`
`PROCESSOR
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 3 of 15
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 3 of 7
`
`US 6,625,790 B1
`
`
`
`1SOH
`
`
`
`}JOSSE OO}}d
`
`
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 4 of 15
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 4 of 7
`
`US 6,625,790 B1
`
`YALNdNOD
`
`0c
`
`OL
`
`PS}
`
`c/Sd
`
`JOAcvl
`
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`TOYLNOS390VSYSLNI
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` NOLLVYNSIANODGaadSMOTNINMOHS
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`“0€SNVLVdcSd
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`8S
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`alsasn
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`cSb
`
`SNOILLVOINNNWOD
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`dSd
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 5 of 15
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 5 of 15
`
`
`
`
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 5 of 7
`
`US 6,625,790 B1
`
`170
`
`COUNTING
`
`CONTACT
`BOUNCE
`DELAY
`
`FIG. 4
`
`172
`
`TERMINAL
`COUNT
`
`178
`
`174
`
`STATE 3 (SE1)
`DETECTED
`
`NOT
`SE1
`
`COUNTING
`
`TERMINAL
`COUNT
`
`ANY WALID USB
`COMMUNICATION
`
`18O
`
`
`
`176
`
`siPS2 DETECTED
`
`siuSB DETECTED
`
`DONE
`
`DONE
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 6 of 15
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 6 of 7
`
`US 6,625,790 B1
`
`
`
`
`
`
`
`
`
`EN|5)NE BOV-RIB LN||
`
`
`BIS 8ST)
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 7 of 15
`
`

`

`U.S. Patent
`
`Sep. 23, 2003
`
`Sheet 7 of 7
`
`US 6,625,790 B1
`
`170
`
`mSec
`
`FIG. 6
`
`72
`
`
`
`202
`
`STATE
`
`COUNTING
`
`TERMINA
`COUNT
`
`
`
`
`
`
`
`200
`
`SiNCERTAN
`USBATTACH(D-)
`
`
`
`
`
`
`
`COUNTING
`
`TERMINAL
`COUNT
`
`
`
`
`
`SE1
`DETECTED
`
`SEO OR )
`KSTATE
`
`
`
`
`
`
`
`
`
`
`
`NOTSE1
`
`COUNTING
`
`
`
`
`
`
`
`
`
`siTOGGLEDM
`ATTACH/DEACH
`
`TOGGLE
`TEST
`FAIL
`
`204
`
`178
`
`USB
`TOGGLE
`PAERERN
`10101
`
`PS/2
`TOGGLE
`PATTERN
`11111
`
`
`
`
`
`Sil JSB
`DETECTED
`
`TERMINAL
`COUNT
`
`
`
`
`
`SiPS2
`DETECTED
`
`176
`
`DONE
`
`180
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 8 of 15
`
`

`

`US 6,625,790 B1
`
`1
`METHOD AND APPARATUS FOR
`DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERIPHERAL DEVICE IS
`CONNECTED
`
`REFERENCE TO CO-PENDING APPLICATION
`The present application is a continuation-in-part of pend
`ing U.S. patent application Ser. No. 09/112,171, filed Jul. 8,
`1998 now U.S. Pat. No. 6,460,094 entitled “METHOD AND
`APPARATUS FOR DETECTING THE TYPE OF INTER
`FACE TO WHICH A PERIPHERAL DEVICE IS CON
`NECTED and assigned to the same assignee as the present
`application, and which is hereby incorporated by reference.
`
`2
`the host computer. The open-collector or open-drain circuit
`(commonly a transistor) is typically implemented inside the
`microprocessor. Another pull-up resistor is required inside
`the peripheral device as well. The peripheral device com
`municating over a PS2 interface is responsible for providing
`a clock signal on the clock conductor, regardless of the
`direction of data flow on the data conductor. The host
`computer pulls the clock conductor to a logic low level to
`inhibit communication from the peripheral device, and it can
`also pull the data conductor low to Signal to the peripheral
`device that the host computer intends to transmit data to the
`peripheral device.
`The USB interface also uses two conductors which
`include differential data Signal conductors D+ and D-.
`In the USB interface at the USB port (i.e., at the host
`computer or USB hub), the two conductors are pulled to a
`logic low level via 15 k ohm resistors. In the peripheral
`device, the D+ conductor is pulled to approximately 3.3
`volts via a 1.5 k ohm resistor if the peripheral device is a
`high-speed USB peripheral device. The D- conductor is
`pulled to 3.3 volts via a 1.5 k ohm resistor if the peripheral
`device is a low-speed USB peripheral device. When a
`peripheral device is attached to the USB port, the USB host
`determines whether it is a low-Speed or high-speed device
`by determining which of the D+ or D- conductors is pulled
`to the logical high level.
`Thus, it can be seen that the two interfaces have different
`hardware structures, and communicate using different Soft
`ware protocols. Traditionally, Separate peripheral devices
`have been provided, one being configured to communicate
`with a USB interface, and the other being configured to
`communicate with a PS2 interface. This requires the manu
`facturer of such peripheral devices to offer two different
`types of peripheral devices in order to Support these two
`different interfaces.
`SUMMARY OF THE INVENTION
`The present invention defines a method and apparatus in
`the peripheral device Such that the peripheral device can
`determine which type of interface it is connected to, and
`configure itself accordingly.
`The peripheral device is connectable to a computer having
`one of a first interface and a Second interface. The first
`interface communicates with a peripheral device over a
`differential data connection having a first data conductor and
`a Second data conductor. The Second interface communi
`cates with the peripheral device over a clock conductor and
`a single-ended data connection, which includes a data con
`ductor. The peripheral device has first and Second commu
`nication conductors configured for connection to the first
`and Second data conductors in the differential data connec
`tion and to the first data conductor in the Single ended data
`connection and the clock conductor. The peripheral device
`includes an interface detection component configured to
`detect which of the first and Second interfaces the peripheral
`device is connected to. The peripheral device also includes
`a controller component configured to communicate between
`the peripheral device and the computer according to a
`protocol corresponding to the detected interface.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of an exemplary environment
`in which an input device in accordance with the present
`invention can be used.
`FIGS. 2A-2C illustrate conventional high-speed and low
`speed USB peripheral devices and a PS2 peripheral device
`coupled to a USB interface and a PS2 interface, respectively.
`
`15
`
`40
`
`45
`
`BACKGROUND OF THE INVENTION
`The present invention relates to a peripheral device con
`nectable to a computer. More particularly, the present inven
`tion relates to a peripheral device configured to detect the
`type of interface to which it is connected.
`A wide variety of peripheral devices are currently con
`figured to be connectable to computers. Such peripheral
`devices commonly include user input devices, Such as
`keyboards, point and click devices (traditionally referred to
`as a computer mouse) and other similar types of devices.
`25
`The computer to which Such devices are connected com
`municates with the devices through one of a number of
`interfaces. Interfaces commonly used to connect to Such
`peripheral devices include a serial interface (Such as an
`RS232 interface) and a PS2 interface. Indeed, the PS2
`interface has long been a Standard for connecting keyboards
`and mice to computers.
`However, recently, another Serial interface referred to as
`a universal serial bus (USB) interface has been introduced.
`35
`The USB interface accommodates a wide variety of com
`puter peripherals, including, for example, keyboards and
`mice. However, a conventional computer is typically pro
`vided with only one interface (such as a PS2 or USB
`interface) for communication with peripheral devices.
`Therefore, if the computer is provided with a PS2 interface,
`the keyboard or mouse must be configured to Support
`communication with the computer according to a protocol
`defined by the PS2 interface. Similarly, if the computer is
`provided with the USB interface, the keyboard or mouse
`must be configured to communicate according to a protocol
`defined by the USB interface.
`In order to do this, a conventional computer peripheral
`device contains a microprocessor which runs a Software
`program to carry out the functions of that particular periph
`eral device. In the device Such as a keyboard or mouse, the
`Software program includes an interface between the periph
`eral device and the host computer, through which the periph
`eral device communicates with the host computer. Such
`communication often includes receiving commands from
`the host computer and transmitting data and Status informa
`tion to the host computer.
`AS discussed above, the PS2 and USB interfaces have
`different hardware and Software requirements, which must
`be met by the microprocessor in the peripheral device So that
`60
`the peripheral device can communicate with the host com
`puter. The PS2 interface uses two conductors which include
`a separate clock conductor and a separate data conductor.
`These conductors are driven by the computer through an
`open-collector or open-drain circuit, and have a pull-up
`resistor (typically in the range of 2 k ohms to 10 k ohms)
`pulling the conductor to a rail voltage (such as VCC) inside
`
`50
`
`55
`
`65
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 9 of 15
`
`

`

`3
`FIG. 3 illustrates a peripheral device in accordance with
`one embodiment of the present invention.
`FIG. 4 is a State diagram illustrating the operation of the
`peripheral device shown in FIG. 3.
`FIG. 5 is a block diagram of a peripheral device in
`accordance with another embodiment of the present inven
`tion.
`FIG. 6 is a State diagram illustrating the operation of the
`peripheral device shown in FIG. 5.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`The present invention includes a method and apparatus,
`implemented in a peripheral device, by which the peripheral
`device detects whether it is coupled to a PS2 interface or a
`USB interface. A peripheral device, in accordance with one
`aspect of the present invention, is configured initially to
`expect a first interface and Senses the State of the interface
`to configure itself appropriately.
`FIG. 1 and the related discussion are intended to provide
`a brief, general description of a Suitable computing envi
`ronment in which the invention may be implemented.
`Although not required, the invention will be described, at
`least in part, in the general context of computer-executable
`instructions, Such as program modules, being executed by a
`personal computer or other computing device. Generally,
`program modules include routine programs, objects,
`components, data Structures, etc. that perform particular
`tasks or implement particular abstract data types. Moreover,
`those skilled in the art will appreciate that the invention may
`be practiced with other computer System configurations,
`including hand-held devices, multiprocessor Systems,
`microprocessor-based or programmable consumer
`electronics, network PCs, minicomputers, mainframe
`computers, and the like. The invention is also applicable in
`distributed computing environments where tasks are per
`formed by remote processing devices that are linked through
`a communications network. In a distributed computing
`environment, program modules may be located in both local
`and remote memory Storage devices.
`With reference to FIG. 1, an exemplary environment for
`the invention includes a general purpose computing device
`in the form of a conventional personal computer 20, includ
`ing processing unit 21, a System memory 22, and a System
`buS 23 that couples various System components including
`the System memory to the processing unit 21. The System
`bus 23 may be any of several types of bus structures
`including a memory bus or memory controller, a peripheral
`bus, and a local bus using any of a variety of bus architec
`tures. The System memory includes read only memory
`(ROM) 24 a random access memory (RAM) 25. A basic
`input/output 26 (BIOS), containing the basic routine that
`helps to transfer information between elements within the
`personal computer 20, Such as during Start-up, is Stored in
`ROM 24. The personal computer 20 further includes a hard
`disk drive 27 for reading from and writing to a hard disk (not
`shown), a magnetic disk drive 28 for reading from or writing
`to removable magnetic disk 29, and an optical disk drive 30
`for reading from or writing to a removable optical disk 31
`such as a CD ROM or other optical media. The hard disk
`drive 27, magnetic disk drive 28, and optical disk drive 30
`are connected to the system bus 23 by a hard disk drive
`interface 32, magnetic disk drive interface 33, and an optical
`drive interface 34, respectively. The drives and the associ
`ated computer-readable media provide nonvolatile Storage
`of computer readable instructions, data structures, program
`modules and other data for the personal computer 20.
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 6,625,790 B1
`
`4
`Although the exemplary environment described herein
`employs a hard disk, a removable magnetic disk 29 and a
`removable optical disk 31, it should be appreciated by those
`skilled in the art that other types of computer readable media
`which can Store data that is accessible by a computer, Such
`as magnetic cassettes, flash memory cards, digital Video
`disks, Bernoulli cartridges, random access memory (RAM),
`read only memory (ROM), and the like, may also be used in
`the exemplary operating environment.
`A number of program modules may be stored on the hard
`disk, magnetic disk 29, optical disk 31, ROM 24 or RAM 25,
`including an operating System 35, one or more application
`programs 36, other program modules 37, and program data
`38. A user may enter commands and information into the
`personal computer 20 through input devices Such as a
`keyboard 40 and pointing device (or mouse) 42. Other input
`devices (not shown) may include a microphone, joystick,
`game pad, Satellite dish, Scanner, or the like. These and other
`input devices are often connected to the processing unit 21
`through one of a plurality of ports. For instance, keyboard 40
`and mouse 42 are connected through a PS2 or USB interface
`45. In the illustrative embodiment, interface (or port) 45 is
`coupled to the System buS 23. User input devices may also
`be connected by other interfaces, Such as a Sound card, a
`parallel port, or a game port. A monitor 47 or other type of
`display device is also connected to the System buS 23 via an
`interface, Such as a Video adapter 48. In addition to the
`monitor 47, personal computers may typically include other
`peripheral output devices Such as Speakers and printers (not
`shown).
`The personal computer 20 may operate in a networked
`environment using logic connections to one or more remote
`computers, Such as a remote computer 49. The remote
`computer 49 may be another personal computer, a Server, a
`router, a network PC, a peer device or other network node,
`and typically includes many or all of the elements described
`above relative to the personal computer 20, although only a
`memory storage device 50 has been illustrated in FIG.1. The
`logic connections depicted in FIG. 1 include a local area
`network (LAN) 51 and a wide area network (WAN).52. Such
`networking environments are commonplace in offices,
`enterprise-wide computer network intranets and the Internet.
`When used in a LAN networking environment, the per
`sonal computer 20 is connected to the local area network 51
`through a network interface or adapter 53. When used in a
`WAN networking environment, the personal computer 20
`typically includes a modem 54 or other means for establish
`ing communications over the wide area network 52, Such as
`the Internet. The modem 54, which may be internal or
`external, is connected to the System buS 23 via the Serial port
`interface 46. In a network environment, program modules
`depicted relative to the personal computer 20, or portions
`thereof, may be Stored in the remote memory Storage
`devices. It will be appreciated that the network connections
`shown are exemplary and other means of establishing a
`communications link between the computerS may be used.
`FIGS. 2A-2C illustrate conventional peripheral devices
`coupled to conventional interfaces. FIG. 2A illustrates a
`high-speed USB peripheral device 100 connected through
`USB interface 102 to CPU 21 of host computer 20. It should
`be noted that high-speed USB peripheral device 100 can be
`any Suitable peripheral device, Such as keyboard 40 or
`mouse 42 or another suitable peripheral device. Peripheral
`device 100 is connected to USB interface 102 and commu
`nicates therewith over two conductors 104 and 106. Con
`ductors 104 and 106 are connected to corresponding con
`ductors 108 and 110 through USB connector 112.
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 10 of 15
`
`

`

`S
`Conductors 104 and 106 carry signals denoted D+ and D
`in a high-speed USB device. Signals D+ and D- are differ
`ential digital data signals with which peripheral device 100
`communicates with computer 20.
`In a high-speed USB arrangement, conductor 104, which
`carries signal D+, is pulled to a logical high level (Such as
`a +5 Volt Supply or other desired Supply Voltage potential
`hereinafter referred to as VCC or the VCC rail) by a pull-up
`resistor 114. Resistor 114 is preferably valued such that the
`voltage potential to which conductor 104 is pulled is
`approximately 3.3 volts. Therefore, resistor 114 can, for
`instance, be a 7.5 kohm resistor connected to a 5 volt VCC
`rail.
`In USB interface 102 on computer 20, both conductors
`108 and 110 (which correspond to the D+ and D-signals)
`are pulled to a logic low level by two 15 kohm resistors 116
`and 118. When peripheral device 100 is initially attached to
`computer 20 through USB interface 102, computer 20 can
`determine that peripheral device 100 is a high-speed USB
`peripheral device because the conductor 104 corresponding
`to Signal D+ is pulled to a logical high level, while conductor
`106 which corresponds to signal D- is not.
`FIG. 2B illustrates the connection of a low-speed USB
`peripheral device 120 to computer 20. Some items are
`25
`similar to those shown in FIG. 2A, and are similarly num
`bered. However, rather than having conductor 104
`(corresponding to signal D+) pulled to a logical high level
`with resistor 114, conductor 106 (which corresponds to
`Signal D-) is pulled to a logical high level with resistor 122.
`Thus, computer 20 determines that peripheral device 120 is
`a low-speed USB device.
`FIG. 2C illustrates another peripheral device 124 con
`nected to computer 20. Peripheral device 124 is configured
`to communicate with computer 20 through a PS2 interface
`35
`126. PS2 peripheral device 124 communicates with com
`puter 20 over a pair of conductors 104 and 106, which
`correspond to a data Signal and a clock Signal. Conductors
`104 and 106 are connected to transistors 131 and 133, which
`are configured as open-collector or open-drain Switches
`controlled by the microprocessor in peripheral device 124.
`Conductors 104 and 106 are connected to conductors 108
`and 110 through PS2 connector 128. Conductors 104 and
`106 are pulled to a logical high level at peripheral device 124
`by resistors 130 and 132 which are typically in a 2 k-10 k
`ohm range.
`In PS2 interface 126, conductors 108 and 110 are also
`pulled to a logical high level by resistors 134 and 136, which
`are also typically in a 2 k-10 k ohm range. Conductors 108
`and 110 are also coupled to ground by transistors 138 and
`140, which are typically open-drain or open-collector and
`driven by appropriate circuitry in processor 21. It should
`also be noted that transistors 138 and 140 can typically be
`implemented inside processor 21, or discretely.
`With the open-collector configured interface, when a
`logical 1 is written to either conductor 108 or 110, the
`conductor is not actively driven high. Instead, it is pulled
`high, to nearly the rail Voltage VCC, via the pull-up resistors
`134 and 136. In this manner, either host processor 21 or
`peripheral device 124 can drive the conductor low without
`the concern of the conductor already being actively driven
`high.
`Peripheral device 124 is responsible for providing the
`clock signal over conductors 106 and 110, to host processor
`21, regardless of the direction of data flow over conductors
`104 and 108. Host processor 21 can pull the conductor 110
`carrying the clock Signal low by controlling transistor 140
`
`6
`appropriately. This inhibits communication from peripheral
`device 124. Host processor 21 can also pull the data con
`ductor 108 low by manipulating transistor 138 in order to
`Signal peripheral device 124 that host processor 21 intends
`to transmit data.
`FIG. 3 illustrates a peripheral device 142 in accordance
`with one embodiment of the present invention. Peripheral
`device 142 includes a communication controller 144 which,
`in turn, includes a USBSIE interface engine 146 and a PS2
`communications controller 148. Peripheral device 142 also,
`in one illustrative embodiment, includes pull-up resistor 150
`which pulls the PS2 data/USB D-signal line to a predeter
`mined voltage potential (such as VCC). Peripheral device
`142 also includes, in one illustrative embodiment, a cable
`with USB connector 152.
`It should be noted that, in FIG. 3, the PS2 data and USB
`D- lines are indicated as being carried by Signal line or
`conductor 160 while the PS2 clock and USB D+ signals are
`indicated as being carried by conductor 158. Of course, the
`USB D+ signal can be carried by the same conductor as the
`PS2 data signal and the USB D-signal can be carried by the
`Same conductor as the PS2 clock signal. Also, while pull-up
`resistor 150 is shown coupled to conductor 160 (which
`corresponds to the USB D-signal), it could also be coupled
`to the conductor which corresponds to the USB D+ signal
`where the USB device is a high speed device, rather than a
`low Speed device. However, the present discussion will
`proceed with respect to the embodiment illustrated in FIG.
`3, for the sake of simplicity.
`FIG.3 further illustrates a PS2 adapter 154 in accordance
`with one embodiment of the present invention. Adapter 154
`includes a USB connector 156 which mates with USB
`connector 152. Adapter 154 connects the signal lines 158
`and 160 to an output connector 162 which is suitable for
`being coupled to a connector or cable from computer 20. In
`one illustrative embodiment, connectors 152 and 156 are
`implemented as a USB Series A plug and receptacle, respec
`tively. Connector 162 is implemented as a PS2 mini-din
`COnnectOr.
`Adapter 154, in the illustrative embodiment, also includes
`a pair of pull-up resistors 164 and 166. When adapter 154 is
`coupled to peripheral device 142, pull-up resistor 164 pulls
`the PS2 clock/USB D+ signal line to VCC. Resistor 166
`pulls the PS2 data/USB D-signal line to VCC as well. The
`pull-ups in adapter 154 eliminate the necessity for the
`microprocessor on peripheral device 142 to control these
`dynamically. This Saves firmware code Space and also
`reduces necessary pin count on the microprocessor by one or
`two pins. This provides a significant cost Savings.
`Table 1 below illustrates the configuration of the two
`signals provided by both USB and PS2 devices. Table 1
`illustrates the signals for a USB low speed device.
`
`TABLE 1.
`
`D+/CLK
`
`D-DAT USB
`
`L
`
`L
`
`H
`
`H
`
`L
`
`H
`
`L
`
`H
`
`SEO
`(Single
`Ended O)
`or Reset
`J, Idle
`
`K, Ximit
`Resume
`SE1
`
`PS/2
`
`Host
`Inhibit
`
`Host
`Inhibit
`Host Ximit
`
`Idle,
`
`I/O
`State
`
`O
`
`1.
`
`2
`
`3
`
`US 6,625,790 B1
`
`15
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Petitioners Ex. 1015
`IPR USP 8,624,550
`Page 11 of 15
`
`

`

`US 6,625,790 B1
`
`TABLE 1-continued
`
`I/O
`State
`
`D+/CLK
`
`D-fDAT USB
`
`PS/2
`
`(Single
`Ended 1)
`
`Confirm
`Connect
`
`8
`computers were discovered to hold PS2 interface commu
`nication lines in an inhibited State for extensive periods of
`time, even on power-up. This can make it difficult to detect
`and respond to initial communication Sequences in a timely
`manner. Similarly, where a peripheral device 142 is “hot
`plugged' into the host computer, the inhibition of the PS2
`communication by the host computer can make it difficult
`for the detection System discussed above to make an imme
`diate detection.
`Therefore, the present invention can be implemented
`according to a second embodiment as well. FIG. 5 illustrates
`peripheral device 182 which is implemented in accordance
`with a second illustrative embodiment of the present inven
`tion. A number of the items illustrated in FIG. 5 are similar
`to those found in FIG. 3, and are similarly numbered.
`However, in the embodiment illustrated in FIG. 5, peripheral
`device 182 includes communication controller 184 which
`not only includes USB interface engine 146 and PS2 com
`munications component 148, but also includes resistor pull
`up control component 186. Control component 186 provides
`an output 188 to a switch 190.
`In the embodiment illustrated in FIG. 5, Switch 190 is
`implemented as a bi-polar transistor 192 which is coupled
`between pull-up resistor 150 and a predetermined voltage
`potential (in this case VCC). This provides control compo
`nent 186 with the ability to either enable pull-up resistor 150
`by connecting pull-up resistor 150 to VCC, or to disable
`pull-up resistor 150, by effectively disconnecting pull-up
`resistor 150 from VCC.
`FIG. 6 is a state diagram which better illustrates the
`operation of peripheral device 182 shown in FIG. 5. A
`number of the states are similar to those shown in FIG. 4,
`and are similarly numbered. Therefore, controller 184 first
`begins the initialization routine at state 170. Controller 184
`also waits, after power-up, for a predetermined time period
`in order to accommodate for contact bounce. This is indi
`cated by state 172. After the desired delay, controller 184
`enters indeterminate state 200.
`Controller 184 (and specifically pull-up control compo
`nent 186) then performs a USBattach operation by enabling
`pull-up resistor 150. In other words, control component 186
`provides an output to bi-polar transistor 192 which effec
`tively connects pull-up resistor 150 to VCC. It will be noted
`that this does not effect PS2 operation since, where a PS2
`interface is provided, adapter 154 is already in place which
`includes its own pull-up resistor 166 on signal line 160.
`Controller 184 then senses the logic level on both signal
`lines 158 and 160 with a level detector Such as that set out
`in co-pending U.S. patent application Ser. No. 09/112,171,
`filed Jul. 8, 1998 entitled “METHOD AND APPARATUS
`FOR DETECTING THE TYPE OF INTERFACE TO
`WHICH A PERIPHERAL DEVICE IS CONNECTED",
`which is hereby fully incorporated by reference.
`AS with the detection routine illustrated in FIG. 4, if
`controller 184 detects a SE1 condition, and that condition
`exists for a predetermined amount of time (Such as three
`milliseconds), controller 184 determines that it has detected
`a PS2 interface. This is indicated by states 178 and 180.
`However, if an SE1 condition is not detected but an SEO
`or K State is detected, controller 184 remains in indetermi
`nate state 200 and simply waits for this condition to change.
`This is because no determination can be made while the
`signal lines 158 and 160 are in the SEO or K state.
`If, on the other hand, while controller 184 is in indeter
`minate state 200, it detects a J state, it moves to state 202 and
`determines whether the J State exists for a predetermined
`
`FIG. 4 is a State diagram illustrating the operation of
`peripheral device 142 shown in FIG.3 and will be described
`with reference to FIG. 3 and Table 1. Communication
`controller 144 begins by Starting the initialization process, as
`indicated by state 170 in FIG. 4. After power-up, commu
`nication controller 144 waits for a time-out period (Such as
`10-100 milliseconds). This allows time for contact bounce
`during mating of the connectors illustrated in FIG. 3. This is
`indicated by state 172 in FIG. 4.
`After reaching the designated time-out period, communi
`cation controller 144 enters an indeterminate state 174. In
`the indeterminate state, controller 144 “assumes” that it is
`connected to a USB interface. In other words, controller 144
`is configured to receive a valid USB communication, or
`USB reset signaling. In the event that controller 144 is in the
`indeterminate state 174 and receives valid USB 1.0 or 1.1
`communications, controller 144 determines that it has
`detected a USB interface and moves to state 176. The USB
`interface engine 146 in controller 144 then takes over
`communications between peripheral device 142 and com
`puter 20.
`In the indeterminate state 174, controller 144 also peri
`odically polls for the presence of a PS2 interface by moni
`toring the state of signal lines 158 and 160. In one specific
`embodiment, controller 144 looks for