R. JACOB (JAKE) BAKER, PH.D., P.E.
`
`Professor of Electrical and Computer Engineering
`Department of Electrical and Computer Engineering
`
`6775 Agave Azul Court
`Las Vegas, NV 89120
`
`(725) 777-3755 (Home Office)
`(208) 850-0517 (Cell)
`
`Email: rjacobbaker@gmail.com
`Website: http://CMOSedu.com/jbaker/jbaker.htm
`
`EDUCATION
`Ph.D. in Electrical Engineering; December 1993; University of Nevada, Reno, GPA 4.0/4.0. Dissertation Title: Applying
`power MOSFETs to the design of electronic and electro-optic instrumentation.
`M.S. and B.S. in Electrical Engineering: May 1986 and May 1988; University of Nevada, Las Vegas. Thesis Title: Three-
`dimensional simulation of a MOSFET including the effects of gate oxide charge.
`ACADEMIC EXPERIENCE
`January 1991 - Present: Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas from
`August 2012 to present. From January 2000 to July 2012 held various positions at Boise State University including:
`Professor (2003 – 2012), Department Chair (2004 - 2007), and tenured Associate Professor (2000 - 2003). From
`August 1993 to January 2000 was a tenured/tenure track faculty member at the University of Idaho: Assistant
`Professor (1993 - 1998) and then tenured Associate Professor (1998 - 2000). Lastly, from January 1991 to May
`1993 held adjunct faculty positions in the departments of Electrical Engineering at the University of Nevada, Las
`Vegas and Reno. Additional details:
`Research is focused on analog and mixed-signal integrated circuit fabrication and design. Worked with multi-
`
`disciplinary teams (civil engineering, biology, materials science, etc.) on projects that have been funded by
`EPA, DARPA, NASA, Army, DMEA, Navy, and the AFRL.
`Current and past research and development interests are:
`o Design and packaging of electrical/optical systems (e.g., LiDARs/LADARs) using LEDs, semiconductor
`lasers, lens for focusing and directing light, integrated circuits, and associated control and communication
`systems/circuits.
`o Capacitive sensing techniques using delta-sigma modulation and interfacing to sensors
`o Design of high-voltage and energy switching circuits
`o Circuit design and fabrication for the control, use, and storage of renewable energy using thermoelectric
`generators
`o Design of electrical/biological/optical circuits and systems using electrowetting on dielectric for
`automating and controlling biological experiments
`o Design of readout integrated circuits (ROICs) for use with focal plane arrays (FPAs)
`o Heterogeneous integration of III-V photonic devices (e.g. FPAs and VCSELs) with CMOS
`o Methods (e.g., 3D packaging and capacitive
`in
`interconnects) to reduce power consumption
`semiconductor memories, memory modules, and digital systems using custom and non-custom (e.g.,
`FPGAs) implementations
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`o Analog and mixed-signal circuit fabrication and design for communication systems, synchronization,
`energy storage, data conversion, and interfaces
`o The design of writing and sensing circuitry for emerging nonvolatile memory technologies, focal planes,
`and displays (arrays) in nascent nanotechnologies (e.g. magnetic, chalcogenide)
`o Reconfigurable electronics design and fabrication using nascent memory technologies such as the
`memristor to implement FPGAs
`o Finding an electronic, that is, no mechanical component, replacement for the hard disk drive using nascent
`fabrication technologies
`o Power electronics circuit design for consumers and consumer electronics including power management
`and adaptive control to reduce power consumption
`o Design of bandpass delta-sigma modulators for IQ demodulation in wireless communication systems in
`OFDM, WiFi, 802.11, Bluetooth, 3G, 4G, etc.
`o University prototyping, fabricating, and packaging of integrated circuits
`Led, as chair, the department in graduate curriculum (MS and PhD), program development, and ABET
`accreditation visits.
` Worked with established and start-up companies to provide technical expertise and identify employment
`opportunities for students.
` Held various leadership and service positions including: ECE chair, graduate coordinator, college curriculum
`committee (chair), promotion and tenure committee, scholarly activities committee, faculty search
`committee, university level search committees, etc. Collaborate with College of Engineering faculty on joint
`research projects.
`Taught courses in circuits, analog IC design, digital VLSI design and fabrication, and mixed-signal integrated
`circuit design to both on- and, via the Internet, off-campus students. Research emphasis in integrated circuit
`design using nascent technologies.
`INDUSTRIAL EXPERIENCE
`2013 - present: Working with Freedom Photonics, Santa Barbara, CA, on the integration, fabrication and design, of
`optoelectronics with CMOS integrated circuits. Work includes the design of compact optical transceivers for range
`finding applications, high-efficiency integrated silicon avalanche photodetectors for quantum key receivers,
`Geiger mode SiGe receivers for long-range communications, cryptography, and the fabrication of near-infrared
`focal plane arrays. Packaging and testing of numerous chips fabricated in both CMOS and SiGe technologies using
`LEDs, ILDs, PIN, APDs, and ROICs.
`2017 - 2019: Worked with Vorpal Research Systems, Las Vegas, NV on the design of integrated circuit electronics and
`optoelectronics for optical transceivers used in LIDARs/LADARs.
`2016 - 2019: Worked with Attollo Engineering on the design of transient digitizers for the capture of high-speed signals
`for range finders using LEDs and lasers in compact optical transceivers.
`2013 - 2018: Working with Mission Support and Test Services, LLC (MSTS, formerly National Security Technologies,
`LLC, [NSTec]) on the Design and Fabrication of Integrated electrical/photonic application specific integrated circuit
`(ASIC) design for use in the implementation of diagnostic instrumentation.
`2013 - 2015: Consultant for OmniVision. Working on integrating CMOS image sensors (CIS) with memory for very high-
`speed consumer imager products. Design specialty DRAM, high-speed interfaces between CIS and DRAM,
`packaging techniques to pair the CIS with DRAM.
`2010 - 2013: Worked with Arete’ Associates on the design of high-speed compressive transimpedance amplifiers for
`LADAR projects and the design of ROIC unit cells. Work funded by the U. S. Air Force.
`2013: Cirque, Inc. Consulting on the design of analog-to-digital interfaces for capacitive touch displays and pads.
`2012: Consultant at Lockheed-Martin Santa Barbara Focal Plane Array. CMOS circuit design and fabrication for the
`development and manufacture of infrared components and imaging systems with an emphasis on highest
`sensitivity Indium Antimonide (InSb) focal plane arrays (FPAs) in linear through large staring formats. Product
`groups include FPAs, integrated dewar assemblies (IDCAs), camera heads, high-speed interfaces between image
`processors and imaging systems, and infrared imaging systems.
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`R. JACOB BAKER, PH.D., P.E.
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`2010 - 2012: Working with Aerius Photonics (and then FLIR Inc. when Aerius was purchase by FLIR) on the design of
`Focal Plane Arrays funded (SBIRs and STTRs) by the U.S. Air Force, Navy, and Army. Experience with readout
`integrated circuits (ROICs) and the design/layout of photodetectors in standard CMOS.
`2009 - 2010: Sun Microsystems, Inc. (and then Oracle) VLSI research group. Provided consulting on memory circuit
`design/fabrication and proximity connection (PxC) interfaces to DRAMs and SRAMs for lower power, 3D
`packaging, for memory modules and controllers implemented with FPGAs and custom ASICs.
`2009 - 2010: Contour Semiconductor, Inc. Design of NMOS voltage and current references as well as the design of a
`charge pump for an NMOS memory chip.
`1994 - 2008: Affiliate faculty (Senior Designer), Micron Technology. Designed CMOS circuits for DRAMs including DLLs,
`PLLs for embedded graphics chips, voltage references and regulators, data converters, field-emitting display
`drivers, sensing for MRAM (using delta-sigma data conversion topologies), SRAMs, RFIDs, CMOS active pixel
`imagers and sensors, power supply design (linear and switching), input buffers, etc. Worked on a joint research
`project between Micron and HP labs in magnetic memory fabrication and design using the MTJ memory cell.
`Worked on numerous technologies ranging from LED lighting to medical imaging using CMOS image sensors (too
`many to list) resulting in numerous US patents (see following list). Considerable experience working with product
`engineering to ensure high-yield from the production line from fabrication to test. Co-authored a book on DRAM
`circuit design through the support of Micron. Gained knowledge in the entire memory design process from
`fabrication to packaging. Developed, designed, and tested circuit design techniques for multi-level cell (MLC) Flash
`memory using signal processing.
`January 2008: Consultant for Nascentric located in Austin, TX. Provide directions on circuit operation (DRAM, memory,
`and mixed-signal) for fast SPICE circuit simulations.
`May 1997 - May 1999: Consultant for Tower Semiconductor, Haifa, Israel. Designed CMOS integrated circuit cells for
`various modem chips, interfaces, and serial buses including USB circuits, charging circuits based upon power
`up/down circuits using an MOS or bandgap reference, pre-amplifiers, comparators, etc.
`Summer 1998: Consultant for Amkor Wafer Fabrication Services, Micron Technology, and Rendition, Inc., Design PLLs
`and DLLs for custom ASICs and a graphics controller chip.
`Summers 1994 - 1995: Micron Display Inc. Designing phase locked loop for generating a pixel clock for field emitting
`displays and a NTSC to RGB circuit on chip in NMOS. These displays are miniature color displays for camcorder and
`wrist watch size color television. Worked on the fabrication and design of video peripheral circuits for these
`displays.
`September - October 1993: Lawrence Berkeley Laboratory. Designed and constructed a 40 A, 2 kV power MOSFET
`pulse generator with a 3 ns rise-time and 8 ns fall-time for driving Helmholtz coils.
`Summer 1993: Lawrence Livermore National Laboratory, Nova Laser Program. Researched picosecond
`instrumentation, including time-domain design for impulse radar and imaging.
`December 1985 - June 1993: (from July 1992 to June 1993 employed as a consultant while finishing up my Ph.D.),
`E.G.&G. Energy Measurements Inc., Nevada, Senior Electronics Design Engineer. Responsible for the design and
`manufacturing of instrumentation used in support of Lawrence Livermore National Laboratory's Nuclear Test
`Program. Responsible for designing and fabricating over 30 electronic and electro-optic instruments including:
`CCD camera design, communication networks, fiber optic transmitters employing high speed laser drive
`electronics, receivers employing envelop tracking for DC voltage restoration and regeneration of received
`information, receiver low noise amplifier design, frame synchronizers for re-assembling transmitted images, high-
`speed SRAM memory system design with battery back-up, calibration equipment design such as a tunnel diode
`pulse generator for testing compensation of oscilloscopes and DAC design for calibrating CCD readout electronics,
`power supply and battery charger designs, sweep circuits for streak cameras, Pockel’s cell drive electronics,
`vertical amplifier design using HBTs for analog oscilloscopes used at the Nevada Test Site, and 10 kV ramp designs
`using a planar triode to name some of the designs.
`This position provided considerable fundamental grounding in EE with a broad exposure ranging from the design
`of PC boards to, for example, the design of cable equalizers. Summarizing, gained experience in circuit design
`technologies including: bipolar, vacuum tubes (planar triodes for high voltages), hybrid integrated circuit
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`fabrication and design, GaAs (high speed logic and HBTs), krytrons, power MOSFETs, microwave techniques,
`power supplies, fiber optic transmitters/receivers, etc.
`Summer 1985: Reynolds Electrical Engineering Company, Las Vegas, Nevada. Gained hands on experience in primary
`and secondary power system design, installation and trouble-shooting electric motors on mining equipment.
`MEMBERSHIPS IN PROFESSIONAL AND SCHOLARLY ORGANIZATIONS
`IEEE (student, 1983; member, 1988; senior member, 1997; Fellow, 2013)
`Member of the honor societies Eta Kappa Nu and Tau Beta Pi
`Licensed Professional Engineer
`HONORS AND AWARDS
`Consolidated Students of the University of Nevada, Las Vegas (CSUN) Faculty Award, 2017
`
`Tau Beta Pi UNLV Outstanding Professor of the Year in 2013, 2014, 2015 and 2016
`
`UNLV ECE Department Distinguished Professor of the Year in 2015
`
`IEEE Fellow for contributions to the design of memory circuits - 2013
`
`Distinguished Lecturer for the IEEE Solid-State Circuits Society, 2012 - 2015
`
`IEEE Circuits and Systems (CAS) Education Award - 2011
`
`Twice elected to the Administrative Committee of the Solid-State Circuits Society, 2011 - 2016
`
`Frederick Emmons Terman Award from the American Society of Engineering Education - 2007
`
`President’s Research and Scholarship Award, Boise State University - 2005
`
`Honored Faculty Member - Boise State University Top Ten Scholar/Alumni Association 2003
`
` Outstanding Department of Electrical Engineering faculty, Boise State 2001
`Recipient of the IEEE Power Electronics Society’s Best Paper Award in 2000
`
`University of Idaho, Department of Electrical Engineering outstanding researcher award, 1998-99
`
`University of Idaho, College of Engineering Outstanding Young Faculty award, 1996-97
`
`
`SERVICE
`Reviewer for IEEE transactions on solid-state circuits, circuits and devices magazine, education, instrumentation,
`nanotechnology, VLSI, etc. Reviewer for several American Institute of Physics journals as well (Review of Scientific
`Instruments, Applied Physics letters, etc.) Board member of the IEEE press (reviewed dozens of books and book
`proposals). Reviewer for the National Institutes of Health. Technology editor and then Editor-in-Chief for the Solid-
`State Circuits Magazine.
`Led the Department on ABET visits, curriculum and policy development, and new program development including the
`PhD in electrical and computer engineering. Provided significant University and College service in infrastructure
`development, Dean searches, VP searches, and growth of academic programs. Provided university/industry
`interactions including starting the ECE department’s advisory board. Held positions as the ECE department
`Masters graduate coordinator and coordinator for the Sophomore Outcomes Assessment Test (SOAT).
`Also currently serves, or has served, on the IEEE Press Editorial Board (1999-2004), as a member of the first Academic
`Committee of the State Key Laboratory of Analog and Mixed-Signal VLSI at the University of Macau, as editor for
`the Wiley-IEEE Press Book Series on Microelectronic Systems (2010-2018), on the IEEE Solid-State Circuits Society
`(SSCS) Administrative Committee (2011-2016), as an Advisory Professor to the School of Electronic and
`Information Engineering at Beijing Jiaotong University, as a Distinguished Lecturer for the SSCS (2012-2015), as
`the Technical Program Chair for the IEEE 58th 2015 International Midwest Symposium on Circuits and Systems,
`MWSCAS 2015, as advisor for the student branch of the IEEE at UNLV (2013-present), and as the Technology Editor
`(2012-2014) and Editor-in-Chief (2015-2020) for the IEEE Solid-State Circuits Magazine,.
`ARMED FORCES
`6 years United States Marine Corps reserves (Fox Company, 2nd Battalion, 23rd Marines, 4th Marine Division),
`Honorable Discharge, October 23, 1987. Military Occupational Specialty was Machine Gunner (MOS 0331)
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`R. JACOB BAKER, PH.D., P.E.
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`TEXTBOOKS AUTHORED
`Baker, R. J., "CMOS Circuit Design, Layout and Simulation, Fourth Edition" Wiley-IEEE Press, 1234 pages. ISBN
`9781119481515 (2019) Over 50,000 copies of this book in print. (Third Edition published in 2010, Revised Second
`Edition published in 2008, and Second Edition Published in 2005)
`Baker, R. J., “CMOS Mixed-Signal Circuit Design,” Wiley-IEEE, 329 pages. ISBN 978-0470290262 (second edition, 2009)
`and ISBN 9780471227540 (First Edition published in 2002)
`Keeth, B., Baker, R. J., Johnson, B., and Lin, F., “DRAM Circuit Design: Fundamental and High-Speed Topics”, Wiley-
`IEEE, 2008, 201 pages. ISBN: 9780470184752
`Keeth, B. and Baker, R. J., “DRAM Circuit Design: A Tutorial”, Wiley-IEEE, 2001, 201 pages. ISBN 0780360141
`Baker, R. J., Li, H.W., and Boyce, D.E. "CMOS Circuit Design, Layout and Simulation," Wiley-IEEE, 1998, 904 pages. ISBN
`9780780334168
`BOOKS, OTHER (edited, chapters, etc.)
`Saxena, V. and Baker, R. J., “Analog and Digital VLSI,” chapter in the CRC Handbook on Industrial Electronics, edited by
`J. D. Irwin and B. D. Wilamowski, CRC Press, 2009 second edition.
`Baker, R. J., “CMOS Analog Circuit Design,” (A self-study course with study guide, videos, and tests.) IEEE Education
`Activity Department, 2000. ISBN 0-7803-4822-2 (with textbook) and ISBN 0-7803-4823-0 (without textbook)
`Baker, R. J., “CMOS Digital Circuit Design,” (A self-study course with study guide, videos, and tests.) IEEE Education
`Activity Department, 2000. ISBN 0-7803-4812-5 (with textbook) and ISBN 0-7803-4813-3 (without textbook)
`Li, H.W., Baker, R. J., and Thelen, D., “CMOS Amplifier Design,” chapter 19 in the CRC VLSI Handbook, edited by Wai-
`kai Chen, CRC Press, 1999 (ISBN 0-8493-8593-8) and the second edition in 2007 (ISBN 978-0-8493-4199-1)
`INVITED TALKS AND SEMINARS
`Have given over 50 invited talks and seminars at the following locations: AMD (Fort Collins), AMI semiconductor,
`Arizona State University, Beijing Jiaotong University, Boise State University, Carleton University, Carnegie Mellon,
`Columbia University, Dublin City University (Ireland), E.G.&G. Energy Measurements, Foveon, the Franklin
`Institute, Georgia Tech, Gonzaga University, Hong Kong University of Science and Technology, ICSEng Keynote,
`ICySSS keynote, IEEE Computing and Communication Workshop (CCWC), IEEE Electron Devices Conference
`(NVMTS), IEEE Workshop on Microelectronics and Electron Devices (WMED), Indian Institute of Science
`(Bangalore, India), Instituto de Informatica (Brazil), Instituto Tecnológico y de Estudios Superiores de Monterrey
`(ITESM, Mexico), Iowa State University, Lawrence Livermore National Laboratory, Lehigh University, Lockheed-
`Martin, Micron Technology, Nascentric, National Semiconductor, Princeton University, Rendition, Saintgits
`College
`(Kerala,
`India), Southern Methodist University, Sun Microsystems, Stanford University, ST
`Microelectronics (Delhi, India), Temple University, Texas A&M University, Tower Semiconductor (Israel),
`University of Alabama (Tuscaloosa), University of Arkansas, University of Buenos Aires (Argentina), University of
`Houston, University of Idaho, University of Illinois (Urbana-Champaign), Université Laval (Québec City, Québec),
`University of Macau, University of Maryland, Université de Montréal (École Polytechnique de Montréal), Xilinx
`(Ireland), University of Nevada (Las Vegas), University of Nevada (Reno), University of Toronto, University of Utah,
`Utah State University, and Yonsei University (Seoul, South Korea).
`RECENT RESEARCH FUNDING (LAST 5 YEARS)
`Recent funding listed below. In-kind, equipment, and other non-contract/grant funding [e.g., MOSIS support, money
`for travel for invited talks, etc.] not listed.
` Goldman, J., Menezes, J., and Baker, R. J., (2021) "Monitored Compression Therapy: Using Smart Technology to
`Optimize the Treatment of Lower Extremity Swelling," UNLV Sports Research & Innovation Initiative. Proof of
`Concept Grant Program, $50,000
`Baker, R. Jacob, (2019-2021) "Tiled Silicon Photomultiplier Array Read-Out Integrated Circuit," NASA, $225,238
`Baker, R. Jacob, (2019-2021) "Dual-Mode, Extended Near-Infrared, Focal Plane Arrays Fabricated with CMOS
`Compatible GeSiSn Alloy Materials," DARPA, $149,998
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`7.
`6.
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`Baker, R. Jacob, (2018-2020) “Geiger Mode SiGe Receiver for Long-Range Optical Communications,” NASA,
`$99,996
`Baker, R. Jacob, (2019) "Improved Quantum Efficiency Photo-Detector," Navy, $29,999
`Baker, R. Jacob, (2018-2019) "Tiled Silicon Photomultiplier Array Read-Out Integrated Circuit – Phase I," NASA,
`$29,999
`Baker, R. Jacob, (2017-2019) "Quantum Cryptography Detector Chip," Defense MicroElectronics Activity (DMEA),
`$266,029
`Baker, R. Jacob, (2017-2019) “Advanced Printed Circuit Board Design Methods for Compact Optical Transceiver,”
`U.S. Army/DOD, $299,605
`Baker, R. Jacob, (2016-2018) "High-Sensitivity Monolithic Silicon APD and ROIC," U.S. Air Force/DOD, $299,665
`Baker, R. Jacob, (2017-2018) "Transimpedance Amplifier Integrated Circuit Collaboration," Department of Energy,
`National Security Technologies, LLC, $100,436
`Baker, R. Jacob, (2017) “Geiger Mode SiGe Receiver for Long-Range Optical Communications,” NASA, $30,000
`Baker, R. Jacob, (2016-2017) "Testing and development of BiCMOS photodetectors and diagnostic
`instrumentation," Department of Energy, National Security Technologies, LLC, $181,605
`Baker, R. Jacob, (2016-2017) "Dual-Mode, Extended Near Infrared, Focal Plane Arrays fabricated with a
`Commercial SiGe BiCMOS Process," DARPA, $41,892
`DOCTORAL STUDENT SUPERVSION
`10. Sachin Namboodiri – A Multi-channel MCP-PMT based Readout Integrated Circuit for LiDAR Applications (2020)
`9. Wenlan Wu – High-Speed Radhard Mega-Pixel CIS Camera for High-Energy Physics (2019)
`8.
`Kostas Moutafis – A Highly-Sensitive Global-Shutter CMOS Image Sensor with On-Chip Memory for Hundreds of
`kilo-frames per second Scientific Experiments (2019)
`Yiyan Li – Portable High Throughput Digital Microfluidics and On-Chip Bacteria Cultures (2016)
`Yacouba Moumouni – Designing, Building, and Testing a Solar Thermoelectric Generation, STEG, for Energy
`Delivery to Remote Residential Areas in Developing Regions (2015)
`5. Qawi IbnZayd Harvard – Low-Power, High-Bandwidth, and Ultra-Small Memory Module Design (2011)
`4.
`Vishal Saxena – K-Delta-1-Sigma Modulators for Wideband Analog-to-Digital Conversion (2010)
`3.
`Robert Russell Hay – Digitally-Tunable Surface Acoustic Wave Resonator (2009)
`2.
`Xiangli Li (the first Boise State University College of Engineering PhD graduate) – MOSFET Modulated Dual
`Conversion Gain CMOS Image Sensors (2008)
`Feng Lin, Research and Design of Low Jitter, Wide Locking-Range Phase-Locked and Delay-Locked Loops (2000)
`1.
`MASTERS STUDENT SUPERVISION
`83. Gonzalo Arteaga – Current-mode photon-counting circuit with SiGe BiCMOS input stage (2020)
`82. Jason Silic – Design and Fabrication of a 6-bit Current-Mode ADC for Lidar and High-Speed Applications (2020)
`81. Brandon Wade (2020)
`80. Mario Valles Montenegro – Front-End CMOS Transimpedance Amplifiers on a Silicon Photomultiplier Resistant
`to Fast Neutron Fluence (2020)
`Jonathan DeBoy (2018)
`79.
`78. Dane Gentry – Design, Layout, and Testing of SiGe APDs Fabricated in a BiCMOS Process (2018)
`77.
`James Mellot – Variable Transition Time Inverters in a Digital Delay Line with Analog Storage for Processing Fast
`Signals and Pulses (2018)
`76. Eric Monahan – High Speed Fast Transient Digitizer Design and Simulation (2018)
`75. Shada Sharif – Design and Analysis of First and Second Order K-Delta-1-Sigma Modulators in Multiple Fabrication
`Processes (2018)
`74. Vikas Vinayaka – Analysis and Design of Analog Front-End Circuitry for Avalanche Photodiodes (APD) and Silicon
`Photo-Multipliers (SiPM) in Time-of-Flight Applications (2018)
`73. Claire Tsagkari – Design, Fabrication and Testing of a Capacitive Sensor Using Delta-Sigma Modulation (2017)
`72. Kevin Buck – Fast Transient Digitizer and PCB Interface (2015)
`71. Marzieh Sharbat Maleki (2015)
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`70. Angsuman Roy – Design, Fabrication and Testing of Monolithic Low-Power Passive Sigma-Delta Analog-to-Digital
`Converters (2015)
`69. Daniel Anderson – Design and Implementation of an Instruction Set Architecture and Instruction Execution Unit
`for the RZ9 Coprocessor System (2014)
`Jared Gordon – Design and Fabrication of an Infrared Optical Pyrometer ASIC (2013)
`68.
`Justin Butterfield (2012)
`67.
`66. Adam Johnson – Methods and Considerations for Testing Resistive Memories (2012)
`65. Ben Millemon – CMOS Characterization, Modeling, and Circuit Design in the Presence of Random Local Variation
`(2012)
`Justin Wood (2012)
`64.
`63. Chamunda Ndinawe Chamunda (2011)
`62. Gary VanAckern – Design Guide for CMOS Process On-Chip 3D Inductors using Thru-Wafer Vias (2011)
`61. Lucien Jan Bissey – High-Voltage Programmable Delta-Sigma Modulation Voltage-Control Circuit (2010)
`60. Kaijun Li (2010)
`59. Yingting Li (co-supervised with Maria Mitkova) (2010)
`58. Lael Matthews (co-supervised with Said Ahmed-Zaid) (2010)
`57. Priyanka Mukeshbhai Parikh (2010)
`56. Todd Plum (co-supervised with Jeff Jessing) – Design and Fabrication of a Chemicapacitive Sensor for the
`Detection of Volatile Organic Compounds (2010)
`55. Rahul Srikonda (2010)
`54. Avani Falgun Trivedi (2010)
`53. Kuang Ming Yap – Gain and Offset Error Correction for CMOS Image Sensors using Delta-Sigma Modulation
`(2010)
`52. Mahesh Balasubramanian – Phase Change Memory - Array Development and Sensing Circuits using Delta-Sigma
`Modulation (2009)
`51. Lincoln Bollschweiler (2009)
`50. Shantanu Gupta (2009)
`49. Qawi Harvard – Wide I_O DRAM Architecture Utilizing Proximity Communication (2009)
`48. Avinash Rajagiri (2009)
`47. Ramya Ramarapu (2009)
`46. Harikrishna Rapole (2009)
`45. Aruna Vadla (2009)
`44. Hemanth Ande (2008)
`43. Curtis Cahoon – Low-Voltage CMOS Temperature Sensor Design using Schottky Diode-Based References (2008)
`42. Prashanth Busa (2008)
`41.
`John McCoy III (2008)
`40. Dennis Montierth – Using Delta-Sigma-Modulation for Sensing in a CMOS Imager (2008)
`39. Rudi Rashwand (2008)
`38. Barsha Shrestha (co-supervised with Zhu Han) – Wireless Access in Vehicular Environments using Bit Torrent and
`Bargaining (2008)
`37. Eric Becker – Design of an Integrated Half-Cycle Delay Line Duty Cycle Corrector Delay Locked Loop (2007)
`36. Matthew Leslie – Noise-Shaping Sense Amplifier for Cross-Point Arrays (2007)
`35.
`Jose Monje (2007)
`34. Sanghyun Park (2007)
`33. Vishal Saxena – Indirect Feedback Compensation Techniques for Multi-Stage Operational Amplifiers (2007)
`32. Meshack Appikatla (2006)
`31. Eric Booth – Wide Range, Low Jitter Delay-Locked Loop Using a Graduated Digital Delay Line and Phase
`Interpolator (2006)
`30. Sucheta Das (2006)
`29. Krishna Duvvada – High Speed Digital CMOS Input Buffer Design (2006)
`28. Krishnamraju Kurra (2006)
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`27. Soumya Narasimhan (2006)
`26. Roger Porter (2006)
`25. David Butler – Low-Voltage Bandgap Reference Design Utilizing Schottky Diodes (2005)
`24. Dragos Dimitriu (2005)
`23. Surendranath Eruvuru – Sensing Circuit Design for an Ion Mobility Spectrometer (2005)
`22. Sandhya Sandireddy (2005)
`21. Harish Singidi (2005)
`20.
`Indira Vemula – Delta-Sigma Modulator Used in CMOS Imagers (2005)
`19. Bhavana Kollimarla – A 1-Bit Analog-to-Digital Converter Using Delta Sigma Modulation for Sensing in CMOS
`Imagers (2004)
`18. Sandeep Pemmaraju – High Voltage Charge Pump Circuit for an Ion Mobility Spectrometer (2004)
`17. Ravindra Puthumbaka – Circuit Design for an Ion Mobility Spectrometer (2004)
`16. Brandon Roth – Comparison of Asynchronous vs. Synchronous Design Technologies using a 16-bit Binary Adder
`(2004)
`Jennifer Taylor – Reading and Writing Flash Memory Using Delta-Sigma Modulation (2004)
`15.
`Jing Plaisted – Methods for Memory Testing (2003)
`14.
`13. Murugesh Subramaniam – Flash Memory Sensing Using Averaging (2003)
`12. Brian Johnson – Application of an Asynchronous FIFO in a DRAM Data Path (2002)
`11. Scott Ward – Electrostatic Discharge (ESD) Protection in CMOS (2002)
`10. Tyler Gomm – Design of a Delay-Locked Loop with a DAC-Controlled Analog Delay Line (2001)
`9.
`Gexin Huang (2001)
`8.
`Chris Atkins (2000)
`7.
`Thaddeus Black (2000)
`6.
`Zuxu Qin (2000)
`5.
`Hao Chen (1999)
`4.
`Doug Hackler (co-supervised with Steve Parke) – TMOS: A Novel Design for MOSFET Technology (1999)
`3.
`Song Liu – Design of a CMOS 6-bit Folding and Interpolating Analog-to-Digital Converter (1999)
`2.
`Ben Ba (1997)
`1.
`Brent Keeth – A Novel Architecture for Advanced High Density Dynamic Random Access Memories (1996)
`GRANTED US PATENTS
`152. Baker, R. J., “Quantizing circuits having improved sensing,” 10,658,018, May 19, 2020.
`151. Baker, R. J., “Quantizing circuits having improved sensing,” 10,403,339, September 3, 2019.
`150. Baker, R. J., “Digital Filters with Memory,” 10,366,744, July 30, 2019.
`149. Baker, R. J., “Quantizing circuits having improved sensing,” 10,127,954, November 13, 2018.
`148. Baker, R. J. and Parkinson, W., “NMOS regulated voltage reference,” 9,753,481, September 5, 2017.
`147. Baker, R. J., “Digital Filters with Memory,” 9,734,894, August 15, 2017.
`146. Baker, R. J. and Keeth, B., "Optical interconnect in high-speed memory systems," 9,697,883, July 7, 2017
`145. Baker, R. J., “Comparators for delta-sigma modulators,” 9,641,193, May 2, 2017.
`144. Baker, R. J., “Quantizing circuits having improved sensing,” 9,449,664, September 20, 2016.
`143. Baker, R. J., “Error detection for multi-bit memory,” 9,336,084, May 10, 2016.
`142. Baker, R. J. and Keeth, B., “Optical interconnect in high-speed memory systems,” 9,299,423, March 29, 2016.
`141. Baker, R. J., “Methods for sensing memory elements in semiconductor devices,” 9,299,405, March 29, 2016.
`140. Baker, R. J., “Comparators for delta-sigma modulators,” 9,135,962, September 15, 2015.
`139. Baker, R. J., “Resistive memory element sensing using averaging,” 9,081,042, July 14, 2015.
`138. Baker, R. J., “Digital Filters with Memory,” 9,070,469, June 30, 2015.
`137. Baker, R. J., "Reference current sources,” 8,879,327, November 4, 2014.
`136. Baker, R. J. and Beigel, K. D., “Multi-resistive integrated circuit memory,” 8,878,274, November 4, 2014.
`135. Baker, R. J., “Methods for sensing memory elements in semiconductor devices,” 8,854,899, October 7, 2014.
`134. Baker, R. J., “Quantizing circuits with variable parameters,” 8,830,105, September 9, 2014.
`133. Baker, R. J., “Integrators for delta-sigma modulators,” 8,754,795, June 17, 2014.
`132. Baker, R. J., “Methods of quantizing signals using variable reference signals,” 8,717,220, May 6, 2014.
`
`Page 8
`
`R. JACOB BAKER, PH.D., P.E.
`
`Petitioners Ex. 1004
`IPR USP 8,624,550
`Page 8 of 32
`
`

`

`131. Baker, R. J. and Keeth, B., “Optical interconnect in high-speed memory systems,” 8,712,249, April 29, 2014.
`130. Baker, R. J., “Resistive memory element sensing using averaging,” 8,711,605, April 29, 2014.
`129. Baker, R. J., “Memory with correlated resistance,” 8,681,557, March 25, 2014.
`128. Baker, R. J., “Reference current sources,” 8,675,413, March 18, 2014.
`127. Baker, R. J., “Methods for sensing memory elements in semiconductor devices,” 8,582,375, November 12, 2013.
`126. Linder, L. F., Renner, D., MacDougal, M., Geske, J., and Baker, R. J., “Dual well read-out integrated circuit (ROIC),”
`8,581,168, November 12, 2013.
`125. Li, W., Schoenfeld, A., and Baker, R. J., “Method and apparatus for providing symmetrical output data for a
`double data rate DRAM,” 8,516,292, August 20, 2013.
`124. Baker, R. Jacob, “Resistive memory element sensing using averaging,” 8,441,834, May 14, 2013.
`123. Qawi, Q.
`I., Drost, R.
`J., and Baker, R.
`Jacob,
`"Increased DRAM-array
`throughput using
`inactive bitlines," 8,395,947, March 12, 2013.
`122. Baker, R. Jacob, “Memory with correlated resistance,” 8,289,772, October 16, 2012.
`121. Lin, F. and Baker, R. Jacob, “Phase splitter using digital delay locked loops,” 8,218,708, July 10, 2012.
`120. Baker, R. Jacob, “Subtraction circui