Declaration in Support of Petition for IPR of U.S. Patent No. 7,239,550
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TCT MOBILE (US), INC.; TCT MOBILE (US) HOLDINGS, INC.; HUIZHOU TCL MOBILE
`COMMUNICATION CO. LTD.; AND TCL COMMUNICATION, INC.
`Petitioners
`v.
`FUNDAMENTAL INNOVATION SYSTEMS INTERNATIONAL LLC,
`Patent Owner
`
`
`U.S. Patent No. 8,624,550
`
`
`DECLARATION OF R. JACOB BAKER, PH.D., P.E.,
` REGARDING U.S. PATENT NO. 8,624,550
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,239,550
`
`TABLE OF CONTENTS
`I. 
`INTRODUCTION .................................................................................................................... 3 
`A.  Educational and Work Background .................................................................................... 3 
`1.  Industry Experience ...................................................................................................... 4 
`2.  Academic Experience ................................................................................................... 8 
`3.  Other Relevant Experience ......................................................................................... 10 
`II.  UNDERSTANDING OF THE LAW ..................................................................................... 11 
`A.  Legal Standard for Prior Art ............................................................................................. 11 
`B.  Legal Standard for Anticipation ........................................................................................ 12 
`C.  Legal Standard for Obviousness ....................................................................................... 13 
`D.  Legal Standard for Claim Construction ............................................................................ 18 
`E.  Legal Standard for Priority Date ....................................................................................... 24 
`III. LEVEL OF ORDINARY SKILL IN THE ART .................................................................... 25 
`IV. BACKGROUND OF THE TECHNOLOGY ......................................................................... 26 
`A.  Overview of USB 1.1 ........................................................................................................ 26 
`B.  Use of the SE1 Abnormal Condition ................................................................................ 36 
`C.  The ‘550 Patent ................................................................................................................. 40 
`1.  Overview of the ’550 Patent ....................................................................................... 40 
`2.  The ’021 Application .................................................................................................. 43 
`V.  OVERVIEW OF THE PRIOR ART....................................................................................... 47 
`A.  Overview of Morita ........................................................................................................... 47 
`B.  Overview of Dougherty .................................................................................................... 50 
`VI. THE CLAIMS OF THE ‘550 PATENT ARE UNPATENTABLE ........................................ 52 
`A.  Morita in View of the Knowledge of a POSITA Renders The Subject Matter of Claims 1-
`18 of the ‘550 Patent Obvious .......................................................................................... 52 
`B.  Dougherty In View Of USB 1.1 Renders The Subject Matter Of Claims 1-2, 9, 10-11,
`And 18 Obvious. ............................................................................................................... 71 
`VII.  CONCLUSION ................................................................................................................. 81 
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,239,550
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`I.
`
`INTRODUCTION
`
`1. My name is R. Jacob Baker Ph.D., P.E., and I am a Professor of
`
`Electrical and Computer Engineering at the University of Nevada, Las Vegas. I
`
`have prepared this declaration as an expert witness on behalf of Petitioners TCT
`
`MOBILE (US), INC.; TCT MOBILE (US) HOLDINGS, INC.; HUIZHOU TCL
`
`MOBILE COMMUNICATION CO. LTD.; and TCL COMMUNICATION, INC.
`
`In this declaration, I will give my opinion as to whether claims 1-18 of U.S. Patent
`
`No. 8,624,550 (“the ’550 patent”) (Ex. 1001) are valid. I also provide herein the
`
`technical bases for these opinions, as appropriate.
`
`2.
`
`This declaration contains statements of my opinions formed to date,
`
`and the bases and rationale for these opinions. I may offer additional opinions
`
`based on further review of materials in this case, including opinions and/or
`
`testimony of other expert witnesses.
`
`3.
`
`For my efforts in connection with the preparation of this declaration, I
`
`have been compensated at my usual and customary rate for this type of consulting
`
`activity. My compensation is in no way contingent on the results of these or any
`
`other proceedings related to the ’550 patent.
`
`A. Educational and Work Background
`4. My qualifications generally are set forth in my curriculum vitae,
`
`which is submitted as Ex. 1004.
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`5.
`
`I have been working as an Engineer since 1985 and I have been
`
`teaching Electrical and Computer Engineering courses since 1991. I am currently a
`
`Professor of Electrical and Computer Engineering at the University of Nevada, Las
`
`Vegas (“UNLV”). I am also currently an industry consultant for Freedom
`
`Photonics. I am the named inventor on over 150 U.S. patents resulting from my
`
`industry work.
`
`6.
`
`I received B.S. and M.S. degrees in Electrical Engineering from
`
`UNLV in 1986 and 1988, respectively. I received my Ph.D. in Electrical
`
`Engineering from the University of Nevada, Reno, in 1993.
`
`7. My doctoral research, culminating in the award of a Ph.D.,
`
`investigated the use of power MOSFETs in the design of very high peak power,
`
`and high-speed, instrumentation. I developed techniques to reliably stack power
`
`MOSFETs to switch higher voltages, that is, greater than 1,000 V and 100 Amps of
`
`current with nanosecond switching times. This work was reported in the paper
`
`entitled “Transformerless Capacitive Coupling of Gate Signals for Series
`
`Operation of Power MOSFET Devices,” published in the IEEE Transactions on
`
`Power Electronics. The paper received the Best Paper Award in 2000.
`
`1.
`
`Industry Experience
`
`8.
`
`I have done technical and expert witness consulting for over 120
`
`companies since I started working as an engineer in 1985. From 1985 to 1993 I
`
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`worked for EG&G Energy Measurements and the Lawrence Livermore National
`
`Laboratory designing nuclear diagnostic instrumentation for underground nuclear
`
`weapon tests at the Nevada test site. During this time, I designed, and oversaw the
`
`fabrication of, over 30 electronic and electro-optic instruments including high-
`
`speed cable and fiber-optic receiver/transmitters, PLLs, frame and bit-syncs, data
`
`converters, streak-camera sweep circuits, Pockel’s cell drivers, micro-channel plate
`
`gating circuits, charging circuits for battery backup of equipment for recording test
`
`data, and analog oscilloscope electronics.
`
`9.
`
` My work during this time, as one example, had a direct impact on my
`
`doctoral research work using power MOSFETs, subsequent publishing efforts, and
`
`industry designs. In addition to the 2000 Best Paper Award from the IEEE Power
`
`Electronics Society, I published several other papers in related areas while working
`
`in industry. I hold a patent, Patent No. 5,874,830, in the area of power supply
`
`design, titled, “Adaptively biased voltage regulator and operating method,” which
`
`was issued on February 23, 1999. I have designed dozens of linear and switching
`
`power supplies for commercial products and scientific instrumentation.
`
`10.
`
`I am a licensed Professional Engineer and have extensive industry
`
`experience in circuit design, fabrication, and manufacture of Dynamic Random
`
`Access Memory (DRAM) semiconductor integrated circuit chips, Phase-Change
`
`Random Access Memory (PCRAM) chips, and CMOS Image Sensors (CISs) at
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`Micron Technology, Inc. (“Micron”) in Boise, Idaho. I spent considerable time
`
`working on the development of Flash memory chips while at Micron. My efforts
`
`resulted in more than a dozen patents relating to Flash memory. One of my
`
`projects at Micron included the development, design, and testing of circuit design
`
`techniques for a multi-level cell (MLC) Flash memory using signal processing.
`
`Another project focused on the design of buffers for high-speed double-data rate
`
`DRAM which resulted in around 10 US patents in buffer design. Among many
`
`other experiences, I led the development of the delay locked loop (DLL) in the late
`
`1990s so that Micron DRAM products could transition to the DDR memory
`
`protocol, used in mobile and non-mobile (server, desktop, cell phones, tablets, etc.)
`
`computing systems as main computer memory, for addressing and controlling
`
`accesses to memory via interprocess communications (IPC) with the memory
`
`controller (MC). I provided technical assistance with Micron’s acquisition of
`
`Photobit during 2001 and 2002, including transitioning the manufacture of CIS
`
`products into Micron’s process technology. Further, I did consulting work at Sun
`
`Microsystems and then Oracle on the design of memory modules during 2009 and
`
`2010. This work entailed the design of low-power, high-speed, and wide
`
`interconnection methods with the goal of transmitting data to/from the memory
`
`module and the MC at higher speeds.
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`11.
`
`I have extensive experience in the development of instrumentation
`
`and commercial products in a multitude of areas including: integrated
`
`electrical/biological circuits and systems, array (memory, imagers, and displays)
`
`circuit design, CMOS analog and digital circuit design, diagnostic electrical and
`
`electro-optic instrumentation for scientific research, CAD tool development and
`
`online tutorials, low-power interconnect and packaging techniques, design of
`
`communication/interface circuits (to meet commercial standards such as USB,
`
`firewire, DDR, PCIe, SPI, etc.), circuit design for the use and storage of renewable
`
`energy, and power electronics. For example, a part of my research at Boise State,
`
`for many years, focused on the use of Thru-Silicon-Vias (TSVs), aka Thru-Wafer
`
`Vias (TWVs), for high-density packaging. These packaging techniques were
`
`utilized in the memory module development work I did with Sun Microsystems
`
`and Oracle. As another example, I’ve designed circuitry for use in implementing
`
`Universal Serial Bus (USB) interfaces circuits while I did consulting at Tower
`
`Semiconductor. I designed PCI communication circuits for IPC between a
`
`Graphics Processor Unit (GPU) and memory while consulting for Rendition, Inc.
`
`12. My current research work is focused in part on the design of
`
`integrated circuits for wireless sensing using LIDAR (LIght Detection And
`
`Ranging). I have worked with several companies in the development of these
`
`circuits and systems including Freedom Photonics, Aerius Photonics and FLIR. In
`
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`the early 1990s I worked on wireless systems for wideband impulse radar while at
`
`Lawrence Livermore Laboratory. Further, part of my research for several years
`
`focused on the digitization of IQ channels using delta-sigma modulation. The
`
`knowledge and experience gained from this effort are reflected in my textbook
`
`CMOS Mixed-Signal Circuit Design and a presentation, which I have presented at
`
`several universities and companies,
`
`http://cmosedu.com/jbaker/papers/talks/BP_DSM_talk.pdf.
`
`2.
`
`Academic Experience
`
`13.
`
`I was an adjunct faculty member in the Electrical Engineering
`
`department of the University of Nevada, Las Vegas in 1991 and 1992. From 1993
`
`to 2000, I served on the faculty at the University of Idaho as an Assistant Professor
`
`and then as a tenured Associate Professor of Electrical Engineering. In 2000, I
`
`joined a new Electrical and Computer Engineering program at Boise State
`
`University (“BSU”) where I served as department chair from 2004 to 2007. At
`
`BSU, I helped establish graduate programs in Electrical and Computer Engineering
`
`including, in 2006, the university’s second Ph.D. degree. In 2012, I re-joined the
`
`faculty at UNLV. Over the course of my career as a professor I have advised over
`
`90 masters and doctoral students.
`
`14.
`
`I have been recognized for my contributions as an educator in the
`
`field. While at Boise State University, I received the President’s Research and
`
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`Scholarship Award (2005), Honored Faculty Member recognition (2003), and
`
`Outstanding Department of Electrical Engineering Faculty recognition (2001). In
`
`2007, I received the Frederick Emmons Terman Award (the “Father of Silicon
`
`Valley”). The Terman Award is bestowed annually upon an outstanding young
`
`electrical/computer engineering educator in recognition of the educator’s
`
`contributions to the profession. In 2011 I received the IEEE Circuits and Systems
`
`Education Award. I received the Tau Beta Pi Outstanding Electrical and Computer
`
`Engineering Professor Award every year it was awarded while I have been back at
`
`UNLV.
`
`15.
`
`I have authored several books and papers in the electrical and
`
`computer engineering area. My published books include CMOS Circuit Design,
`
`Layout, and Simulation (Baker, R.J., Wiley-IEEE, ISBN: 9781119481515 (4th ed.,
`
`2019)) and CMOS Mixed-Signal Circuit Design (Baker, R.J., Wiley-IEEE, ISBN:
`
`9780470290262 (2nded., 2009) and ISBN: 978-0471227540 (1st ed., 2002)). I co-
`
`authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth, B.,
`
`Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 9780470184752 (2008)),
`
`DRAM Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE, ISBN:
`
`0780360141 (2001)), and CMOS Circuit Design, Layout and Simulation (Baker,
`
`R.J., Li, H.W., and Boyce, D.E., Wiley-IEEE, ISBN: 9780780334168 (1998)). I
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`contributed as an editor and co-author on several other electrical and computer
`
`engineering books.
`
`3. Other Relevant Experience
`
`16.
`
`I have performed technical and expert witness consulting for over 100
`
`companies and laboratories and given more than 50 invited talks at conferences,
`
`companies, and Universities. Further, I am the author and co-author of more than
`
`100 papers and presentations in the areas of electrical and computer engineering
`
`design, fabrication and packaging.
`
`17.
`
`I currently serve, or have served, as a volunteer on: the IEEE Press
`
`Editorial Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
`
`Microelectronic Systems (2010-2018); as the Technical Program Chair of the 2015
`
`IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS
`
`2015); on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
`
`(2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015); and as the
`
`Technology Editor (2012-2014) and Editor-in-Chief (2015-2020) for the IEEE
`
`Solid-State Circuits Magazine. These meetings, groups, and publications are
`
`intended to allow researchers to share and coordinate research. My active
`
`participation in these meetings, groups, and publications allowed me to see what
`
`other researchers in the field have been doing.
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`18.
`
`In addition to the above, I am an IEEE Fellow for contributions to
`
`memory design and a member of the honor societies Eta Kappa Nu and Tau Beta
`
`Pi.
`
`19. My current research work is focused in part on the design of
`
`integrated circuits for wireless sensing using LIDAR (LIght Detection And
`
`Ranging). I have worked with several companies in the development of these
`
`circuits and systems including Aerius Photonics and FLIR.
`
`20.
`
`I have considered information from various sources in forming my
`
`opinions. A list of materials considered is included in the list of exhibits that I
`
`understand Petitioner is filing. I may review additional documents filed in
`
`connection with this proceeding as they become available.
`
`II. UNDERSTANDING OF THE LAW
`
`21.
`
`I have applied the following legal principles provided to me by
`
`counsel in arriving at the opinions set forth in this declaration.
`
`A. Legal Standard for Prior Art
`22.
`I understand that a patent or other publication must first qualify as
`
`prior art before it can be used to invalidate a patent claim.
`
`23.
`
`I understand that a U.S. or foreign patent qualifies as prior art to an
`
`asserted patent if the date of issuance of the patent is prior to the invention of the
`
`asserted patent. I further understand that a printed publication, such as a book or
`
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`an article published in a magazine or trade publication, qualifies as prior art to an
`
`asserted patent if the date of publication is prior to the invention of the asserted
`
`patent.
`
`24.
`
`I understand that a U.S. or foreign patent qualifies as prior art to an
`
`asserted patent if the date of issuance of the patent is more than one year before the
`
`filing date of the asserted patent. I further understand that a printed publication,
`
`such as a book or an article published in a magazine or trade publication,
`
`constitutes prior art to an asserted patent if the publication occurs more than one
`
`year before the filing date of the asserted patent.
`
`25.
`
`I understand that a U.S. patent qualifies as prior art to the asserted
`
`patent if the application for that patent was filed in the United States before the
`
`invention of the asserted patent.
`
`26.
`
`I understand that to qualify as prior art, a reference must contain an
`
`enabling disclosure that allows one of ordinary skill to practice the claims without
`
`undue experimentation.
`
`27.
`
`I understand that documents and materials that qualify as prior art can
`
`be used to invalidate a patent claim as anticipated or as obvious.
`
`B.
`
`Legal Standard for Anticipation
`28.
`I understand that once the claims of a patent have been properly
`
`construed, the second step in determining anticipation of a patent claim requires a
`
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`comparison of the properly construed claim language to the prior art on a
`
`limitation-by-limitation basis.
`
`29.
`
`I understand that a prior art reference “anticipates” an asserted claim,
`
`and thus renders the claim invalid, if all elements of the claim are disclosed in that
`
`prior art reference, either explicitly or inherently (i.e., necessarily present or
`
`implied).
`
`30.
`
`I understand that a patent is anticipated if before such person’s
`
`invention thereof, the invention was made in this country by another inventor who
`
`had not abandoned, suppressed, or concealed it.
`
`31.
`
`I have written this declaration with the understanding that in an inter
`
`partes review anticipation must be shown by a preponderance of the evidence.
`
`C. Legal Standard for Obviousness
`32.
`I have been instructed by counsel on the law regarding obviousness,
`
`and understand that even if a patent is not anticipated, it is still invalid if the
`
`differences between the claimed subject matter and the prior art are such that the
`
`subject matter as a whole would have been obvious at the time the invention was
`
`made to a person of ordinary skill in the pertinent art.
`
`33.
`
`I understand that a person of ordinary skill in the art provides a
`
`reference point from which the prior art and claimed invention should be viewed.
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`This reference point prevents a person of ordinary skill from using one’s insight or
`
`hindsight in deciding whether a claim is obvious.
`
`34.
`
`I also understand that an obviousness determination includes the
`
`consideration of various factors such as (1) the scope and content of the prior art,
`
`(2) the differences between the prior art and the challenged claims, (3) the level of
`
`ordinary skill in the pertinent art, and (4) the existence of secondary considerations
`
`such as commercial success, long-felt but unresolved needs, failure of others, etc.
`
`35.
`
`I am informed that secondary considerations of non-obviousness may
`
`include (1) a long felt but unmet need in the prior art that was satisfied by the
`
`invention of the patent; (2) commercial success or lack of commercial success of
`
`processes covered by the patent; (3) unexpected results achieved by the invention;
`
`(4) praise of the invention by others skilled in the art; (5) taking of licenses under
`
`the patent by others; and (6) deliberate copying of the invention. I also understand
`
`that there must be a relationship between any such secondary indicia and the
`
`invention. I further understand that contemporaneous and independent invention
`
`by others is a secondary consideration supporting an obviousness determination.
`
`36.
`
`I understand that an obviousness evaluation can be based on a
`
`combination of multiple prior art references. I understand that the prior art
`
`references themselves may provide a suggestion, motivation, or reason to combine,
`
`but other times the link between two or more prior art references is simple
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`common sense. I further understand that obviousness analysis recognizes that
`
`market demand, rather than scientific literature, often drives innovation, and that a
`
`motivation to combine references may be supplied by the direction of the
`
`marketplace.
`
`37.
`
`I understand that if a technique has been used to improve one device,
`
`and a person of ordinary skill in the art would recognize that it would improve
`
`similar devices in the same way, using the technique is obvious unless its actual
`
`application is beyond his or her skill.
`
`38.
`
`I also understand that practical and common-sense considerations
`
`should guide a proper obviousness analysis, because familiar items may have
`
`obvious uses beyond their primary purposes. I further understand that a person of
`
`ordinary skill in the art looking to overcome a problem will often be able to fit the
`
`teachings of multiple publications together like pieces of a puzzle, although the
`
`prior art need not be like two puzzle pieces that must fit perfectly together. I
`
`understand that obviousness analysis therefore considers the inferences and
`
`creative steps that a person of ordinary skill in the art would employ under the
`
`circumstances.
`
`39.
`
`I understand that a particular combination may be proven obvious by
`
`showing that it was obvious to try the combination. For example, when there is a
`
`design need or market pressure to solve a problem and there are a finite number of
`
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`identified, predictable solutions, a person of ordinary skill has good reason to
`
`pursue the known options within his or her technical grasp because the result is
`
`likely the product not of innovation but of ordinary skill and common sense.
`
`40.
`
`I understand that the combination of familiar elements according to
`
`known methods may be proven obvious when it does no more than yield
`
`predictable results. When a work is available in one field of endeavor, design
`
`incentives and other market forces can prompt variations of it, either in the same
`
`field or a different one. If a person of ordinary skill can implement a predictable
`
`variation, obviousness likely bars its patentability.
`
`41.
`
`It is further my understanding that a proper obviousness analysis
`
`focuses on what was known or obvious to a person of ordinary skill in the art, not
`
`just the patentee. Accordingly, I understand that any need or problem known in
`
`the field of endeavor at the time of invention and addressed by the patent can
`
`provide a reason for combining the elements in the manner claimed.
`
`42.
`
`I understand that a claim can be obvious in light of a single reference,
`
`without the need to combine references, if the elements of the claim that are not
`
`found explicitly or inherently in the reference can be supplied by the common
`
`sense of one of skill in the art.
`
`43.
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`I understand that a person of ordinary skill could have combined two
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`pieces of prior art or substituted one prior art element for another if the substitution
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,239,550
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`can be made with predictable results, even if the swapped-in element is different
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`from the swapped-out element. In other words, the prior art need not be like two
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`puzzle pieces that must fit together perfectly. The relevant question is whether
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`prior art techniques are interoperable with respect to one another, such that that a
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`person of skill would view them as a design choice, or whether a person of skill
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`could apply prior art techniques into a new combined system.
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`44.
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`In sum, my understanding is that prior art teachings are properly
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`combined where a person of ordinary skill in the art having the understanding and
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`knowledge reflected in the prior art and motivated by the general problem facing
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`the inventor, would have been led to make the combination of elements recited in
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`the claims. Under this analysis, the prior art references themselves, or any need or
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`problem known in the field of endeavor at the time of the invention, can provide a
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`reason for combining the elements of multiple prior art references in the claimed
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`manner.
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`45.
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`I have been informed and understand that the obviousness analysis
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`requires a comparison of the properly construed claim language to the prior art on
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`a limitation-by-limitation basis.
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`46.
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`I have written this declaration with the understanding that in an inter
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`partes review obviousness must be shown by a preponderance of the evidence.
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,239,550
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`D. Legal Standard for Claim Construction
`47.
`I have been instructed by counsel on the law regarding claim
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`construction and patent claims and understand that a patent may include two types
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`of claims, independent claims and dependent claims. An independent claim stands
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`alone and includes only the limitations it recites. A dependent claim can depend
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`from an independent claim or another dependent claim. I understand that a
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`dependent claim includes all the limitations that it recites in addition to all of the
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`limitations recited in the claim from which it depends.
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`48.
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`It is my understanding that in proceedings before the USPTO, claims
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`are construed similarly as in district court litigation, and that this standard is
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`sometimes referred to as the Phillips standard. Under this standard, it is my
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`understanding that claim terms are given the meaning the term would have to a
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`person of ordinary skill in the art at the time of the invention, in view of the
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`specification and file history.
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`49.
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`In comparing the claims of the ’550 patent to the prior art, I have
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`carefully considered the ’550 patent and its file history in light of the
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`understanding of a person of skill at the time of the alleged invention.
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`50.
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`I understand that to determine how a person of ordinary skill would
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`understand a claim term, one should look to those sources available that show what
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`a person of skill in the art would have understood disputed claim language to
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`mean. Such sources include the words of the claims themselves, the remainder of
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`the patent’s specification, the prosecution history of the patent (all considered
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`“intrinsic” evidence), and “extrinsic” evidence concerning relevant scientific
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`principles, the meaning of technical terms, and the state of the art.
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`51.
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`I understand that, in construing a claim term, one looks primarily to
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`the intrinsic patent evidence, including the words of the claims themselves, the
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`remainder of the patent specification, and the prosecution history.
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`52.
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`I understand that extrinsic evidence, which is evidence external to the
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`patent and the prosecution history, may also be useful in interpreting patent claims
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`when the intrinsic evidence itself is insufficient.
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`53.
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`I understand that words or terms should be given their ordinary and
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`accepted meaning unless it appears that the inventors were using them to mean
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`something else. In making this determination, the claims, the patent specification,
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`and the prosecution history are of paramount importance. Additionally, the
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`specification and prosecution history must be consulted to confirm whether the
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`patentee has acted as its own lexicographer (i.e., provided its own special meaning
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`to any disputed terms), or intentionally disclaimed, disavowed, or surrendered any
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`claim scope.
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`54.
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`I understand that the claims of a patent define the scope of the rights
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`conferred by the patent. The claims particularly point out and distinctly claim the
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`Declaration in Support of Petition for IPR of U.S. Patent No. 7,239,550
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`subject matter which the patentee regards as his invention. Because the patentee is
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`required to define precisely what he claims his invention to be, it is improper to
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`construe claims in a manner different from the plain import of the terms used
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`consistent with the specification. Accordingly, a claim construction analysis must
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`begin and remain centered on the claim language itself. Additionally, the context
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`in which a term is used in the asserted claim can be highly instructive. Likewise,
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`other claims of the patent in question, both asserted and unasserted, can inform the
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`meaning of a claim term. For example, because claim terms are normally used
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`consistently throughout the patent, the usage of a term in one claim can often
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`illuminate the meaning of the same term in other claims. Differences among
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`claims can also be a useful guide in understanding the meaning of particular claim
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`terms.
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`55.
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`I understan