U.S. Patent No. 6,651,134
`Petition for Inter Partes Review
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`DECLARATION OF R. JACOB BAKER, PH.D., P.E. IN SUPPORT OF
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,651,134
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`TABLE OF CONTENTS
`
`Page
`
`TABLE OF CONTENTS
`
`I.
`
`BACKGROUND AND QUALIFICATIONS ................................................ 1
`A.
`Industry Experience .............................................................................. 2
`B.
`Academic Experience ........................................................................... 5
`Other Relevant Experience ................................................................... 7
`C.
`OVERVIEW OF THE TECHNOLOGY ........................................................ 8
`II.
`SUMMARY OF GROUNDS ....................................................................... 10
`III.
`LEGAL STANDARDS ................................................................................ 12
`IV.
`THE CHALLENGED PATENT .................................................................. 15
`V.
`PATENT PROSECUTION HISTORY ........................................................ 18
`VI.
`VII. LEVEL OF ORDINARY SKILL IN THE ART .......................................... 20
`VIII. CLAIM CONSTRUCTION ......................................................................... 20
`A.
`“non-interruptible” (claims 1, 16, 17) ................................................ 21
`B.
`“means for reading data . . . / means for generating a
`predetermined number of said internal address signals” (claim
`16) ....................................................................................................... 22
`“external address signal” (claims 1, 13, 15-17) ................................. 24
`“burst” (claim 2) ................................................................................. 24
`“internal address signal” (claims 1, 2, 12, 15-17) .............................. 24
`“logic circuit” (claims 1, 12) .............................................................. 25
`“predetermined number of [said] internal address signals”
`(claims 1-4, 12, 15-17) ....................................................................... 25
`“memory” (claims 1, 8-9, 14, 17)....................................................... 26
`H.
`“address signal” (claims 1-4, 10-13, 16-17) ....................................... 26
`I.
`SPECIFIC EXPLANATION OF GROUNDS ............................................. 26
`
`C.
`D.
`E.
`F.
`G.
`
`IX.
`
`i
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`A.
`
`B.
`
`C.
`
`D.
`
`TABLE OF CONTENTS
`(continued)
`
`Page
`
`Ground 1: Claims 1-3, 8, 12-13, 16, and 17 are anticipated by
`US 6,115,280 (“Wada”) ..................................................................... 26
`1. Wada ........................................................................................ 26
`2.
`Independent Claim 1 ................................................................ 33
`3.
`Dependent Claim 2 .................................................................. 39
`4.
`Dependent Claim 3 .................................................................. 41
`5.
`Dependent Claim 8 .................................................................. 43
`6.
`Dependent Claim 12 ................................................................ 44
`7.
`Dependent Claim 13 ................................................................ 45
`8.
`Independent Claim 16 .............................................................. 48
`9.
`Independent Claim 17 .............................................................. 55
`Ground 2: Claims 1-4, 8, 12-14, 16, and 17 are obvious over
`Wada in view of the knowledge of a POSITA ................................... 56
`1.
`Independent Claims 1 and 16 ................................................... 56
`2.
`Dependent Claims 2-3, 8, 12-13, and 17 ................................. 56
`3.
`Dependent Claim 4 .................................................................. 57
`4.
`Dependent Claim 14 ................................................................ 58
`Ground 2a: Claims 1-4, 8, 12-14, 16, and 17 are rendered
`obvious by the combination of Wada and US 5,584,033
`(“Barrett”) in view of the knowledge of a POSITA ........................... 59
`1.
`Barrett ....................................................................................... 59
`2.
`Claims 1-4, 8, 12-14, 16, and 17 .............................................. 62
`Ground 3: Claims 4-7, and 18-20 are rendered obvious by the
`combination of Wada and U.S. 6,185,149 (“Fujioka”) in view
`of the knowledge of a POSITA. ......................................................... 62
`1.
`Fujioka ..................................................................................... 62
`2.
`Dependent Claim 4 .................................................................. 66
`3.
`Dependent Claim 5 .................................................................. 66
`
`ii
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`TABLE OF CONTENTS
`(continued)
`
`Page
`
`4.
`Dependent Claim 6 .................................................................. 67
`Dependent Claim 7 .................................................................. 67
`5.
`Dependent Claim 18 ................................................................ 68
`6.
`Dependent Claim 19 ................................................................ 68
`7.
`Dependent Claim 20 ................................................................ 69
`8.
`Ground 3a: Claims 4-7, and 18-20 are rendered obvious by the
`combination of Wada, Barrett, and Fujioka in view of the
`knowledge of a POSITA. ................................................................... 69
`Ground 4: Claims 9-10, 14, and 21 are rendered obvious by the
`combination of Wada and US 6,226,755 (“Reeves”) in view of
`the knowledge of a POSITA .............................................................. 69
`1.
`Reeves ...................................................................................... 69
`2.
`Dependent Claim 9 .................................................................. 72
`3.
`Dependent Claim 10 ................................................................ 72
`4.
`Dependent Claim 14 ................................................................ 73
`Dependent Claim 21 ................................................................ 74
`5.
`Ground 4a: Claims 9-10, 14, and 21 are rendered obvious by
`the combination of Wada, Barrett, and Reeves in view of the
`knowledge of one of ordinary skill in the art ..................................... 74
`Ground 5: Claims 11 and 15 are rendered obvious by the
`combination of Wada and US 5,784,331 (“Lysinger”) in view
`of the knowledge of one of ordinary skill in the art ........................... 75
`1.
`Lysinger ................................................................................... 75
`2.
`Dependent Claim 11 ................................................................ 78
`3.
`Dependent Claim 15 ................................................................ 79
`Ground 5a: Claims 11 and 15 are rendered obvious by the
`combination of Wada, Barrett, and Lysinger in view of the
`knowledge of one of ordinary skill in the art ..................................... 81
`
`E.
`
`F.
`
`G.
`
`H.
`
`I.
`
`iii
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`
`I, R. Jacob Baker, Ph.D., P.E., declare as follows:
`
`1.
`
`My name is R. Jacob Baker. I have prepared this declaration as an
`
`expert witness retained by Advanced Micro Devices, Inc. In this declaration, I
`
`present my opinions, and technical basis for those opinions, that claims 1-21 of
`
`U.S. Patent No. 6,651,134 (“the ’134 Patent”) are invalid.
`
`2.
`
`This declaration contains statements of my opinions formed to date
`
`and the reasons for those opinions. I may offer additional opinions based on further
`
`review of materials in this case, including opinions and/or testimony of other
`
`expert witnesses. I make this declaration based upon my own personal knowledge
`
`and, if called upon to testify, would testify competently to the matters contained
`
`herein.
`
`I.
`
`BACKGROUND AND QUALIFICATIONS
`1.
`I have been working as an Engineer since 1985, and I have been
`
`teaching Electrical and Computer Engineering courses since 1991. I am currently
`
`a Professor of Electrical and Computer Engineering at the University of Nevada,
`
`Las Vegas (“UNLV”). I am also currently an industry consultant for Freedom
`
`Photonics. I am the named inventor on over 150 U.S. patents resulting from my
`
`industry work.
`
`1
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`I received the B.S. and M.S. degrees in Electrical Engineering from
`
`2.
`
`UNLV in 1986 and 1988, respectively. I received my Ph.D. in Electrical
`
`Engineering from the University of Nevada, Reno, in 1993.
`
`3.
`
`My doctoral research, culminating in the award of a Ph.D.,
`
`investigated the use of power MOSFETs in the design of very high peak power,
`
`and high-speed, instrumentation. I developed techniques to reliably stack power
`
`MOSFETs to switch higher voltages, that is, greater than 1,000 V and 100 Amps of
`
`current with nanosecond switching times. This work was reported in the paper
`
`entitled “Transformerless Capacitive Coupling of Gate Signals for Series Operation
`
`of Power MOSFET Devices,” published in the IEEE Transactions on Power
`
`Electronics. The paper received the Best Paper Award in 2000.
`
`A.
`4.
`
`Industry Experience
`From 1985 to 1993 I worked for EG&G Energy Measurements and
`
`the Lawrence Livermore National Laboratory designing nuclear diagnostic
`
`instrumentation for underground nuclear weapon tests at the Nevada test site.
`
`During this time I designed, and oversaw the fabrication of, over 30 electronic and
`
`electro-optic instruments including high-speed cable and fiber-optic
`
`receiver/transmitters, PLLs, frame and bit-syncs, data converters, streak-camera
`
`sweep circuits, Pockel’s cell drivers, micro-channel plate gating circuits, charging
`
`2
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`circuits for battery backup of equipment for recording test data, and analog
`
`oscilloscope electronics.
`
`5.
`
`My work during this time, as one example, had a direct impact on my
`
`doctoral research work using power MOSFETs, subsequent publishing efforts, and
`
`industry designs. In addition to the 2000 Best Paper Award from the IEEE Power
`
`Electronics Society, I published several other papers in related areas while working
`
`in industry. I hold a patent, Patent No. 5,874,830, in the area of power supply
`
`design, titled, “Adaptively biased voltage regulator and operating method,” which
`
`was issued on February 23, 1999. I have designed dozens of linear and switching
`
`power supplies for commercial products and scientific instrumentation.
`
`6.
`
`I am a licensed Professional Engineer and have extensive industry
`
`experience in circuit design, fabrication, and manufacture of Dynamic Random
`
`Access Memory (DRAM) semiconductor integrated circuit chips, Phase-Change
`
`Random Access Memory (PCRAM) chips, and CMOS Image Sensors (CISs) at
`
`Micron Technology, Inc. (“Micron”) in Boise, Idaho. I spent considerable time
`
`working on the development of Flash memory chips while at Micron. My efforts
`
`resulted in more than a dozen patents relating to Flash memory. One of my
`
`projects at Micron included the development, design, and testing of circuit design
`
`techniques for a multi-level cell (MLC) Flash memory using signal processing.
`
`Among many other experiences, I led the development of the delay locked loop
`
`3
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`(DLL) in the late 1990s so that Micron DRAM products could transition to the
`
`DDR memory protocol for addressing and controlling accesses to memory via
`
`interprocess communications (IPC) with the memory controller (MC). I provided
`
`technical assistance with Micron’s acquisition of Photobit during 2001 and 2002,
`
`including transitioning the manufacture of CIS products into Micron’s process
`
`technology. Further, I did consulting work at Sun Microsystems and then Oracle
`
`on the design of memory modules during 2009 and 2010. This work entailed the
`
`design of low-power, high-speed, and wide interconnection methods with the goal
`
`of transmitting data to/from the memory module and the MC at higher speeds.
`
`7.
`
`I have extensive experience in the development of instrumentation and
`
`commercial products in a multitude of areas including: integrated
`
`electrical/biological circuits and systems, array (memory, imagers, and displays)
`
`circuit design, CMOS analog and digital circuit design, diagnostic electrical and
`
`electro-optic instrumentation for scientific research, CAD tool development and
`
`online tutorials, low-power interconnect and packaging techniques, design of
`
`communication/interface circuits (to meet commercial standards such as USB,
`
`firewire, DDR, PCIe, SPI, etc.), circuit design for the use and storage of renewable
`
`energy, and power electronics. For example, a part of my research at Boise State,
`
`for many years, focused on the use of Thru-Silicon-Vias (TSVs), aka Thru-Wafer
`
`Vias (TWVs), for high-density packaging. These packaging techniques were
`
`4
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`utilized in the memory module development work I did with Sun Microsystems
`
`and Oracle. As another example, I’ve designed circuitry for use in implementing
`
`Universal Serial Bus (USB) interfaces circuits while I did consulting at Tower
`
`Semiconductor. I designed PCI communication circuits for IPC between a
`
`Graphics Processor Unit (GPU) and memory while consulting for Rendition, Inc.
`
`8.
`
`My current research work is focused in part on the design of
`
`integrated circuits for wireless sensing using LIDAR (LIght Detection And
`
`Ranging). I have worked with several companies in the development of these
`
`circuits and systems including Aerius Photonics and FLIR. In the early 1990s I
`
`worked on wireless systems for wideband impulse radar while at Lawrence
`
`Livermore Laboratory. Further, part of my research for several years focused on
`
`the digitization of IQ channels using delta-sigma modulation. The knowledge and
`
`experience gained from this effort are reflected in my book CMOS Mixed-Signal
`
`Circuit Design and a presentation, which I presented at several companies and
`
`universities, http://cmosedu.com/jbaker/papers/talks/BP_DSM_talk.pdf.
`
`B.
`9.
`
`Academic Experience
`I was an adjunct faculty member in the Electrical Engineering
`
`department of the University of Nevada, Las Vegas in 1991 and 1992. From 1993
`
`to 2000, I served on the faculty at the University of Idaho as an Assistant Professor
`
`and then as a tenured Associate Professor of Electrical Engineering. In 2000, I
`
`5
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`joined a new Electrical and Computer Engineering program at Boise State
`
`University (“BSU”) where I served as department chair from 2004 to 2007. At
`
`BSU, I helped establish graduate programs in Electrical and Computer Engineering
`
`including, in 2006, the university’s second Ph.D. degree. In 2012, I re-joined the
`
`faculty at UNLV. Over the course of my career as a professor I have advised over
`
`85 masters and doctoral students.
`
`10.
`
`I have been recognized for my contributions as an educator in the
`
`field. While at Boise State University, I received the President’s Research and
`
`Scholarship Award (2005), Honored Faculty Member recognition (2003), and
`
`Outstanding Department of Electrical Engineering Faculty recognition (2001). In
`
`2007, I received the Frederick Emmons Terman Award (the “Father of Silicon
`
`Valley”). The Terman Award is bestowed annually upon an outstanding young
`
`electrical/computer engineering educator in recognition of the educator’s
`
`contributions to the profession. In 2011 I received the IEEE Circuits and Systems
`
`Education Award. I received the Tau Beta Pi Outstanding Electrical and Computer
`
`Engineering Professor Award every year it was awarded while I have been back at
`
`UNLV.
`
`11.
`
`I have authored several books and papers in the electrical and
`
`computer engineering area. My published books include CMOS Circuit Design,
`
`Layout, and Simulation (Baker, R.J., Wiley-IEEE, ISBN: 9781119481515 (4th ed.,
`
`6
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`2019)) and CMOS Mixed-Signal Circuit Design (Baker, R.J., Wiley-IEEE, ISBN:
`
`9780470290262 (2nded., 2009) and ISBN: 9780471227540 (1st ed., 2002)). I co-
`
`authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth, B.,
`
`Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 9780470184752 (2008)),
`
`and DRAM Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE,
`
`ISBN: 0780360141 (2001)) I contributed as an editor and co-author on several
`
`other electrical and computer engineering books.
`
`C.
`12.
`
`Other Relevant Experience
`I have performed technical and expert witness consulting for over 100
`
`companies and laboratories and given more than 50 invited talks at conferences,
`
`companies, and Universities. Further, I am the author and co-author of more than
`
`100 papers and presentations in the areas of electrical and computer engineering
`
`design, fabrication and packaging.
`
`13.
`
`I currently serve, or have served, as a volunteer on: the IEEE Press
`
`Editorial Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
`
`Microelectronic Systems (2010-2018); as the Technical Program Chair of the 2015
`
`IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS
`
`2015); on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
`
`(2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015); and as the
`
`Technology Editor (2012-2014) and Editor-in-Chief (2015-2020) for the IEEE
`
`7
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`Solid-State Circuits Magazine. These meetings, groups, and publications are
`
`intended to allow researchers to share and coordinate research. My active
`
`participation in these meetings, groups, and publications allowed me to see what
`
`other researchers in the field have been doing.
`
`14.
`
`In addition to the above, I am an IEEE Fellow for contributions to
`
`memory circuit design and a member of the honor societies Eta Kappa Nu and Tau
`
`Beta Pi.
`
`15.
`
`I understand my CV is being filed herewith as Exhibit Ex-1003.
`
`II. OVERVIEW OF THE TECHNOLOGY
`16. As of early 2000, when the ’134 Patent was filed, integrated circuit
`
`memories had been well known for decades and were in use widely throughout the
`
`semiconductor, computer, and other industries. At a basic level, memories are
`
`comprised of circuit elements that store information to represent one of two logic
`
`states, a 1 (true or ON) or a 0 (false or OFF).
`
`17.
`
`The most common form of memory is dynamic random access
`
`memory, or DRAM. DRAM uses a transistor and a capacitor to form a memory
`
`cell. A charged capacitor represents a 1, and a discharged capacitor represents a 0.
`
`A charged capacitor, however, tends to leak charge, and it must be periodically
`
`refreshed. Thus, the DRAM must read and write back data to each DRAM cell
`
`periodically to refresh the DRAM memory cell’s contents.
`
`8
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`18. Another form of integrated circuit memory is static random access
`
`memory, or SRAM. Instead of a capacitor to store charge, SRAM uses transistors
`
`in each memory cell arranged as a flip-flop. An advantage of SRAM is that
`
`because it does not use a capacitor to maintain a data state. Therefore the leakage
`
`that happens in a DRAM is not a concern in an SRAM. The SRAM does not need
`
`to be refreshed. However, the disadvantage is that an SRAM cell takes up more
`
`area on a chip than DRAM, so it has lower storage capacity for a given chip area.
`
`For a fixed amount of memory SRAM is therefore more expensive than DRAM.
`
`19. Memory cells are typically arranged in an array of columns (bitlines)
`
`and rows (wordlines). The intersection of a bitline and a wordline is the address of
`
`the memory cell at that location. When a controller asserts an address of a given
`
`cell then data can be read from or written to that cell.
`
`20. Often, the data to be accessed in a memory array is stored in
`
`contiguous cells. Thus, in the late 1980’s or early 1980’s, it was realized that more
`
`efficient data throughput could be achieved by reading or writing data to or from
`
`memory in bursts. In other words, the controller would assert a single address, and
`
`then circuit logic would automatically generate a series of addresses offset from
`
`that initial address to transfer a series of data values in response to a single address.
`
`See, for example, U.S. Patent No. 4,366,539 to Johnson et al., entitled “Memory
`
`9
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`controller with burst mode capability,” issued in 1982. Such burst transfers reduce
`
`overhead and allow for higher data throughput.
`
`21.
`
`In an SRAM system, because no refresh is required, burst data
`
`transfers can be initiated and allowed to run to completion with no need to
`
`interrupt them. In a DRAM system, however, periodic refresh of the memory cells
`
`is required, and if the timing is not managed efficiently, a data burst might be
`
`interrupted in order to carry out a refresh cycle. However, this problem was
`
`overcome by arranging different memory partitions in such a way that a refresh
`
`cycle for one partition was hidden behind a burst read or write of another partition,
`
`a technique called “hidden memory refresh.” See, for example, U.S. Patent No.
`
`4,357,686 to Scheuneman, issued in 1982 and entitled “Hidden memory refresh,”
`
`which discusses hidden memory refresh operations in a system using burst-mode
`
`memory transactions.
`
`III.
`
`SUMMARY OF GROUNDS
`22.
`I understand that AMD is seeking review and cancellation of all 21
`
`claims of the ’134 Patent under 35 U.S.C. §102 and/or §103 based on the following
`
`grounds:
`
`Ground 1: Claims 1-3, 8, 12-13, 16, and 17 are anticipated by US 6,115,280
`
`(“Wada”);
`
`10
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`Ground 2: Claims 1-4, 8, 12-14, 16, and 17 are rendered obvious by Wada
`
`in view of the knowledge of a person of ordinary skill in the art (“POSITA”);
`
`Ground 2a: Claims 1-4, 8, 12-14, 16, and 17 are rendered obvious by Wada
`
`and US 5,584,033 (“Barrett”) in view of the knowledge of a POSITA;
`
`Ground 3: Claims 4-7, and 18-20 are rendered obvious by Wada and U.S.
`
`6,185,149 (“Fujioka”) in view of the knowledge of a POSITA.
`
`Ground 3a: Claims 4-7, and 18-20 are rendered obvious by Wada, Barrett,
`
`and Fujioka in view of the knowledge of a POSITA
`
`Ground 4: Claims 9-10, 14, and 21 are rendered obvious by Wada and US
`
`6,226,755 (“Reeves”) in view of the knowledge of a POSITA;
`
`Ground 4a: Claims 9-10, 14, and 21 are rendered obvious by Wada, Barrett,
`
`and Reeves in view of the knowledge of a POSITA;
`
`Ground 5: Claims 11 and 15 are rendered obvious by Wada and US
`
`5,784,331 (“Lysinger”) in view of the knowledge of a POSITA; and
`
`Ground 5a: Claims 11 and 15 are rendered obvious by Wada, Barrett, and
`
`Lysinger in view of the knowledge of one a POSITA.
`
`23. None of the references relied upon in the Petition was cited by the
`
`Examiner during prosecution of the ’134 Patent. Ex-1001, 1.
`
`11
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`
`IV. LEGAL STANDARDS
`24.
`I am not an attorney. In this declaration, I apply relevant legal
`
`principles as they have been provided to me by attorneys to arrive at the opinions
`
`set forth in this declaration.
`
`25. Anticipation: I understand a challenged claim may be invalid as
`
`“anticipated” if all elements of the challenged claim are disclosed in the prior art
`
`reference. The prior art reference need not use the same words as the challenged
`
`claim, but all elements must be disclosed so that a POSITA could make and use the
`
`claimed subject matter.
`
`26.
`
`I understand that when a challenged claim covers several structures,
`
`either generically or as alternatives, the claim is deemed anticipated if any of the
`
`structures within the scope of the claim is found in the prior art reference.
`
`27. Obviousness: I understand that even if a challenged claim is not
`
`anticipated, it is still invalid if the differences between the claimed subject matter
`
`and the prior art are such that the claimed subject matter would have been obvious
`
`to a person of ordinary skill in the pertinent art at the time the alleged invention.
`
`28.
`
`I understand that an obviousness analysis includes the consideration
`
`of factors such as (1) the scope and content of the prior art, (2) the differences
`
`between the prior art and the challenged claim, (3) the level of ordinary skill in the
`
`pertinent art, and (4) “secondary” or “objective” evidence of non-obviousness.
`
`12
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`Secondary or objective evidence of non-obviousness includes
`
`29.
`
`evidence of: (1) a long felt but unmet need in the prior art that was satisfied by the
`
`claimed invention; (2) commercial success or the lack of commercial success of
`
`the claimed invention; (3) unexpected results achieved by the claimed invention;
`
`(4) praise of the claimed invention by others skilled in the art; (5) taking of licenses
`
`under the patent by others; (6) deliberate copying of the claimed invention; and (7)
`
`contemporaneous and independent invention by others. However, I understand that
`
`there must be a relationship between any secondary evidence of non-obviousness
`
`and the claimed invention.
`
`30.
`
`I understand that a challenged claim can be invalid for obviousness
`
`over a combination of prior art references if a POSITA would have had a
`
`motivation to combine those references. The motivation to combine may come
`
`from the references themselves, from simple common sense, or market demand.
`
`31. A POSITA may combine the teachings of multiple publications even
`
`if they do not necessarily fit perfectly together. Therefore, I understand that
`
`references for obviousness need not fit perfectly together like puzzle pieces.
`
`Instead, I understand that obviousness analysis takes into account inferences,
`
`creative steps, common sense, and practical logic and applications that a person of
`
`ordinary skill in the art would employ under the circumstances.
`
`13
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`I understand that a claim can be obvious in light of a single reference,
`
`32.
`
`if the elements of the challenged claim that are not explicitly or inherently
`
`disclosed in the reference can be supplied by the common sense of one of skill in
`
`the art.
`
`33. Claim Construction: I understand that the interpretation of claims is
`
`a legal issue the must be resolved before an invalidity analysis can be performed. I
`
`have been instructed by attorneys to apply the claim constructions set forth in the
`
`accompanying petition. Where competing proposals for construction have been
`
`identified, I apply the prior art under all proposed constructions.
`
`34.
`
`I understand that certain claim limitations may be construed under 35
`
`U.S.C. § 112 ¶ 6 as what is known as a “means plus function” limitation. Such
`
`terms are interpreted to cover only the corresponding structure described in the
`
`specification, and equivalents thereof. I understand that a structure is considered
`
`structurally equivalent to the corresponding structure identified in the specification
`
`if the differences between them are insubstantial, such as when the structure
`
`performs the same function in substantially the same way to achieve substantially
`
`the same result. I further understand that a structural equivalent must have been
`
`available at the time of the issuance of the claim.
`
`14
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`
`V.
`
`THE CHALLENGED PATENT
`35.
`The ’134 Patent is directed to an integrated circuit comprising a
`
`memory and a logic circuit and a method for addressing the memory circuit with a
`
`burst of internal address signals that may be non-interruptible. Ex. 1001 at
`
`Abstract. A device reads data from memory by asserting an address and receiving
`
`data from the memory location specified by that address. In “burst” mode,
`
`however, a controller asserts a single address, and memory circuit logic generates a
`
`series of internal addresses, typically offset from the initial address as address+0,
`
`address+1, address+2, etc., and returns data from multiple memory locations
`
`specified by those internal addresses in response to one external addresses.
`
`36.
`
`The preferred embodiment of the alleged invention seen in Fig. 1 of
`
`the ‘134 patent is “configured to transfer a fixed number of words of data with
`
`each access (e.g., read or write).” Id. at 2:28-30. An array of memory cells may be
`
`addressed by a “burst address counter” circuit that receives an external address
`
`(ADDR_EXT), a clock (CLK), and control signals (e.g., LOAD, ADV) and that
`
`outputs a burst of internal addresses ADDR_INT that access the memory cells.
`
`See id. at 2:31-46. Specifically, Fig. 1 depicts “Burst Address Counter / Register”
`
`102, which latches in external address ADDR_EXT when the LOAD signal is
`
`asserted. Id. at 3:14-19. When ADV is asserted, a fixed number of internal
`
`addresses (ADDR_INT) are generated in response to the CLK signal. Id. at 3:19-
`
`15
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`24. “Once the circuit 102 has started generating the fixed number of addresses, the
`
`circuit 102 will generally not stop until the fixed number of addresses has been
`
`generated (e.g., a non-interruptible burst).” Id. at 3:25-29.
`
`37.
`
`The ’134 Patent discloses two embodiments of the “Burst Address
`
`Counter” 102, seen in Figs. 2 and 3. In Fig. 2, below, an initial address
`
`(ADDR_EXT) is latched into the address counter register 126 when LOAD is
`
`asserted. Id. at 4:6-8. When ADV is asserted, the BURST_CLK signal is
`
`generated in response to CLK and increments the address in the address counter
`
`register 126 to produce a predetermined number of internal address values
`
`ADDR_INT (116). Id. at 4:6-14.
`
`16
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`
`38.
`
`In Fig. 3, an n-bit external address (ADDR_EXT) is divided into an
`
`m-bit portion and a k-bit portion. Id. at 4:18-25. The k-bit portion is sent to
`
`counter (138) and is incremented by the CLK signal when ADV is asserted. Id. at
`
`4:28-33. A multiplexer (136) selects either the latched k-bit portion of the external
`
`address (142) or the k-bit output of the counter (138) and concatenates it with the
`
`latched m-bit portion of the address to create the internal addresses (ADDR_INT)
`
`that are used to address the memory array. Id. at 4:34-39.
`
`17
`
`Petitioner STMicroelectronics, Inc., Ex. 1002
`IPR2021-00355
`
`

`

`U.S. Patent No. 6,651,134
`Baker Declaration
`
`VI. PATENT PROSECUTION HISTORY
`39.
`I reviewed the file history of the application that issued as the ’134
`
`Patent. The application was repeatedly rejected during prosecution and eventually
`
`allowed after the Examiner did not file a response to the applicant’s appeal brief.
`
`40. On 10/1/2001, the Examiner rejected the 17 pending claims, rejecting
`
`dependent claims 6 and 15 (which recite that the burst l