NAVAL POSTGRADUATE SCHOOL
`Monterey, California
`
`THESIS
`
`A DIRECT SEQUENCE - CODE DIVISION MULTIPLE
`ACCESS/DIFFERENTIAL PHASE-SHIFT KEYING
`(DS-CDMA/DPSK) MODEM DESIGN
`
`by
`
`Önder Kara
`
`March 1997
`
`Thesis Advisor: Tri T. Ha
`Co-Advisor: R. Clark Robertson
`Approved for public release; distribution is unlimited.
`
`19971119 053 [OTIC QUALEfif W SPECTED 3
`
`Petitioner's Exhibit 1018
`Page 001
`
`

`

`REPORT DOCUMENTATION PAGE
`
`Form Approved OMB No. 0704-0188
`
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`AGENCY USE ONLY (Leave blank)
`
`REPORT TYPE AND DATES COVERED
`Master's Thesis
`
`2.
`
`REPORT DATE
`March 1997
`
`TITLE AND SUBTITLE A DIRECT SEQUENCE - CODE DIVISION
`MULTIPLE ACCESS/DIFFERENTIAL PHASE-SHIFT KEYING
`(DS-CDMA/DPSK) MODEM DESIGN
`6. AUTHOR(S) Kara, Onder
`
`7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)
`Naval Postgraduate School
`Monterey, CA 93943-5000
`
`J. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES)
`
`5.
`
`FUNDING NUMBERS
`
`PERFORMING
`ORGANIZATION
`REPORT NUMBER
`
`10. SPONSORING/MONITORING
`AGENCY REPORT NUMBER
`
`11. SUPPLEMENTARY NOTES The views expressed in this thesis are those of the author and do not reflect the official
`policy or position of the Department of Defense or the U.S. Government.
`
`12a. DISTRIBUTION/AVAILABILITY STATEMENT
`Approved for public release; distribution is unlimited.
`
`13. ABSTRACT (maximum 200 words)
`
`12b.
`
`DISTRIBUTION CODE
`
`The development of a differential phase-shift keying (DPSK), direct sequence, spread spectrum modem is
`conducted for the purpose of creating a prototype design to be implemented in a multi-user environment. In this
`design, a maximal length sequence of 31 chips is used to spread the information data. The multi-user performance
`analysis is performed by using Bit Error Rate (BER) test equipment (1645 Hewlett Packard data error analyzer). A
`multi-user interference cancellation circuit for two users is introduced, and measurements are performed to show its
`effectiveness.
`The design itself encompasses the selection of components and demonstrates that the preliminary operational
`characteristics of a spread spectrum DPSK modem scheme for CDMA application can be achieved.
`
`14. SUBJECT TERMS Spread Spectrum Modem, Direct Sequence, Code Division Multiple
`Access, Gold Sequences
`
`15. NUMBER OF
`PAGES
`
`71
`16. PRICE CODE
`
`17. SECURITY CLASSIFICA-
`TION OF REPORT
`Unclassified
`
`18. SECURITY CLASSIFI-
`CATION OF THIS PAGE
`Unclassified
`
`19. SECURITY CLASSIFICA-
`TION OF ABSTRACT
`Unclassified
`
`20. LIMITATION OF
`ABSTRACT
`UL
`
`NSN 7540-01-280-5500
`
`Standard Form 298 (Rev. 2-89)
`Prescribed by ANSI Std. 239-18 298-102
`
`'»TIC QUÄLET? mSSEÜSBD S'
`
`Petitioner's Exhibit 1018
`Page 002
`
`

`

`Page 003——
`
`Petitioner's Exhibit 1018
`
`Petitioner's Exhibit 1018
`Page 003
`
`

`

`Approved for public release; distribution is unlimited.
`
`A DIRECT SEQUENCE - CODE DIVISION MULTIPLE
`ACCESS/DIFFERENTIAL PHASE-SHIFT KEYING (DS-CDMA/DPSK) MODEM
`DESIGN
`
`Önder Kara
`Lieutenant Junior Grade, Turkish Navy
`B.S., Turkish Naval Academy, 1991
`
`Submitted in partial fulfillment of the
`requirements for the degree of
`
`MASTER OF SCIENCE IN ELECTRICAL ENGINEERING
`
`from the
`
`NAVAL POSTGRADUATE SCHOOL
`March 1997
`
`//
`
`Author:
`
`Approved by:
`
`Under Kara
`
`7w T. 44-t^L
`Tri Ha, Thesis Advisor
`
`Herschel H. Loomis, Jr., Chajpman
`Department of Electrical and Computer Engineering
`
`Petitioner's Exhibit 1018
`Page 004
`
`

`

`IV iv
`
`Page 005
`—
`
`Petitioner's Exhibit 1018
`
`Petitioner's Exhibit 1018
`Page 005
`
`

`

`ABSTRACT
`
`The development of a differential phase-shift keying (DPSK), direct
`
`sequence, spread spectrum modem is conducted for the purpose of creating a
`
`prototype design to be implemented in a multi-user environment. In this design,
`
`a maximal length sequence of 31 chips is used to spread the information data.
`
`The multi-user performance analysis is performed by using Bit Error Rate (BER)
`
`test equipment (1645 Hewlett Packard data error analyzer). A multi-user
`
`interference cancellation circuit for two users is introduced, and measurements
`
`are performed to show its effectiveness.
`
`The design itself encompasses the selection of components and
`
`demonstrates that the preliminary operational characteristics of a spread
`
`spectrum DPSK modem scheme for CDMA application can be achieved.
`
`Petitioner's Exhibit 1018
`Page 006
`
`

`

`VI vi
`
`Page 007
`—
`
`Petitioner's Exhibit 1018
`
`Petitioner's Exhibit 1018
`Page 007
`
`

`

`TABLE OF CONTENTS
`
`I. INTRODUCTION 1
`
`II. THE DESIGN OF A DS-CDMA/DPSK MODEM 3
`
`A. GENERAL 3
`
`B. PN GENERATOR 6
`
`C. MODULATOR 11
`
`D. DEMODULATOR 15
`
`E. ACQUISITION 19
`
`F. SYNCHRONIZATION 23
`
`G. FILTERS 27
`
`H. CODE DIVISION MULTIPLE ACCESS 28
`
`III. EXPERIMENTAL RESULTS 33
`
`IV. MULTI-USER INTERFERENCE CANCELLATION 37
`
`V. CONCLUSIONS 45
`
`APPENDIX A. BLOCK DIAGRAMS 47
`
`APPENDIX B. CIRCUITS 51
`
`APPENDIX C. THE DESIGN OF THE BAND PASS FILTER 57
`
`LIST OF REFERENCES 59
`
`INITIAL DISTRIBUTION LIST 61
`
`VII
`
`Petitioner's Exhibit 1018
`Page 008
`
`

`

`VIII viii
`
`Petitioner's Exhibit 1018
`
`Page 009
`
`Petitioner's Exhibit 1018
`Page 009
`
`

`

`I. INTRODUCTION
`
`Coordination and control of spread spectrum networks consist of the usual
`
`issues such as architecture, protocols, throughput, system delay, routing and
`
`relay control, gateways, data quality, acknowledgment, and cryptographic key
`
`distribution. In addition, networking of spread spectrum radios involves
`
`monitoring signaling activity, controlling the number of users, taking advantage of
`
`the increase in throughput of code division multiple access (CDMA), and
`
`maintaining gateway interoperability.
`
`Code division multiple access [Ref.1] is a very attractive area for research
`
`and development in satellite and cellular network systems because of the
`
`increasing demand on capacity and privacy.
`
`Entering a CDMA network poses difficulties for both receivers and
`
`transmitters. As a receiver, network entry requires code acquisition and
`
`synchronization. As a transmitter, uncontrolled network entry may cause
`
`interference at other receiving nodes in the network. CDMA systems utilize a
`
`high chip rate coding sequence to spread and despread the information data to
`
`overcome these difficulties. By using a pseudo-noise (PN) sequence, the
`
`baseband information spectrum is spread over a wideband spectrum. The
`
`CDMA signal usually has a maximum power spectral density below the channel
`
`Petitioner's Exhibit 1018
`Page 010
`
`

`

`noise level. When two CDMA signals share the same frequency band, a certain
`
`amount of crosstalk, or mutual interference, occurs.
`
`The interference can be minimized since it is possible to design spreading
`
`sequences, such as Gold sequences, with low cross-correlation values so that
`
`the different code sequences are nearly orthogonal. The number of users in the
`
`same frequency band has an upper limit since system performance degrades as
`
`the number of users increases [Ref.1].
`
`The objective of this thesis is to design and build a direct sequence code
`
`division multiple access, differential phase-shift keying (DS-CDMA/DPSK) spread
`
`spectrum modem that can be used in satellite network systems and to test its
`
`multi-user performance. An interference cancellation circuit is introduced to test
`
`the elimination of multi-user interference for two users. The following initial
`
`parameters are provided as guidance in formulating the design:
`
`1. DPSK modulation with coherent detection [Ref.2].
`
`2. Direct sequence spread spectrum using Gold Sequences of 31 chips
`
`generated from a preferred-pair of m-sequences [Ref.1].
`
`3. Each data bit to be spread by one complete Gold sequence [Ref.1].
`
`4. Data bit rate equal to 1200 bits per second.
`
`5. Four users in the frequency band.
`
`The basic concept of the PN sequence synchronization circuit is taken
`
`from [Ref. 1,3,4,5]. The basic characteristics of code division multiple access
`
`(CDMA) are taken from [Ref. 1,6].
`
`2
`
`Petitioner's Exhibit 1018
`Page 011
`
`

`

`II. THE DESIGN OF DS-CDMA/DPSK MODEM
`
`A. GENERAL
`
`The modulator section of the DS-CDMA/DPSK modem design has six
`
`main functional blocks:
`
`1. Pseudo-random noise sequence generator [Ref. 2,3,4,5].
`
`2. Data source and clock generator [Ref.7].
`
`3. Differential encoder [Ref.8,9].
`
`4. Level shifter [Ref.8].
`
`5. Low pass filter and mixer [Ref.8,9,10,11].
`
`6. Signal Generator (carrier).
`
`The DPSK modulator functional block diagram is shown in Figure 1.
`
`Master Clock
`
`PN
`Generator
`
`r»
`
`Differential
`Encoder
`
`Data
`
`Data
`Generator
`
`'
`
`S *\ ,
`
`\ )
`XOR Gate
`
`Level
`Shifter
`
`Data
`Clock
`Generator
`
`DS-SS/DPSK
`X^lgna^
`
`LPF
`
`Carrier
`Signal
`Generator
`
`Figure 1. The DPSK Modulator Functional Block Diagram.
`
`Petitioner's Exhibit 1018
`Page 012
`
`

`

`A 37.2 kHz master clock is generated by a WAVETEK Model 142 function
`
`generator. This master clock provides clock pulses for the PN generator and the
`
`pattern generator (Model 1645A).
`
`Two 5-bit shift registers are used as a pseudo-random Gold sequence
`
`generator in this spread spectrum modulator. By design, each data bit will
`
`contain an entire PN sequence of 31 chips. The PN sequence is also used to
`
`generate a 1.2 kHz clock which in turn is used to trigger a 1.2 kbps data signal
`
`from the pattern generator.
`
`The data is spread digitally by using a modulo-2 adder as detailed later.
`
`After spreading the data, the signal levels are shifted from TTL levels to± 5 volts.
`
`A low pass filter with a cut-off frequency of 37.2 kHz was designed and built to
`
`suppress the side lobes of the baseband spread spectrum signal. The resultant
`
`signal at the output of low pass filter is mixed with the 76.2 kHz carrier signal.
`
`This DS-CDMA/DPSK signal is connected to the demodulator directly via
`
`hardwire.
`
`The demodulator functional block diagram is obviously more complicated
`
`than that of the modulator. There are several functions performed by the
`
`demodulator:
`
`1. Signal demodulation [Ref.6,14,17,21].
`
`2. Spectrum despreading [Ref. 12].
`
`3. PN sequence generation [Ref.3,23].
`
`4. Acquisition and tracking [Ref.4,6].
`
`Petitioner's Exhibit 1018
`Page 013
`
`

`

`The demodulator functional block diagram is shown in Figure 2.
`
`Keceivea
`
`Signal
` p
`
`Despreader/
`
`Demodulator
`
`Demodulated
`
`»-
`
`Data
`Differential
` ^.
`
`Encoder
`
`PN
`
` ►
`
`Tracking
`
`i L
`
`*—1
`
`a.
`
`Carrier
`
`Signal
`Generator
`
`PN
`Acquisition
`
`Figure 2. Demodulator Functional Block Diagram.
`
`The function of the PN acquisition subsystem is to bring the PN signal
`
`generated in the demodulator to within ±TJ2 of the received PN signal where Tc
`
`is the chip duration. To obtain the phase difference in the range of ±TJ2, the
`
`acquisition subsystem searches through a set of 31 different discrete phases
`
`and selects the one which yields the highest correlation with the incoming PN
`
`signal.
`
`Once the phase of the local PN signal is within ±TJ2 of the incoming PN
`
`signal, the tracking circuit attempts to bring the phase difference to zero.
`
`The PN signal from the tracking circuit and a coherent carrier are used for
`
`despreading and demodulation to obtain an estimate of the transmitted data.
`
`A detailed block diagram of demodulator is shown in Figure 3.
`
`Petitioner's Exhibit 1018
`Page 014
`
`

`

`Received
`Signal
`
`BPF
`
`Envelope
`Detector
`
`w
`
`Loop
`
`Filter
`
`vco
`
`Early / Late
`
`Generator
`
`T ^©
`
`Signal
`
`Generator
`
`Integrator
`+
`Amplifier
`
`Sample &
`
`Hold
`
`Level
`
`Shifter
`
`Differential
`
`Decoder
`
`Phase
`Update
`
`Circuit
`
`BPF
`
`Envelope
`
`Detector
`
`Comparator
`
`.Clock
`
`Demodulated
`Signal
`
`Figure 3. The Functional Block Diagram of the Demodulator.
`
`PN acquisition is performed before tracking. Since the carrier frequency
`
`and phase are available, coherent carrier demodulation is used with the
`
`acquisition circuit. Once the PN code phase has been acquired, the PN tracking
`
`circuit is initiated.
`
`B. PN GENERATOR
`
`The generation of PN sequences for spread spectrum applications is a
`
`topic that has received considerable attention in the technical literature [Ref.1,3].
`
`The baseband frequency spectrum of the PN sequence which is used in this
`
`design is shown in Figure 4.
`
`Petitioner's Exhibit 1018
`Page 015
`
`

`

`REF 26. O dBm MARKER 37 200. O Hz
`10 dB/DIV RANGE 30. O dBm -24.9 dBm
` :— - "| 1 :
`\ i i • ■ !
`
`i
`
`i ! i
`
`j
`
`
`
`i |"TtoMi i
`
`1 m'
`1 i ® !
`i
`
`i
`i
`
`1
`i i
`
`; i 5
`
`| ''"^ \j0f1QW -Lflm
`! i ! \f :
`
`in I
`
`! ■ m
`
`,
`
`i
`
`\
`
`i !
`I 1
`i j
`i |
`
`i —.
`
`i i ! ' I
`i ■■
`START .O Hz
`VBW 3 KHz
`RBW 1 KHz
`
`: l l
`STOP 100 000. O Hi
`ST .2 SEC
`
`Figure 4. Power Spectral'Density of the PN Sequence.
`
`The cross-correlation properties of PN sequences are as important as the
`
`auto-correlation properties for CDMA applications. For example, in CDMA each
`
`user is assigned a particular PN sequence. Ideally, the PN sequences among
`
`users should be mutually orthogonal. However, the PN sequences used in
`
`practice exhibit some cross-correlation [Ref. 1,6].
`
`High peak values for the cross-correlations are undesirable in CDMA.
`
`Although it is possible to select a small subset of m-sequences that have
`
`relatively small cross-correlation peak values, the number of sequences in the
`
`set is usually too small for CDMA applications. PN sequences with better
`
`periodic cross-correlation than m-sequences are given by Gold. Two m-
`
`Petitioner's Exhibit 1018
`Page 016
`
`

`

`sequences of length n with a periodic cross-correlation function that takes on the
`
`possible values {-1, -t(m), t(m) -2} where t(m)=1 + 2L(m+2)/2j , with |_cj denoting
`
`the integer part of the real number c, are called preferred sequences. From a
`
`pair of preferred sequences, a set of sequences of length n are constructed by
`
`taking the modulo-2 sum of the first sequence with n cyclic shifted versions of the
`
`second sequence or vice versa. Thus, n new periodic sequences with period
`
`n=2m-1 (2-1)
`
`are obtained. The sequences constructed in this manner are called Gold
`
`sequences [Ref.2].
`
`A generalized Gold sequence generator configuration is taken from Dixon
`
`[Ref.3] and shown in Figure 5.
`
`Shift Register 1
`
`Code 1
`
`Clock O
`
`Code 3
`
`Shift Register 2
`
`Code 2
`
`Figure 5. The Configuration of the Gold Code Sequence Generator. [Ref.3]
`
`Each m-sequence generator itself consists of two 4-bit, serially connected
`
`feedback shift registers. The main structure of the PN generator design is taken
`
`from Pickholtz [Ref. 4]. The illustration of the Gold sequence generation is
`
`shown in Figure 6.
`
`Petitioner's Exhibit 1018
`Page 017
`
`

`

`In the design of the first of the two m-sequence generators, the second
`
`and fifth stages of the shift register are modulo-2 added by an exclusive OR gate
`
`[Fig.6]. The resultant logic level is fed back to the input of the third stage of the
`
`shift register. For the second of the two m-sequence generators, the fourth and
`
`fifth stages of the shift register are modulo-2 added, and the resultant signal is
`
`fed back to the input of the fifth stage of the shift register. Similarly, the second
`
`and fifth stages are also modulo-2 added, and the resultant signal is fed back to
`
`the input of the third stage of the shift register. The resultant PN sequences,
`
`which are the outputs of the fifth stage of each shift register, are maximal length
`
`sequences with outputs consisting of a series of TTL levels in pseudo random
`
`order. This binary sequence is repeated every 31 clock cycles and each
`
`sequential pattern is identical.
`
`Figure 6. Illustration of the Gold Code Generation [Ref.4]
`
`Petitioner's Exhibit 1018
`Page 018
`
`

`

`A representative sample of the first Gold sequence employed in the
`
`spreading and despreading sections is shown in Figure 7. A 31-bit period of the
`
`Gold sequence in Figure 7 is marked by the vertical dotted lines.
`
`+1V
`
`+5V
`
`Figure 7. Top: Clock (37.2 kHz).
`Bottom: PN Sequence (Gold Sequence).
`
`The Gold sequence which consists of two preferred m-sequences having
`
`the generator polynomials fi(x)=(1+x2+x5) and f2(x)=(1+x2+x4+x5) is shown in
`
`Figure 8 with the resultant Gold sequence f(x)=f1(x).f2(x)=(1+x+x3+x9+x10) [Ref.4].
`
`The generation of the 1.2 kbps data clock is accomplished internally by
`
`using the master clock used in the PN' generator. To accomplish this, all five
`
`outputs of the shift register stages are fed to an AND gate to generate a 1.2 kHz
`
`square wave clock which is used to trigger the 1.2 kbps data.
`
`10
`
`Petitioner's Exhibit 1018
`Page 019
`
`

`

`« 1.20 kH*
`
`■
`—4~
`
`+5V
`
`OV
`
`+5V
`
`OV
`
`+5V
`
`OV
`
`Figure 8. Top: First Preferred m Sequence. f1(x)=(1+x2+x5).
`Middle: Second Preferred m Sequence. f2(x)=(1+x2+x4+x5).
`Bottom: Gold Sequence. f(x)=(1+x+x3+x9+x10).
`(The vertical lines show a 31-bit period of the Gold sequence).
`
`C. MODULATOR
`
`For a DPSK signal, data bits are differentially encoded, and the
`
`information is contained in the change in phases between successive bits. The
`
`differential encoding operation is described mathematically by [Ref. 14]:
`
`ck= bk 0 Cd (2.2)
`
`where bk is the k th information bit into the encoder, ck is the k th output bit of the
`
`encoder, cvi is the (k-1) th encoded bit,-and © denotes modulo-2 addition. The
`
`output bit Q< represents a logic one by a change in polarity and a logic zero by
`
`no change in polarity. A practical implementation of Equation 2.2 is shown in
`
`Figure 9.
`
`11
`
`Petitioner's Exhibit 1018
`Page 020
`
`

`

`b(k)
`
`XOR
`
`/T\ c(k)
`J
`
`c(k-1)
`
`1 I I 1
`1
`4
`3
`2
`
`shift register
`
`I I I
`
`clock
`
`Figure 9. The Configuration of Differential Encoder.
`
`The differential encoder is constructed by employing an exclusive OR
`
`(XOR) gate and a four-bit shift register. The differentially encoded data is
`
`presented in Figure 10.
`
`Figure 10. Top: Information Data (bk).
`Bottom: Differentially Encoded Data (ck).
`
`12
`
`Petitioner's Exhibit 1018
`Page 021
`
`

`

`The generation of the DPSK modulated signal is achieved by two
`
`sequential mixing operations. The 1.2 kbps data sequence is mixed with the PN
`
`sequence in the modulator section to create the PN encoded data stream. An
`
`XOR gate is used for this process. The TTL voltages are converted to their
`
`analog equivalents for interfacing with the analog components in this design.
`
`The mixers employed for modulation consist of an XOR gate (7486) and
`
`an analog voltage multiplier (AD 534). The spreading section consists of two
`
`elements: the spreading gate and the level shifter. The spreading gate is an
`
`XOR gate that modulo-2 adds the 1.2 kbps data signal and the PN sequence
`
`with a chip rate of 37.2 kchip per second.
`
`The inputs to the XOR gate are the data stream (at 1.2 kbps) and the PN
`
`sequence generated by the PN generator section of the modulator. The output
`
`of the XOR gate can be thought of essentially as a bi-phase shifted PN
`
`sequence. Considering the length of the sequence (31 chips) as one period,
`
`each data transition, which contains 31 chips, causes the PN sequence to invert.
`
`The PN sequence phase relationship is thus similar to that of a bi-phase shifted
`
`sinusoid since the PN sequence is also a periodic wave form. The maximum
`
`periodicity is the reciprocal of the data rate, 833.33 \is.
`
`The PN output of the XOR is fed to a level shifter. The level shifting is
`
`accomplished by connecting the output of the spreading gate to a LM311
`
`comparator (with an amplification of 2:1) whose reference voltage is set at 2.5V,
`
`the mid-point between 0 and 5V. The resultant output is a balanced PN encoded
`
`13
`
`Petitioner's Exhibit 1018
`Page 022
`
`

`

`sequence with bipolar voltages of +5 and -5 volts as the digital logic PN
`
`sequence changes the logic levels between 0 and 5 volts, respectively. The
`
`resulting PN data stream from the comparator is interfaced with the (AD534)
`
`mixer. The AD 534 is a monolitic, laser trimmed, four-quadrant multiplier/divider
`
`having a maximum multiplication error of 0.25% [Ref. 13]. This signal is
`
`connected directly to the Y1 input of the mixer (AD534). The sinusoidal carrier
`
`from the signal generator is connected to X1 input of the mixer where X2, Y2,
`
`and Z2 are connected to ground. The mixer accomplishes multiplication
`
`according to [Ref. 13]:
`
`V^(Xl-XT-Y2)+Z2 (2-3)
`
`The phase reversals at the output of the modulator due to the PN code
`
`employed can be observed in Figure 11. The output is the carrier frequency
`
`changing its phase with the change of phase of the PN sequence.
`
`14
`
`Petitioner's Exhibit 1018
`Page 023
`
`

`

`+5V
`
`-5V
`
`+2V
`
`OV
`
`-2V
`
`Figure 11. Top: PN Code.
`Bottom: Modulator Output
`
`DEMODULATOR
`
`The coherent detection of DPSK signals assumes the availability of local
`
`carriers (reference signals) that are in perfect synchronism with the carriers in
`
`the transmitter.
`
`As shown in Figure 3, after the despreading process, the resultant band
`
`pass signal is translated to baseband by mixing it with the carrier signal
`
`(76.2kHz) having the same frequency and phase as the carrier in the modulator.
`
`The frequency translation is achieved by an AD534 multiplier. A fourth order
`
`low-pass filter with a cut-off frequency of 1.2 kHz suppresses the image
`
`frequencies after the mixing process. The frequency response of the low-pass
`
`filter is shown in Figure 12.
`
`15
`
`Petitioner's Exhibit 1018
`Page 024
`
`

`

`REF -a.5 dBm MARKER 1 200. 0 Hz
`2 dB/D IV RANGE lO. 0 dBm -9.96 dBm
`
`1
`1
`
`[W-rv—
`
`!
`i
`
`t
`
`i
`
`i
`r ' ""
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`\
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`\.
`3
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`START .0 Hz S1"H
`c
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`RBW 30 Hz VBW lOO Hz ST 6. B SEC
`
`Figure 12. Frequency Response of the Fourth Order Low-Pass Filter.
`
`The amplification factor of 0.1 of all the mixers employed in the
`
`demodulation process is compensated for by a non-inverting voltage amplifier
`
`(LM318) [Ref.8], The integrator output in the demodulator is shown in Figure 13.
`
`The resultant signal is sampled with the rising edge of the 1.2 kHz clock
`
`by a sample-and-hold circuit (LF398) and is then applied to a level shifter circuit
`
`(LM311).
`
`16
`
`Petitioner's Exhibit 1018
`Page 025
`
`

`

`« 1.20 "'
`
`^_^ » «B^^»
`
`*\y\/^
`
`+5V
`
`OV
`
`+.5V
`
`-.5V
`
`"^™ '
`: i
`i
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`; 1
`
`1
`: i
`
`*g >1V
`
`Figure 13. Top: Transmitted Data.
`Bottom: Integrator Output in the Demodulator.
`
`The last task in the DPSK demodulator is to decode the received data
`
`differentially. The differentially decoded data (bk) is related to the received data
`
`(Ck) by [Ref. 14]
`
`bk= ck © CM (2.4)
`
`The decoder is implemented by using a configuration similar to the encoder but
`
`with a slight difference. The decoder is shown in Figure 14. The decoding
`
`operation in the demodulator can easily be verified by substituting Equation (2.2)
`
`into Equation (2.4); i.e.,
`
`bk= (bk8 CM) 0 ck.,= bk
`
`(2.5)
`
`17
`
`Petitioner's Exhibit 1018
`Page 026
`
`

`

`Figure 14. The Configuration of the Decoder.
`
`The transmitted information signal and the received signal are shown in
`
`Figure 15.
`
`+2.5V
`ov
`
`+5V
`
`OV
`
`Figure 15. Top: Transmitted Information Signal.
`Bottom: Received Information Signal
`
`The other two functions performed by the receiver are acquisition and
`
`tracking, which are explained in the following sections in detail.
`
`18
`
`Petitioner's Exhibit 1018
`Page 027
`
`

`

`E. ACQUISITION
`
`PN acquisition is usually the first task that the receiver has to perform.
`
`The acquisition process brings the phases of the local and the incoming PN
`
`signals to within a certain range. This range must also be within the pull-in range
`
`of the tracking circuit. Acquisition was the most difficult and the most time
`
`consuming task in this receiver design. The block diagram of the acquisition
`
`circuit is shown in Figure 16.
`
`Received .
`Signal f
`
`^r
`
`w To Demodulator
`
`BPF
`
`Envelope
`
`Detector
`
`Y
`i
`
`PN
`Generator
`
`\
`Voltage
`Controlled
`Switch
`
`Phase
`Update
`Circuit
`
`p Comparator
`
`Figure 16. The Functional Block Diagram of the Acquisition Circuit
`
`As shown in Figure 16, the receiver generated PN sequence is applied to
`
`the Y., input of an AD534 multiplier and the incoming signal is applied to its X,
`
`input. The instantaneous output of the AD534 is characterized by one of two
`
`possibilities when the spread spectrum signal is present at the input of the
`
`demodulator. In the first case, the receiver generated PN sequence lines up
`
`chip for chip with the received PN sequence. In the second case, further
`
`spreading of the already widened frequency spectrum is caused by misalignment
`
`of the PN sequences. The multiplier output is connected through a band-pass
`
`19
`
`Petitioner's Exhibit 1018
`Page 028
`
`

`

`filter to an envelope detector. The voltage level at the envelope detector output
`
`is used to determine alignment or misalignment.
`
`In the uncorrelated case as shown in Figure 17, where the misalignment
`
`is one (greater than half) chip, the resulting signal at the output of the band pass
`
`filter is presented. The envelope detector output is rather low, approximately
`
`0.1V, when the incoming PN sequence is not aligned with the local PN
`
`sequence. When the two PN sequences are correlated, the output from the
`
`envelope detector is notably greater and ranges between 1.9V and 2.2V. Thus,
`
`a band of correlation exists within one half chip either early or late relative to the
`
`received PN sequence. In this region, alignment of the PN sequences used in
`
`the modulator and the demodulator is possible.
`
`The change from the acquisition to the synchronization mode is triggered
`
`by this higher output which is also used as an indication of acquisition of the
`
`incoming signal. In the analysis of the spectral outputs of the band-pass filter for
`
`each case, a difference in the correlated versus uncorrelated signals at the
`
`output of the envelope detector can be seen. The uncorrelated and correlated
`
`spectra as they appear on a spectrum analyzer from the output of the band-pass
`
`filter of the punctual channel are presented in Figures 19 and 20 where for this
`
`thesis the punctual sequence is defined as the PN sequence which despreads
`
`the received signal. Note that the output spectrum of the band-pass filter
`
`changes significantly when correlation occurs.
`
`20
`
`Petitioner's Exhibit 1018
`Page 029
`
`

`

`+5V
`
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`
`+5V
`
`OV
`
`+0.1V
`
`OV
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`-0.1V
`
`aifllli liiillfiiiim
`
`200*$
`
`Figure 17. Top: PN Sequence Used in Modulation.
`Middle: Punctual PN Sequence from Demodulator.
`Bottom: Band-Pass Filter Output (Uncorrelated).
`
`Figure 18. Top: PN Sequence Used in Modulation.
`Middle: Punctual PN Sequence from Demodulator.
`Bottom: Band-Pass Filter Output (Correlated).
`
`21
`
`Petitioner's Exhibit 1018
`Page 030
`
`

`

`REF 30. O dBm MARKER 78 191. 1 Hz
`10 dB/D IV RANGE 25.0 dBm 6.8 dBm
`
`I
`
`►
`
`\f^f y
`
`.■.MLrttfHllMlUfc-
`' ri TPWRA,,
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`l^tr1
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`
`START 18 700.0 Hz STOP 115,000. O Hz
`RBW 300 Hz VBW 1 KHz ST 2.2 SEC
`
`Figure 19. Uncorrelated Spectrum Output of the Punctual Channel Band-Pass
`Filter
`
`The side lobes appearing at the output of the band-pass filter during
`
`correlation are representative of the despread DPSK modulated carrier.
`
`Moreover, in the correlated case, the spectral distance that occurs between the
`
`center frequency of the main lobe and the side lobes is just about 1.5 times the
`
`data rate (Rb).
`
`22
`
`Petitioner's Exhibit 1018
`Page 031
`
`

`

`REF 7.5 dBm MARKER 70 500.0 Hz
`5 dB/DIV RANGE 10. 0 dBm 2. 65 dBm
`
`CENTER 76 200.O Hz
`RBW 300 Hz VBW 1 KHz
`
`SPAN 20.000. O Hz
`ST . 6 SEC
`
`Figure 20. Correlated Spectrum Output of the Punctual Channel Band-Pass
`Filter
`
`F. SYNCHRONIZATION
`
`All direct sequence spread spectrum receivers must be synchronized to
`
`the incoming PN sequence in order to achieve despreading. The
`
`synchronization circuit consists of a loop that monitors the error and adjusts the
`
`desired signal in such a way so that the error goes to zero. Tracking is initiated
`
`after the acquisition circuit has brought the phase difference between the
`
`T
`incoming and the local PN signals to within ± -f- seconds. The primary concern
`
`in an operational spread spectrum system is to ensure that the demodulator can
`
`despread the incoming spread spectrum signal to a narrow-band modulated
`
`signal from which the original transmitted data may be demodulated.
`
`23
`
`Petitioner's Exhibit 1018
`Page 032
`
`

`

`To achieve this, a demodulator design must possess two critical features.
`
`First, the same local PN sequence must be used in the despreading process as
`
`was used to originally spread the data. Second, the phase of the local PN
`
`sequence must be controlled and compensated for differences between it and
`
`the PN sequence imbedded within the incoming signal. This design uses a
`
`means of tracking referred to as a tau-dither loop [Ref. 1,3,4]. This tracking loop
`
`is a delay-locked loop with only a single branch as shown in Figure 21. A tau-
`
`dither loop is similar to the delay-lock loop, but it uses only one correlator branch
`
`as opposed to two branches for the delay-lock loop. The correlation with early
`
`and late versions of the PN signal is achieved by dithering back and forth
`
`between these early and late signals. An advantage of tau-dither loop is that it
`
`eliminates the problem of matching the characteristics of the two correlator
`
`branches.
`
`Received
`Signal
`
`X
`
`* BPF
`
`Envelope
`
`Detector
`
`g'Ct)
`
`Loop
`
`Filter
`
`+ KEJ 9"(t)
`Kxt
`
`9©
`
`Local PN
`
`Generator
`
`VCO
`
`Figure 21. The Tau-Dither Loop [Ref. 1,3,4].
`
`24
`
`Petitioner's Exhibit 1018
`Page 033
`
`

`

`Unmatched branches can degrade performance. However, the signal power in
`
`the tau-dither loop is 3 dB smaller than that in the delay-lock loop and,
`
`accordingly, the tracking jitter is larger. The control or gating waveforms (g(t),
`
`g'(t) and g"(t) which are shown in Figure 22) are used to generate both arms of
`
`the delay-lock loop (DLL) through one branch [Ref.4]. Due to its simplicity, the
`
`tau-dither loop is often used instead of the DLL. It has a signal channel which is
`
`switched between early and late correlation by switching signal g'(t). The signal
`
`g'(t) is a square wave voltage which takes on values ±1V. If g'(t)= -1V, then
`
`g(t)= 1V and g"(t)=0V. In this first case, the half bit early PN sequence is
`
`selected by the controlling gates and the half bit late PN sequence is blocked.
`
`On the other hand, if g'(t)=1V, then g(t)=0V and g"(t)=1V. In the second case,
`
`conversely, the resultant signal is the late PN sequence. The signal g'(t) is also
`
`used to multiply the envelope detector output. This multiplication provides the
`
`sign inversion necessary to generate the correlation curve from early and late
`
`signals. A representation of an ideal correlation signal at the input of the loop
`
`filter is shown in Figure 23.
`
`When a frequency difference exists, the punctual PN sequence will
`
`attempt to drift (early or late) out of correlation