Petition for Inter Partes Review of U.S. Patent No. 7,494,846
`Claims 1-16
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`DOCKET NO: 72484-0008US3
`Filed on behalf of Samsung Electronics Co., Ltd.
`By: Taeg Sang Cho, Reg. No. 69,618
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`Yung-Hoon Ha, Reg. No. 56,368
`Cosmin Maier, Reg. No. 75,387
`Desmarais LLP
`230 Park Ave
`New York, NY 10169
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
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`TRENCHANT BLADE TECHNOLOGIES, LLC.
`Patent Owner
`
`__________________
`
`
`Case IPR2021-00258
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`__________________
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`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,494,846
`CHALLENGING CLAIMS 1-16
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,494,846
`Claims 1-16
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`TABLE OF CONTENTS
`Introduction ...................................................................................................... 1 
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`I. 
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`II.  Mandatory Notices ........................................................................................... 1 
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`A. 
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`B. 
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`C. 
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`D. 
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`Real Parties-in-Interest .......................................................................... 1 
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`Related Matters ...................................................................................... 1 
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`Counsel .................................................................................................. 1 
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`Service Information (37 C.F.R. § 42.8(b)(4)) ....................................... 2 
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`III. 
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`Fees .................................................................................................................. 3 
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`IV.  Grounds for Standing ....................................................................................... 3 
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`V. 
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`Identification of Challenge and Relief Requested ........................................... 3 
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`A. 
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`B. 
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`Identification of Prior Art ...................................................................... 3 
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`Statutory Grounds of Unpatentability ................................................... 4 
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`VI.  Overview of the ’846 Patent ............................................................................ 4 
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`A.  Alleged Problem In The Art .................................................................. 6 
`
`B. 
`
`C. 
`
`Purported Invention of the ’846 Patent ................................................. 6 
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`Prosecution History of the ’846 Patent ................................................. 9 
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`VII.  Overview of the Primary Prior Art Reference ............................................... 10 
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`A.  Overview of Matsuo ............................................................................ 10 
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`VIII.  Level of Ordinary Skill in the Art ................................................................. 14 
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`IX.  Claim Construction ........................................................................................ 15 
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`X. 
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`Specific Grounds for Challenge .................................................................... 15 
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`A.  Ground I: Matsuo Anticipates Claims 1, 3, 8, 9 and 11. ..................... 16 
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`U.S. Patent No. 7,494,846
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`Claim 1 ...................................................................................... 16 
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`1. 
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`2. 
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`3. 
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`4. 
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`5. 
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`Claim 3 ...................................................................................... 35 
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`Claim 8 ...................................................................................... 36 
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`Claim 9 ...................................................................................... 37 
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`Claim 11 .................................................................................... 38 
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`B. 
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`Ground II: Matsuo in combination with Farnworth renders
`obvious Claims 4-7. ............................................................................. 39 
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`1. 
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`2. 
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`3. 
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`Claim 7 ...................................................................................... 39 
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`Claims 4 and 5 ........................................................................... 42 
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`Claims 4 and 6 ........................................................................... 47 
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`C. 
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`Ground III: Matsuo in combination with Beffa renders obvious
`Claim 10. ............................................................................................. 50 
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`1. 
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`Claim 10 .................................................................................... 50 
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`D.  Ground IV: Matsuo in combination with Trezza renders obvious
`Claims 2, 12-14 and 16. ...................................................................... 53 
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`1. 
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`2. 
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`3. 
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`4. 
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`5. 
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`Claim 2 ...................................................................................... 53 
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`Claim 12 .................................................................................... 61 
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`Claim 13 .................................................................................... 74 
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`Claim 14 .................................................................................... 76 
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`Claim 16 .................................................................................... 78 
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`E. 
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`Ground V: Matsuo in combination with Leedy renders obvious
`Claim 8. ............................................................................................... 80 
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`1. 
`
`Claim 8 ...................................................................................... 80 
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`Petition for Inter Partes Review
`U.S. Patent No. 7,494,846
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`F. 
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`Ground VI: Matsuo in combination with Suh renders obvious
`Claims 4 and 5. .................................................................................... 82 
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`1. 
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`Claims 4 and 5 ........................................................................... 82 
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`G.  Ground VII: Matsuo in combination with Trezza and Beffa
`renders obvious Claim 15. ................................................................... 84 
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`1. 
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`Claim 15 .................................................................................... 84 
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`XI.  Discretionary Factors ..................................................................................... 85 
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`A. 
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`B. 
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`35 U.S.C. § 325(d)............................................................................... 85 
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`35 U.S.C. § 314(a) ............................................................................... 86 
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`XII.  Conclusion ..................................................................................................... 86 
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`Petition for Inter Partes Review
`U.S. Patent No. 7,494,846
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`PETITIONER’S EXHIBIT LIST
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`Petitioner
`Exhibit No.
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`1012
`1013
`1014
`1015
`1016
`1017
`1018
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`DESCRIPTION
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`U.S. Patent No. 7,494,846
`Declaration of Dr. Vivek Subramanian
`U.S. Patent Publication No. 2003/0062612 (“Matsuo”)
`U.S. Patent No. 6,841,883 (“Farnworth”)
`U.S. Patent No. 5,915,231 (“Beffa”)
`U.S. Patent Publication No. 2006/0278992 (“Trezza”)
`U.S. Patent Publication No. 2005/0023656 (“Leedy”)
`U.S. Patent Publication No. 2007/0218678 (“Suh”)
`U.S. Patent No. 7,691,748 (“Han”)
`U.S. Patent Publication No. 2002/0185337 (“Miura”)
`U.S. Patent Publication No. 2004/0232559 (“Adelmann”)
`File History of U.S. Patent No. 7,494,846
`U.S. Patent Publication No. 2005/0054140 (“Kim”)
`U.S. Patent Publication No. 2004/0016939 (“Akiba”)
`U.S. Patent No. 6,784,023 (“Ball”)
`U.S. Patent Publication No. 2006/0012012 (“Wang”)
`U.S. Patent Publication No. 2001/0014037 (“Kim”)
`U.S. Patent Publication No. 2005/0263605 (“Muranaka”)
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`iv
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`Petition for Inter Partes Review
`U.S. Patent No. 7,494,846
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`I.
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`Introduction
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`
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`Petitioner Samsung Electronics Co., Ltd. (“Petitioner”) requests inter partes
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`review of claims 1-16 (the “challenged claims”) of U.S. Patent No. 7,494,846 (the
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`“’846 Patent”).
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`II. Mandatory Notices
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`A. Real Parties-in-Interest
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`Petitioner identifies itself and Samsung Semiconductor, Inc. as real
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`parties-in-interest (“RPIs”).
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`B. Related Matters
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`On November 20, 2020, the RPIs filed a declaratory judgment action of
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`noninfringement of U.S. Patent Nos. 6,720,619, 7,056,821, and 7,494,846. Samsung
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`Electronics Co. Ltd. v. Trenchant Blade Technologies LLC, Case No. 5:20-cv-08205
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`(N.D.Cal) (“Trenchant Litigation”). Petitioner has filed petitions for inter partes
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`review against U.S. Patent Nos. 6,720,619 and 7,056,821.
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`C. Counsel
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`Petitioner is filing a power of attorney appointing the practitioners associated
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`with Customer Number 132,593. Petitioner designates the following lead and back-
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`up counsel:
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`1
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`Petition for Inter Partes Review
`U.S. Patent No. 7,494,846
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`
`Lead Counsel
`Taeg Sang Cho (Reg. No. 69,618)
`Desmarais LLP
`230 Park Ave
`New York, NY 10169
`Telephone: (212) 351-3400
`Facsimile: (212) 351-3401
`Email: tcho@desmaraisllp.com
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`
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`First Back-up Counsel
`Yung-Hoon Ha (Reg. No. 56,368)
`Desmarais LLP
`230 Park Ave
`New York, NY 10169
`Telephone: (212) 351-3400
`Facsimile: (212) 351-3401
`Email: yha@desmaraisllp.com
`Back-up Counsel
`Cosmin Maier (Reg. No. 75,387)
`Desmarais LLP
`230 Park Ave
`New York, NY 10169
`Telephone: (212) 351-3400
`Facsimile: (212) 351-3401
`Email: cmaier@desmaraisllp.com
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`
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))
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`Post and hand delivery: Desmarais LLP
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`Telephone:
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`Email:
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`230 Park Ave, New York, NY 10169
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`212-351-3400
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`samsung-trenchant-ipr@desmaraisllp.com
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`Please address all correspondence to counsel identified above. Petitioner
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`consents to electronic service by email at:
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`samsung-trenchant-ipr@desmaraisllp.com.
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`2
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`Petition for Inter Partes Review
`U.S. Patent No. 7,494,846
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`III. Fees
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`Petitioner concurrently submits required fees for this Petition. The Board is
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`authorized to charge Desmarais LLP’s deposit account, No. 50-6822, for any fee
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`deficiency.
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`IV. Grounds for Standing
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`Petitioner certifies that the ’846 Patent is available for inter partes review and
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`that Petitioner is not estopped or barred from requesting inter partes review.
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`V.
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`Identification of Challenge and Relief Requested
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`Petitioner requests inter partes review and cancellation of claims 1-16 of the
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`’846 Patent.
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`A.
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`Identification of Prior Art
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`The following references are pertinent to the grounds of unpatentability
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`explained below:
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`1. U.S. Patent Publication No. 2003/0062612 (“Matsuo” (Ex. 1003)),
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`which published on April 3, 2003, is prior art under 35 U.S.C. § 102(b).
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`2.
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`U.S. Patent No. 6,841,883 (“Farnworth” (Ex. 1004)), which issued on
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`January 11, 2005, is prior art under 35 U.S.C. § 102(b).
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`3.
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`U.S. Patent No. 5,915,231 (“Beffa” (Ex. 1005)), which issued on June
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`22, 1999, is prior art under 35 U.S.C. § 102(b).
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`U.S. Patent No. 7,494,846
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`4.
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`U.S. Patent Publication No. 2006/0278992 (“Trezza” (Ex. 1006)),
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`which was filed on January 10, 2006, published on December 14, 2006, and claims
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`priority to U.S. Provisional Application No. 60/690,759 filed on June 14, 2005, is
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`prior art under 35 U.S.C. §§ 102(a),(e).
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`5.
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`U.S. Patent Publication No. 2005/0023656 (“Leedy” (Ex. 1007)),
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`which published on February 3, 2005, is prior art under 35 U.S.C. § 102(b).
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`6.
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`U.S. Patent Publication No. 2007/0218678 (“Suh” (Ex. 1008)), which
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`was filed on December 29, 2006 and published on September 20, 2007, is prior art
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`under 35 U.S.C. § 102(e).
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`B.
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`Statutory Grounds of Unpatentability
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`Petitioner requests cancellation of claims 1-16 of the ’846 Patent under 35
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`U.S.C. §§ 102 and 103. This Petition demonstrates that there is a reasonable
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`likelihood that Petitioner will prevail with respect to cancellation of at least one
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`challenged claim. See 35 U.S.C. § 314(a).
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`VI. Overview of the ’846 Patent
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`It has long been known that one way to increase the density of components in
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`a semiconductor device is to stack multiple semiconductor chips or “dies” on top of
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`each other vertically. See, e.g., Ex. 1001, 1:35-37 (“three-dimensional integrated
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`circuit (3DIC) and stacked dies are commonly used.”). Admitted prior art Figure 1
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`U.S. Patent No. 7,494,846
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`of the ’846 Patent below shows two identical dies1 (10 and 12, in gray below)
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`vertically stacked and aligned with each other. See id., Figure 1. Ex. 1002, ¶¶ 34-
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`35.
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`As shown above, “[t]hrough-silicon vias (TSV)” (in light green) provide
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`electrically conductive paths that pass through the dies (in gray); and (2) bond pads
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`(in dark yellow) are connected to the TSVs, providing electrical connection between
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`the stacked dies. Ex. 1001, 1:37-45 (“TSVs 4 penetrate through semiconductor
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`substrate 2, and are connected to the integrated circuits in the respective dies and
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`1 All bold/italics/color emphases and annotations are added unless noted
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`otherwise.
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`bonding pads 6. Dies 10 and 12 are bonded through bonding pads 6.”). Moreover,
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`the dies are vertically aligned with each other. In other words, the ’846 Patent admits
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`that vertically aligned stacked die structures with vertically aligned bond pads and
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`TSVs were already known in the prior art. See, e.g., Ex. 1001, Figure 1. Ex. 1002,
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`¶ 36.
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`A. Alleged Problem In The Art
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`The ’846 Patent describes using TSVs to stack multiple memory dies. Ex.
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`1001, 1:48-50. The memory dies preferably “have exactly the same design, and can
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`be fabricated using a same set of masks” to reduce fabrication complexity and cost.
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`Id., 1:51-56. But each identical die “need[s] to have [a] unique addresses in order to
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`distinguish [the dies] from each other.” Id., 1:57-67. The ’846 patent explains that
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`the prior art taught using different “redistribution lines” and “interposers” to
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`distinguish between the different dies of a stacked memory die structure. Id.
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`According to the ’846 Patent, however, those methods for distinguishing between
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`dies in a stacked memory die structure are costly. Id. Ex. 1002, ¶ 37.
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`B.
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`Purported Invention of the ’846 Patent
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`The ’846 Patent purports to solve this problem by including, in each identical
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`memory die, a programmable identification circuit (shown below in blue) that
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`uniquely identifies the memory die. The identification data stored in the
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`identification circuit serves as the “unique address” of each die, allowing one die
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`to be distinguished from the other dies. Ex. 1001, 4:55-57 (“The programmable
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`elements in the ID circuit of each die are programmed differently from … other
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`dies.”), 4:67-5:2 (“act[] as a unique address of the corresponding die.”); see also id.,
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`2:8-21, 4:37-5:15. Using identification circuits to distinguish between dies
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`purportedly lowers the manufacturing cost relative to redistribution lines and/or
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`interposers. Id., 3:29-33. Ex. 1002, ¶ 38.
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`Figure 5 below shows an embodiment with four dies stacked on top of each
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`other. See Ex. 1001, 5:42 (“Referring to FIG. 5, dies 1, 2, 3 and 4 are stacked…”).
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`As shown, “[e]ach of dies 1, 2, 3 and 4 includes a substrate, on which integrated
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`circuits (not shown) may be formed.” Id., 4:8-9. Identification (ID) circuits are
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`shown in the left, and input/output (IO) paths (discussed further below) are shown
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`on the right. Ex. 1002, ¶¶ 39-40.
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`As shown on the left, the identification circuits are connected to through-
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`silicon vias (“TSVs”) (shown in green) that provide electrical connections to
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`vertically adjacent dies. See Ex. 1001, 4:37-5:15, Figure 5. Connected to the TSVs
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`are “chip-select pads P1, P2, P3 and P4” that are vertically aligned with “chip-select
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`pads P1_B, P2_B, P3_B and P4_B” “[o]n the opposite side of the die.” Id., 4:37-
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`44. Each TSV of one die electrically connects to a corresponding TSV of an
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`adjacent die through the corresponding chip-select pads. Id., 4:37-5:15, Figure 5.
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`The chip-select pads are used to provide a chip select signal that activates (enables)
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`for operation one of the dies in the stack. Id., 5:54-64. Ex. 1002, ¶¶ 41-42.
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`As shown on the right, each die further includes different TSVs (shown in
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`light green) for I/O paths and a “plurality of input/output (I/O) pads PIO1 through
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`PIOn [that] is connected to the integrated circuits.” Ex. 1001, 4:9-11, 4:18-21. The
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`I/O pads are “connected to a respective I/O pin PIO1_B through PIOn_B, which
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`are on the opposite side of the die.” Id., 4:15-19. The I/O pads and the I/O pins
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`are vertically aligned with each other. Id., 4:19-21. Ex. 1002, ¶ 43.
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`As explained in the Grounds below, the method for forming a stack of
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`vertically aligned memory dies having aligned TSVs for I/O and aligned TSVs for
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`a chip select signal was well-known in the prior art. Ex. 1002, ¶ 38.
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`C.
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`Prosecution History of the ’846 Patent
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`The ’846 Patent was filed on March 9, 2007 and issued on February 24, 2009
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`after receiving a first-action allowance. Ex. 1001, Cover; Ex. 1012 [File History],
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`39-44 (Notice of Allowance dated August 8, 2008). The Examiner stated that
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`although a prior art reference, Muranaka (Ex. 1018), discloses a multi-chip module
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`with identification circuits, it “does not disclose or suggest the bonding as recited
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`wherein each of the I/O pads2 in the first die is connected to an I/O path in the
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`2 The Examiner appears to have read “I/O conductive paths” to be synonymous
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`with “I/O pads.” But claim 1 more broadly recites that “I/O conductive paths
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`comprises through-silicon vias” and claim 12 similarly recites “I/O conductive
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`second die as recited in claim 1 or vertical alignment of I/O pads as recited in claim
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`12.” Id., 43. Ex. 1002, ¶¶ 44-48.
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`VII. Overview of the Primary Prior Art Reference
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`The alleged invention of the ’846 patent—including the supposedly missing
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`bonding limitations—was well-known in the art as of the March 9, 2007 priority
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`date of the ’846 Patent. See Ex. 1002, ¶¶ 63-208.
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`A. Overview of Matsuo
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`Matsuo teaches identical vertically stacked memory chips. Ex. 1003, [0005]
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`(“a plurality of [memory] chips stacked in a vertical direction.”), [0028]
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`(“integrated circuits C1 to C4 have substantially the same structure and conform
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`to the same specification.”). Ex. 1002, ¶ 50.
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`Matsuo’s Figure 1 below shows four identical chips C1 to C4 stacked
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`together. Ex. 1003, [0027]-[0028] (“a plurality of semiconductor integrated circuit
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`chips (LSI chips) C1 to C4 [are] stacked together [and] have substantially the same
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`structure.”). The left portion of Figure 1 shows through plugs (PG) that are used
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`for input/output (IO) circuits. The right portion of Figure 1 shows through plugs
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`paths comprises a first input/output (I/O) pad and a second I/O pad.” Ex. 1002,
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`¶ 47.
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`(PG) that are used for connections to identification circuits (not shown in Figure
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`1) in each chip. Ex. 1002, ¶ 51.
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`As shown above, memory chips C1, C2, C3, and C4 include (1) “terminals
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`TM [that] comprise through plugs PG [in light green and green] formed of
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`conductive material and penetrating the chip” (Ex. 1003, [0029]); and (2) “pads
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`[that] are formed on the through plugs” (not shown in Figure 1). Id., [0042]. The
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`through plugs PG are vertically aligned and electrically connected using bumps (in
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`orange and pink). Id., [0029] (“The corresponding terminals of the chips [that
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`comprise through plugs PG] are connected together by bumps BP.”), [0043],
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`[0030]. Matsuo thus teaches the features the Examiner considered to be missing
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`from the prior art. Ex. 1002, ¶ 52.
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`U.S. Patent No. 7,494,846
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`Moreover, the left side of Figure 1 shows “power terminal and terminals to
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`and from which control and data signals are input and output.” Ex. 1003, [0029];
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`[0028] (“terminals to which a clock signal and various control signals are input
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`[and] are connected together.”). Ex. 1002, ¶ 58.
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`The right side of Figure 1 shows “select terminal[s]” that “specif[y] a chip
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`address (CA0, CA1),” which are “used for chip selection to activate (enable) a
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`desired chip.” Ex. 1003, [0029]-[0030], [0036]-[0037]; cf. Ex. 1001, 4:37-5:15. The
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`select terminals are connected to a “holding circuit” (in the identification circuit)
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`that uniquely identifies a particular memory die. See Ex. 1003, [0030] (“[E]ach
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`chip has a holding circuit (not shown) that electrically holds (stores) identification
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`data used to distinguish this chip from the others.”). Ex. 1002, ¶ 53.
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`The identification circuits further includes logic circuits (shown below in
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`Figure 3) that identifies the enabled die within the stack. When a memory chip
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`receives the “chip address (CA0, CA1)” over the select terminals, the select
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`terminals provide the received “chip address (CA0, CA1)” to the logic circuits3
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`3 The ’846 Patent similarly describes a decoding circuit that determines the
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`“identification of the [enabled] die.” Ex. 1001, 4:49-54 (“The decoding circuit
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`includes an AND gate, … and an output of the AND gate is connected to a chip-
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`(e.g., latch circuits 12a, 12b, EXNOR circuits 14a, 14b, and a NAND circuit 15).
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`The logic circuits determine whether the chip address (CA0, CA1) identifies the
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`memory circuit in its chip for activation. Ex. 1003, [0035]-[0037]. Ex. 1002, ¶ 55.
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`Matsuo shows additional logic circuits in Figure 7 below (called
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`identification
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`information setting circuit)
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`in
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`the
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`identification circuit.
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`Specifically, Matsuo teaches a “setting terminal [that] is … used to set
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`identification information in a holding circuit.” Ex. 1003, [0029]; id., Abstract,
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`Claims 1, 9. Ex. 1002, ¶ 54.
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`enable (CE) line for the enablement and the identification of the respective die.”).
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`Ex. 1002, ¶ 56.
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`U.S. Patent No. 7,494,846
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`VIII. Level of Ordinary Skill in the Art
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`The following combinations of education and experience would have
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`qualified someone as a person of ordinary skill in the art (“POSITA”) of the ’846
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`Patent as of its filing date in March 2007:
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`-
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`-
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`a Master’s degree in electrical engineering, physics, or materials
`science; or
`a Bachelor’s degree in electrical engineering, physics, or
`materials science, with two years of practical experience with
`semiconductor/memory research and design.
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`Further, additional education could make up for less practical experience, and vice
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`versa. Ex. 1002, ¶ 59.
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`IX. Claim Construction
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`The claims should be construed “in accordance with the ordinary and
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`customary meaning of such claim as understood by one of ordinary skill in the art
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`and the prosecution history pertaining to the patent.” 37 C.F.R. § 42.100(b); see also
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`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). Here, challenged
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`claims are unpatentable under their ordinary and customary meanings. Thus, the
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`Board need not expressly construe any claim term at this stage.4
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`X.
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`Specific Grounds for Challenge
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`This petition presents the following Grounds of invalidity of challenged
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`claims:
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`4 Petitioner reserves all rights to raise claim construction arguments and other
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`arguments in any parallel or future litigation concerning the ’846 Patent. For
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`example, comparing the claims to the accused products in the litigation may raise
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`controversies that require construction of certain claim terms.
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`Petition for Inter Partes Review
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`Grounds Claims
`I
`1, 3, 8, 9, 11
`II
`4-7
`III
`10
`IV
`2, 12-14, 16
`V
`8
`VI
`4-5
`VII
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`Statutory Ground Prior Art Reference(s)
`§ 102
`Matsuo
`§ 103
`Matsuo, Farnworth
`§ 103
`Matsuo, Beffa
`§ 103
`Matsuo, Trezza
`§ 103
`Matsuo, Leedy
`§ 103
`Matsuo, Suh
`§ 103
`Matsuo, Trezza, Beffa
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`The sections below, as supported by the Declaration of Dr. Subramanian,
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`demonstrate how the challenged claims are unpatentable. See 37 C.F.R.
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`42.104(b)(4)-(5).
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`A. Ground I: Matsuo Anticipates Claims 1, 3, 8, 9 and 11.
`1.
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`Claim 1
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`[1Pre] A method of forming a semiconductor
`structure, the method comprising:
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`To the extent the preamble is limiting, Matsuo discloses the preamble. For
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`example, Figures 4 and 6 show flow charts describing different “example[s] of a
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`method of manufacturing a stacked type semiconductor device.” Ex. 1003, [0014],
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`[0018], [0020]. Ex. 1002, ¶¶ 65-66.
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`[1A] forming a first semiconductor die and a second
`semiconductor die identical to the first semiconductor
`die,
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`Matsuo discloses this limitation. Specifically, Matsuo discloses forming chip
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`C1 (the claimed “first semiconductor die”) and chip C2 (the claimed “second
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`semiconductor die”) that is identical to chip C1. Ex. 1002, ¶ 67.
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`Figures 4 and 6 illustrate a process of forming a plurality of identical
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`semiconductor dies. Ex. 1003, [0018], [0020], [0049], [0050]. For example, in
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`Figure 4, “a circuit including semiconductor active elements and wires as well as
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`through plugs are formed in a semiconductor wafer … [and] pads are formed on the
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`through plugs (S11).” Id., [0042]. Then, “bumps are formed on the previously
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`formed pads (S13).” Id., [0043]. Then, “the wafer is polished … [and] further
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`diced into chips (S15). Subsequently, the chips5 are selected (S16) and then stacked
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`and assembled together (S17).” Id., [0044]. That process forms a plurality of
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`identical chips (including chips C1 and C2) that are stacked together. Accordingly,
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`Matsuo teaches forming identical first and second semiconductor dies. Ex. 1002,
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`¶¶ 68-70.
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`5 The terms “chip” and “die” are often used interchangeably. See Ex. 1016, [0002]
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`(“referred to in the art as a chip or die”); see also Ex. 1003, [0042] (“defective
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`chips, if any are detected by pre-die-sorting.”). Ex. 1002, ¶ 69.
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`Dies C1 to C4 in Matsuo are “identical” in the context of the challenged
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`claims. First, the ’846 Patent states that the claimed first and second
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`semiconductor dies are identical because they “have exactly the same design, and
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`can be fabricated using a same set of masks.” Ex. 1001, 1:55-56. Just like the ’846
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`patent, the semiconductor dies C1 and C2 in Matsuo also have exactly the same
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`design and can be fabricated using the same set of masks. Specifically, Matsuo
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`teaches that those dies have “substantially the same structure,” “substantially the
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`same shape, substantially the same number of terminals, substantially the same
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`circuit configuration, and the like.” Ex. 1003, [0028]. Ex. 1002, ¶¶ 71-73.
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`Second, the ’846 Patent recognizes that dies are “identical” even if the dies
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`have some differences. Ex. 1001, 6:23-27 (“[T]he only difference between die 4
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`and dies 1, 2 and 3 are the thickness of the substrates (hence the lengths of TSVs),
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`and programming states of the programmable elements. Accordingly die 4 is still
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`considered to be identical to dies 1, 2 and 3.”). As such, a POSITA would have
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`understood Matsuo’s “substantially the same” chips to be “identical” in the context
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`of the ’846 Patent. Ex. 1002, ¶ 73.
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` [1B] wherein each of the first and the second
`semiconductor dies comprises: an
`identification
`circuit; and
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`Matsuo discloses this limitation. Each die in Matsuo (including chips C1 and
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`C2) includes at least “a holding circuit … that electrically holds (stores)
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`identification data used to distinguish [one] chip from the others.” Ex. 1003, [0030],
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`[0034]; [0035] (“A holding circuit 11 in each of the chips C1 to C4 holds the chip’s
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`own identification data.”). Ex. 1002, ¶¶ 74-77.
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`Matsuo’s holding circuit 11 corresponds to the programmable elements in
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`the identification circuit of the ’846 Patent. Ex. 1001, 4:22-32, 4:55-57 (explaining
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`that the identification circuit includes programmable elements that “are
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`programmed differently from the programmable elements in the ID circuits of other
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`dies.”). Ex. 1002, ¶ 77.
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`Matsuo also teaches that the identification circuits includes logic circuits6
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`(shown above in Figure 3 and below in Figure 7). For example, as shown above in
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`Figure 3, when a memory chip receives the “chip address (CA0, CA1)” over the
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`select terminals, it is provided to the logic circuits7 (e.g., latch circuits 12a, 12b,
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`EXNOR circuits 14a, 14b, and a NAND circuit 15). The logic circuits then
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`determine whether the chip address (CA0, CA1) is identifying the memory circuit
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`in its chip based on the identification data in the holding circuit. Ex. 1003, [0035]-
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`[0037]. Ex. 1002, ¶ 78.
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`Additional logic circuit called “identification information setting circuit”
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`is shown in Figure 7. Ex. 1003, [0052]. Matsuo uses a “setting terminal …to set
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`6 This is again just like the ’846 patent which teaches that the programmable
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`elements may be connected to decoding circuits (i.e., logic circuit). Ex. 1001,
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`4:47-49, 4:29-32. Ex. 1002, ¶¶ 75-76.
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`7 The ’846 Patent similarly describes a decoding circuit that determines the
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`“identification of the [enabled] die.” Ex. 1001, 4:49-54 (“The decoding circuit …
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`connected to a chip-enable (CE) line for the enablement and the identification of
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`the respective die.”). Ex. 1002, ¶ 75.
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`identification information in a holding circuit,” and it does so using the logic
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`circuit in Figure 7. Id., [0029], [0030], [0052]; id., Abstract, Claims 1, 9. In other
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`words, the logic circuit in Figure 7 programs the identification data in the holding
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`circuit. Id., [0030], [0052]. Ex. 1002, ¶ 79.
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`Therefore, Matsuo teaches that each of C1 and C2 (the claimed “first and
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`the second semiconductor dies”) includes an identification circuit including at
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`least a holding circuit 11 (the programmable elements of the claimed
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`“identification circuit”) and logic circuits (other blue colored circuit components
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`shown in Figures 3 and 7 above). Ex. 1002, ¶ 80.
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`[1C] wherein each of the first and the second
`semiconductor dies comprises: … a plurality of
`input/output (I/O) conductive paths connected to
`memory circuits in the respective first and second
`semiconductor dies, wherein the plurality of I/O
`conductive paths comprises through-silicon vias;
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`Matsuo discloses this limitation. Matsuo teaches that each of C1 and C2
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`comprises a plurality of through plugs PG (the claimed “through-silicon vias”).8
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`In particular, Matsuo teaches that each chip includes “terminals TM [that] comprise
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`through plugs PG formed of conductive material and penetrating the chip.” Ex.
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`1003, [0029]; [0006] (“[T]he chips are electrically connected together via, for
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`example, through plugs that penetrate the chips.”); [0042]. As was well-known in
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`the art, through plugs PG are formed vertically through the semiconductor substrate
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`and are often called through-silicon vias (TSVs). See, e.g., Ex. 1009, 1:38-48 (“A
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`8