(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0263605 A1
`(43) Pub. Date:
`Dec. 1, 2005
`Muranaka
`
`US 20050263605A1
`
`(54) METHOD FOR IDENTIFYING
`SEMCONDUCTOR INTEGRATED CIRCUIT
`DEVICE, METHOD FOR MANUFACTURING
`SEMCONDUCTOR INTEGRATED CIRCUIT
`DEVICE, SEMICONDUCTOR INTEGRATED
`CIRCUIT DEVICE AND SEMCONDUCTOR
`CHIP
`
`Related U.S. Application Data
`(62) Division of application No. 10/433,161, filed on Oct.
`15, 2003, now Pat. No. 6,941,536, filed as 371 of
`international application No. PCT/JP01/07727, filed
`on Sep. 6, 2001.
`Foreign Application Priority Data
`
`(30)
`
`(75) Inventor: Masaya Muranaka, Akishima (JP)
`
`Dec. 1, 2000 (WO)............................ PCT/JPOO/O8500
`
`Correspondence Address:
`MILES & STOCKBRIDGE PC
`1751. PINNACLE DRIVE
`SUTE 500
`MCLEAN, VA 22102-3833 (US)
`
`(73) Assignees: Hitachi, Ltd.; Hitachi ULSI Systems
`Co., Ltd.
`(21) Appl. No.:
`11/194,487
`(22) Filed:
`Aug. 2, 2005
`
`
`
`Publication Classification
`
`(51) Int. Cl." .............................................. G06K 19/06
`(52) U.S. Cl. .............................................................. 235/492
`
`ABSTRACT
`(57)
`In the manufacturing process of a Semiconductor integrated
`circuit device, a plurality of identification elements having
`the same arrangement are formed and the relation of mag
`nitude in a physical amount corresponding to variations in
`the process of the plurality of identification elements is
`employed as identification information unique to the Semi
`conductor integrated circuit device.
`
`SAMSUNG EXHIBIT 1018
`Samsung v. Trenchant
`Case IPR2021-00258
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 1 of 74
`
`US 2005/0263605 A1
`
`FIG. 1
`
`NV4
`
`FIG. 2
`
`
`
`EGISTER
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 2 of 74
`
`US 2005/0263605 A1
`
`FG. 3
`
`FIG. 4
`
`
`
`VLT2 - VLT1 X VLT4 X VLT3
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 3 of 74
`
`US 2005/0263605 A1
`
`FIG. 5
`
`A
`
`A2
`
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`
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`c EOPOEXE OE Ole O
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`
`B3
`
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`
`D4
`
`NV3
`
`B4
`
`NV4
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 4 of 74
`
`US 2005/0263605 A1
`
`FIG. 6
`
`- AMP1 AMP2
`
`Pass
`NV2
`INV3
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`
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`
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`
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`D
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`
`NV1
`NV1
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`NV1
`
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`NV2
`
`NV4
`INV4
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 5 of 74
`
`US 2005/0263605 A1
`
`FIG. 7
`
`AMP1 AMP2
`
`Y2
`
`X3
`
`Y2 Y4 X2 X4
`Y1 Y3 X1 X3
`
`
`
`CLK
`RES
`
`Binary Counter
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 6 of 74
`
`US 2005/0263605 A1
`
`FIG. 8
`
`
`
`sk
`
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`
`FIG. 9
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 7 of 74
`
`US 2005/0263605 A1
`
`F.G. 10
`
`
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 8 of 74
`
`US 2005/0263605 A1
`
`F.G. 12
`
`PP
`
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`
`
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 9 of 74
`
`US 2005/0263605 A1
`
`FIG. 14
`
`
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 10 of 74
`
`US 2005/0263605 A1
`
`FIG. 17
`
`
`
`Y4 X2 X4
`Y3 X1 X3
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 11 of 74
`
`US 2005/0263605 A1
`
`FIG. 18
`
`(A)
`
`RES
`
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`
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 12 of 74
`FIG. 19
`
`US 2005/0263605 A1
`
`LOGICALTHRESHOLD
`VALUE DETERMINATION UNIT
`
`
`
`
`
`PON
`
`LOGICAL THRESHOD
`VALUE DETERMINAEON UNT
`VSS
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 13 of 74
`
`US 2005/0263605 A1
`
`
`
`
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 14 of 74
`
`US 2005/0263605 A1
`
`LSI PINS
`
`
`
`IDENTIFICATION NUMBER
`
`SN|d IST
`
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`Patent Application Publication Dec. 1, 2005 Sheet 15 of 74
`
`US 2005/0263605 A1
`
`FIG. 22
`BASIC REPETITION UNTS
`ELEMENT NUMBER
`YO/XO/ GATE TERMINAL NAME
`
`A XOf
`
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`
`SOURCE/ORAN
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`
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 16 of 74
`FIG. 23
`
`US 2005/0263605 A1
`
`
`
`X-DECODER
`
`CMOS LOGICALTHRESHOLD
`VALUE DETECTOR CIRCUIT
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 17 of 74
`
`US 2005/0263605 A1
`
`INPUTIOUTPUT CIRCUIT
`
`COLUMN DECODER
`
`
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 18 of 74
`
`US 2005/0263605 A1
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`Patent Application Publication
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`Dec. 1, 2005 Sheet 19 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 20 0f 74
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`Patent Application Publication Dec. 1
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`Patent Application Publication Dec. 1, 2005 Sheet 25 of 74
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`Patent Application Publication Dec. 1, 2005
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`Patent Application Publication Dec. 1, 2005 Sheet 28 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 30 of 74
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`Patent Application Publication Dec. 1, 2005 Sheet 31 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 32 of 74
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`US 2005/0263605 A1
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`FIG. 39
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`Patent Application Publication Dec. 1, 2005 Sheet 33 of 74
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`US 2005/0263605 A1
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`ent Application Publication Dec. 1, 2005 Sheet 34 of 74
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`Patent Application Publication Dec. 1, 2005 Sheet 35 of 74
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`US 2005/0263605 A1
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`FG. 43
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`Patent Application Publication Dec. 1, 2005 Sheet 36 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 37 of 74
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`Patent Application Publication Dec. 1, 2005 Sheet 38 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 39 of 74
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`US 2005/0263605 A1
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`FIG. 47
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`Patent Application Publication Dec. 1, 2005 Sheet 40 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 41 of 74
`
`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 42 of 74
`
`US 2005/0263605 A1
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`FIG 51
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 43 of 74
`
`US 2005/0263605 A1
`
`FIG. 53
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 44 of 74
`FIG. 55
`
`US 2005/0263605 A1
`
`OUTPUT DATA
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 45 of 74
`
`US 2005/0263605 A1
`
`F.G. 56
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`Patent Application Publication Dec. 1, 2005 Sheet 46 of 74
`
`US 2005/0263605 A1
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`Patent Application Publication Dec. 1
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1
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`Patent Application Publication Dec. 1
`
`9.
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 50 of 74
`
`US 2005/0263605 A1
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`O-IST
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`Patent Application Publication Dec. 1, 2005 Sheet 51 of 74
`
`US 2005/0263605 A1
`
`F.G. 62
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`Patent Application Publication
`
`Dec. 1, 2005 Sheet 52 of 74
`
`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 53 of 74
`
`US 2005/0263605 A1
`
`F.G. 65
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`MANAGEMENT NUMBER = 1
`
`
`
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`NUMBER OF REGISTRATIONS
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`
`DETERMINE
`MAXIMUMAND MINIMUM ELEMENT
`NUMBERS (6)
`
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`
`COMPARE DENTIFICATION .
`NUMBERS, AND COUNT
`NUMBER OF UNMATCH BITS (6)
`
`SELECT CLOSEST ONE AS
`MATCHING CANDIDATE (7)
`
`NCREMENT MANAGEMENT
`NUMBER BY ONE
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 54 of 74
`
`US 2005/0263605 A1
`
`FIG. 66
`
`CD
`10010010111010 - - -
`IDENTIFIED NUMBER
`
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`
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`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 55 of 74
`
`US 2005/0263605 A1
`
`F.G. 67
`
`FOUNDRY NAME
`PROCESS NAME
`SYNTHESIZING
`TOO. NAME
`REOURED
`IDENTIFICATION CAPABILITY
`USED SUPPLY
`VOLTAGE
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`TEMPERATURE
`
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`SIGNAL NAME
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`SOFT PINFORMATION
`
`

`

`Patent Application Publication Dec. 1, 2005 Sheet 56 of 74
`
`US 2005/0263605 A1
`
`FIG. 68
`
`TRUTH TABLE
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`RTL
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 57 of 74
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`US 2005/0263605 A1
`
`F.G. 69
`
`
`
`GENERAL
`NFORMATION
`DAABASE
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`s O
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`ICCARD
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`

`

`Patent Application Publication Dec. 1, 2005 Sheet 58 of 74
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`US 2005/0263605 A1
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`FIG. 70
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`PRE-PROCESS
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`

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`Patent Application Publication Dec. 1
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`Patent Application Publication Dec. 1, 2005 Sheet 61 of 74
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`Patent Application Publication Dec. 1, 2005 Sheet 65 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 66 of 74
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`Patent Application Publication Dec. 1, 2005 Sheet 67 of 74
`
`US 2005/0263605 A1
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`FIG. 79
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`

`Patent Application Publication Dec. 1, 2005 Sheet 68 of 74
`
`US 2005/0263605 A1
`
`BUIL-IN CIRCUITS
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`DENTIFICATION NUMBER
`GENERATOR CRCUT
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`

`Patent Application Publication Dec. 1, 2005 Sheet 69 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 70 of 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 71 0f 74
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`US 2005/0263605 A1
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`Patent Application Publication Dec. 1, 2005 Sheet 72 of 74
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`Patent Application Publication Dec. 1, 2005 Sheet 73 of 74
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`US 2005/0263605 A1
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`FIG. 85
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`Patent Application Publication Dec. 1, 2005 Sheet 74 of 74
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`US 2005/0263605 A1
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`US 2005/0263605 A1
`
`Dec. 1, 2005
`
`METHOD FOR IDENTIFYING SEMCONDUCTOR
`INTEGRATED CIRCUIT DEVICE, METHOD FOR
`MANUFACTURING SEMCONDUCTOR
`INTEGRATED CIRCUIT DEVICE,
`SEMCONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND SEMCONDUCTOR CHIP
`
`TECHNICAL FIELD
`0001. The present invention relates to a method for
`identifying a Semiconductor integrated circuit device, a
`method for manufacturing a Semiconductor integrated cir
`cuit device, a Semiconductor integrated circuit device and a
`Semiconductor chip, and mainly relates to the technology for
`assigning identification information unique to Semiconduc
`tor integrated circuit devices or Semiconductor chips to
`identify individual Semiconductor integrated circuit devices
`or Semiconductor chips.
`
`BACKGROUND ART
`0002. A semiconductor integrated circuit device can be
`utilized in a variety of desired manners based on identifi
`cation information unique thereto, if Such identification
`information is assigned. If unique identification information
`can be set to Semiconductor integrated circuit devices on a
`one-by-one basis, a novel manufacturing method and prod
`uct management technique, demonstrated by the inventors,
`can be provided under the utilization of the unique identi
`fication information, as described later.
`0003) When a fault occurs at a stage such as an actual use
`Stage of a Semiconductor integrated circuit device, factors
`causing the fault is readily pursued if unique identification
`information can be retrieved from the Semiconductor inte
`grated circuit device. For example, a Semiconductor maker
`can acquire information Such as the manufacturing term,
`manufacturing line, manufacturing lot, testing history,
`design information and the like based on the unique iden
`tification information of the Semiconductor integrated circuit
`device. This facilitates the pursuit of factors which cause the
`fault and countermeasures to be taken therefor.
`0004. The marking based on an ink printing method or a
`laser impressing method given to a package, which forms
`part of a Semiconductor integrated circuit device, can be
`regarded as one type of identification information. While
`this type of marking mainly comprises a product model
`name of the Semiconductor integrated circuit device, the
`product model name may be accompanied by a code repre
`Sentation of the manufacturing term Such as year, week and
`the like. However, with this type of marking representation,
`it is difficult to set unique identification information to
`Semiconductor integrated circuit devices on a one-by-one
`basis, which can be manufactured in large quantity or
`manufactured over a long term as industrial products, due to
`the Shortage of the amount of information which can be
`represented thereby.
`0005. It can be assumed to set a programmable element
`Such as a fuse element to a Semiconductor chip which forms
`part of a Semiconductor integrated circuit device and to give
`unique identification information inherent to the program
`mable element. However, if the original Semiconductor
`integrated circuit device does not need a program element,
`this type of assumable technique would disadvantageously
`cause a complicated manufacturing proceSS and an increased
`
`cost of the Semiconductor integrated circuit device due to the
`requirement for an additional manufacturing Step for the
`programmable element. The manufacturing process will be
`free from additional complication if the Semiconductor
`integrated circuit device originally has a programmable
`element. Even in this case, an additional or modified manu
`facturing Step is needed for writing unique recognition
`information into the programmable element.
`0006. In a know technique referred to as “silicon signa
`ture,” a product model name or unique information is written
`into a Semiconductor integrated circuit device in Such a
`manner that they can be electrically read out. However, this
`type of technique requires an additional or modified manu
`facturing Step for writing the information, as is the case with
`the foregoing.
`0007. The inventors were informed, through an investi
`gation after the present invention had been made, that
`inventions described in JP-A-6-196435, JP-A-10-055939,
`JP-A-11-214274, JP-A-7-335509, and JP-A-7-050233
`existed as related to the present invention, later described.
`Either of the inventions described in the official documents
`is recognized to require an extra manufacturing Step for
`Writing unique identification information into each chip.
`However, these official documents are not recognized to
`include any description related to a method for identifying a
`Semiconductor integrated circuit device which does not
`particularly require an additional or a modified manufactur
`ing Step as the present invention, later described.
`0008. It is therefore an object of the present invention to
`provide a Semiconductor integrated circuit device or a
`semiconductor chip which can be individually identified in
`a simple configuration, and a method for identifying a
`Semiconductor integrated circuit device or a Semiconductor
`chip. It is another object of the present invention to provide
`a Semiconductor integrated circuit device which is capable
`of identifying individual Semiconductor integrated circuit
`devices or Semiconductor chips with a high reliability. It is
`a further object of the present invention to provide a rational
`method for manufacturing a Semiconductor integrated cir
`cuit device. The above and other objects and novel features
`of the present invention will become apparent from the
`description of the Specification and the accompanying draw
`IngS.
`
`DISCLOSURE OF THE INVENTION
`0009 Representatives of the inventions disclosed in this
`application are briefly described in Summary as follows.
`Specifically, in course of a manufacturing process of Semi
`conductor integrated circuit devices, a plurality of identifi
`cation elements having the same arrangement are formed
`and the relation of magnitude in a physical amount corre
`sponding to variations in the process of the plurality of
`identification elements is employed as the basis for identi
`fication information unique to the Semiconductor integrated
`circuit device.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0010 FIG. 1 is a basic circuit diagram illustrating one
`embodiment of an identification number generator circuit
`according to the present invention;
`0011 FIG. 2 is a basic circuit diagram illustrating
`another embodiment of the identification number generator
`circuit according to the present invention;
`
`

`

`US 2005/0263605 A1
`
`Dec. 1, 2005
`
`0012 FIG. 3 is a basic circuit diagram illustrating
`another embodiment of the identification number generator
`circuit according to the present invention;
`0013 FIG. 4 is a diagram for describing the operation of
`the identification number generator circuit of FIG. 3;
`0.014
`FIG. 5 is a basic circuit diagram illustrating
`another embodiment of the identification number generator
`circuit according to the present invention;
`0.015
`FIG. 6 is an equivalent circuit diagram for describ
`ing the circuit in the embodiment of FIG. 5;
`0016 FIG. 7 is a circuit diagram illustrating a specific
`embodiment corresponding to the embodiment of FIG. 5;
`0017 FIG. 8 is a timing chart for describing the opera
`tion of the circuit in the embodiment of FIG. 7;
`0.018
`FIG. 9 is a diagram for describing the operation of
`the circuit in the embodiment of FIG. 7;
`0.019
`FIG. 10 is an exemplary modification illustrating
`one embodiment of a unit circuit which comprises a CMOS
`inverter circuit and Switch MOSFETs which are the core of
`the identification number generator circuit according to the
`present invention;
`0020 FIG. 11 is an exemplary modification illustrating
`another embodiment of the unit circuit which comprises a
`CMOS inverter circuit and Switch MOSFETs which are the
`core of the identification number generator circuit according
`to the present invention;
`0021
`FIG. 12 is an exemplary modification illustrating
`another embodiment of the unit circuit which comprises a
`CMOS inverter circuit and Switch MOSFETs which are the
`core of the identification number generator circuit according
`to the present invention;
`0022 FIG. 13 is an exemplary modification illustrating
`another embodiment of the unit circuit which comprises a
`CMOS inverter circuit and Switch MOSFETs which are the
`core of the identification number generator circuit according
`to the present invention;
`0023 FIG. 14 is an exemplary modification illustrating
`another embodiment of the unit circuit which comprises a
`CMOS inverter circuit and Switch MOSFETs which are the
`core of the identification number generator circuit according
`to the present invention;
`0024 FIG. 15 is an exemplary modification illustrating
`another embodiment of the unit circuit which comprises a
`CMOS inverter circuit and Switch MOSFETs which are the
`core of the identification number generator circuit according
`to the present invention;
`0.025
`FIG. 16 is a circuit diagram illustrating one
`embodiment of a CMOS inverter circuit used in the identi
`fication number generator circuit according to the present
`invention;
`0.026
`FIG. 17 is a circuit diagram illustrating another
`embodiment of the identification number generator circuit
`according to the present invention;
`0027 FIG. 18 is a waveform chart for describing the
`operation of the circuit in the embodiment illustrated in FIG.
`17;
`
`0028 FIG. 19 is a block diagram illustrating another
`embodiment of the identification number generator circuit
`according to the present invention;
`0029 FIG. 20 is a block diagram illustrating another
`embodiment of the identification number generator circuit
`according to the present invention;
`0030 FIG. 21 is a general block diagram illustrating one
`embodiment of a Semiconductor integrated circuit device
`according to the present invention;
`0031
`FIG. 22 is an element layout diagram illustrating
`one embodiment of the Semiconductor integrated circuit
`device according to the present invention;
`0032 FIG. 23 is an equivalent circuit diagram corre
`sponding to the foregoing FIG. 22,
`0033 FIG. 24 is a block diagram illustrating one
`embodiment in which the present invention is applied to
`dynamic RAM;
`0034 FIG.25 is a general schematic diagram illustrating
`one embodiment of a Semiconductor integrated circuit
`device which employs the identification number generator
`circuit according to the present invention;
`0035 FIG. 26 is an explanatory diagram for explaining
`an algorithm for identifying an identification number
`according to the present invention;
`0036 FIG. 27 is an explanatory diagram for explaining
`an algorithm for identifying an identification number
`according to the present invention;
`0037 FIG. 28 is a schematic diagram illustrating one
`embodiment of a method of registering a matching algo
`rithm in a System for identifying a Semiconductor integrated
`circuit device according to the present invention;
`0038 FIG. 29 is a schematic diagram illustrating one
`embodiment of the method of registering a matching algo
`rithm in the System for identifying a Semiconductor inte
`grated circuit device according to the present invention;
`0039 FIG. 30 is an explanatory diagram showing an
`exemplary comparison method in the foregoing FIG. 29;
`0040 FIG. 31 is an explanatory diagram showing a
`comparison method when using the order of logical thresh
`old values in a CMOS inverter circuit;
`0041
`FIG. 32 is an explanatory diagram showing a
`comparison method when using the order of logical thresh
`old values in the CMOS inverter circuit;
`0042 FIG. 33 is a schematic diagram illustrating one
`embodiment of a Semiconductor integrated circuit device to
`which the present invention is applied;
`0043 FIG. 34 is a block diagram illustrating one
`embodiment of a multi-chip module to which the present
`invention is applied;
`0044 FIG. 35 is a block diagram illustrating one
`embodiment of a dedicated program chip in the foregoing
`FIG. 34;
`004.5
`FIG. 36 is a schematic diagram for describing a
`manufacturing Step of one embodiment of a Semiconductor
`
`

`

`US 2005/0263605 A1
`
`Dec. 1, 2005
`
`integrated circuit device which is mounted with the identi
`fication number generator circuit according to this applica
`tion;
`FIG. 37 is a schematic diagram for describing a
`0.046
`manufacturing Step of one embodiment when a Semicon
`ductor integrated circuit device mounted with the identifi
`cation number generator circuit according to this application
`is assembled into a circuit mounting board;
`0047 FIG. 38 is a schematic diagram for describing a
`manufacturing Step of another embodiment of the Semicon
`ductor integrated circuit device which mounted with the
`identification number generator circuit according to this
`application;
`0.048
`FIG. 39 is a block diagram illustrating an exem
`plary application specific LSI which is provided with the
`identification number generator circuit according to the
`present invention;
`0049 FIG. 40 is a circuit diagram illustrating an embodi
`ment in which variations in logical threshold value of the
`CMOS inverter according to the present invention is applied
`to a random number generator;
`0050 FIG. 41 is a sche