(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2006/0012012 A1
`Wang et al.
`(43) Pub. Date:
`Jan. 19, 2006
`
`US 2006001 2012A1
`
`(52) U.S. Cl. .............................................................. 257/620
`
`(57)
`
`ABSTRACT
`
`(54) SEMICONDUCTOR DEVICE WITH CRACK
`PREVENTION RING AND METHOD OF
`MANUFACTURE THEREOF
`(76) Inventors: Ping-Wei Wang, Hsin-Chu (TW);
`Chi-Ming Morris Wu, Hsin-Chu (TW) A method of forming a crack prevention ring at the exterior
`Correspondence Address:
`edge of an integrated circuit to prevent delamination and
`SLATER & MATSIL, LLP.
`cracking during the Separation of the integrated circuits into
`1795O PRESTON ROAD, SUTE 1000
`individual die. The crack prevention ring extends vertically
`DALLAS, TX 75252 (US)
`into a Semiconductor workpiece to at least a metallization
`layer of the integrated circuit. The crack prevention ring may
`(21) Appl. No.:
`10/891,955
`be formed simultaneously with the formation of test pads of
`the integrated circuits. The crack prevention ring may be
`partially or completely filled with conductive material. An
`air pocket may be formed within the crack prevention ring
`beneath a passivation layer of the integrated circuit. The
`crack prevention ring may be removed during the Singula
`tion process. An optional Seal ring may be formed between
`the crack prevention ring and the integrated circut.
`
`(22) Filed:
`
`Jul. 15, 2004
`Publication Classification
`
`(51) Int. Cl.
`HOIL 23/544
`
`(2006.01)
`
`
`
`SAMSUNG EXHIBIT 1016
`Samsung v. Trenchant
`Case IPR2021-00258
`
`

`

`Patent Application Publication Jan. 19, 2006 Sheet 1 of 9
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`US 2006/0012012 A1
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`

`

`Patent Application Publication Jan. 19, 2006 Sheet 2 of 9
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`US 2006/0012012 A1
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`

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`Patent Application Publication Jan. 19, 2006 Sheet 3 of 9
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`US 2006/0012012 A1
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`

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`Patent Application Publication Jan. 19, 2006 Sheet 4 of 9
`
`US 2006/0012012 A1
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`

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`Patent Application Publication Jan. 19, 2006 Sheet 5 of 9
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`US 2006/0012012 A1
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`Patent Application Publication Jan. 19, 2006 Sheet 6 of 9
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`US 2006/0012012 A1
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`Patent Application Publication Jan. 19, 2006 Sheet 9 of 9
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`US 2006/0012012 A1
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`

`

`US 2006/0012012 A1
`
`Jan. 19, 2006
`
`SEMCONDUCTOR DEVICE WITH CRACK
`PREVENTION RING AND METHOD OF
`MANUFACTURE THEREOF
`
`TECHNICAL FIELD
`0001. The present invention relates generally to semicon
`ductor devices, and more particularly to the formation of a
`Seal ring at the edge of an integrated circuit to prevent
`delamination and cracks in insulating layers of the integrated
`circuit during die Separation.
`
`BACKGROUND
`0002. In the evolution of integrated circuits in semicon
`ductor technology, there has been a trend towards device
`Scaling. Scaling or reducing the Size increases circuit per
`formance, primarily by increasing circuit Speed, and also
`increases the functional complexity of the integrated cir
`cuits. The number of devices per integrated circuit (also
`referred to in the art as a chip or die) has increased
`throughout the years. When integrated circuits contained
`only a Small number of devices per chip, the devices could
`be easily interconnected in a single level. However, the need
`to accommodate more devices and increased circuit Speed
`has led to the use of multi-level or multi-layer interconnects.
`0003. In a multi-level interconnection system, the area
`needed by the interconnect lines is shared among two or
`more levels, which increases the active device fractional
`area, resulting in increased functional chip density. Imple
`menting a multilevel interconnect process to a fabrication
`Scheme increases the complexity of the manufacturing pro
`cess. Typically, the active devices (e.g., the transistors,
`diodes, capacitors and other components) are manufactured
`in the lower layers of wafer processing. After the active
`devices are processed, the multilevel interconnects are usu
`ally formed. Hundreds or thousands of chips or die are
`typically manufactured on a Single wafer. The die are
`Separated after the manufacturing proceSS is complete by
`Sawing the die apart on Scribe lines at edges of each die. The
`die are then individually packaged, or are packaged in
`multi-chip modules, as examples.
`0004 Assemiconductor devices continue to shrink, vari
`ous aspects of multilevel interconnect processes are chal
`lenged. The propagation delay of integrated circuits
`becomes limited by the large RC time delay of interconnec
`tion lines when minimum feature Size is decreased below
`about 1 um, for example. Therefore, the industry is tending
`towards the use of different materials and processes to
`improve multilevel interconnect implementations. In par
`ticular, the change in the conductive materials and insulating
`materials used in multilevel interconnect Schemes is proving
`challenging and requires a change in a number of processing
`parameterS.
`0005 For many years, the insulating material used to
`isolate conductive lines from one another was Silicon diox
`ide. Silicon dioxide has a dielectric constant (k) of approxi
`mately 4.0 or greater, where the dielectric constant value k
`is based on a Scale where 1.0 represents the dielectric
`constant of vacuum. However, now there is a trend in the
`Semiconductor industry towards the use of low-dielectric
`constant materials (e.g., having a dielectric constant k of
`about 3.5 or less) for insulating materials.
`
`0006 Integrated circuit manufacturers are employing
`finer circuit widths, low dielectric constant (low-k) materi
`als, and other technologies to make Smaller and higher-speed
`Semiconductor devices. Along with these advancements, the
`challenges of maintaining yield and throughput have also
`increased. Low-k materials tend to be weaker and less robust
`than the Silicon dioxide that was used as a dielectric material
`in the past. AS far as reliability is concerned, the low-k
`material near die cornerS has a tendency to crack/delamina
`tion, especially in the Sawing process to Separate the die
`from one another. The cracks tend to occur in a direction
`parallel to the wafer Surface.
`0007. In general, the scribe lines are defined in areas of
`the multi-layer Structure that are without a die circuit pattern
`and have a width of about 80 to 120 tim, depending on the
`dimensions of the die manufactured on the wafer. Further
`more, when at least one layer of the multi-layer Structure is
`composed of a metal material with a high thermal expansion
`coefficient, the dimensional variation of the layer is Suffi
`cient to introduce high-level internal StreSS into the wafer in
`the area of the Scribe line. Consequently, portions of the
`wafer around the Scribe line Suffer damage, Such as peeling,
`delamination, or dielectric fracture. The types of Scribe line
`damage mentioned above are usually observed when the
`multi-layer Structure includes an inter-metal-dielectric layer
`of low dielectric constant (low-k).
`0008. The stress resulting from the sawing process causes
`Serious peeling starting from near the test keys at the die
`corners. This results in delamination at the interface between
`the multiple layers at the die corners. Delamination impacts
`the reliability of the device, and contributes to production of
`Stringers (residual materials) that interfere with further pro
`cessing and testing of the integrated circuit. It is not uncom
`mon for Stresses to crack a passivation film formed over the
`die corners during the Sealing process of a resin mode
`package. If a low-k material is used near the guard ring
`corners, the crack issue becomes more Serious and further
`reduces reliability.
`
`SUMMARY OF THE INVENTION
`0009. These and other problems are generally solved or
`circumvented, and technical advantages are generally
`achieved, by preferred embodiments of the present inven
`tion, in which a crack prevention ring comprising a conduc
`tive material is formed near the edge of the integrated circuit
`die proximate the Scribe line. The crack prevention ring
`preferably extends deep within the integrated circuit device
`Vertically with respect to the workpiece, at least into a
`metallization layer of the integrated circuit. The crack pre
`vention ring may comprise the conductive material that test
`pads for the Semiconductor device comprise, and the crack
`prevention ring may either be lined with the conductive
`material or may be completely filled with the conductive
`material.
`0010. In accordance with a preferred embodiment of the
`present invention, a method of manufacturing a Semicon
`ductor device includes providing a workpiece and forming a
`plurality of integrated circuits over the workpiece. Each
`integrated circuit includes a Scribe line at the exterior edges
`thereof, and a plurality of metallization layerS formed over
`and being electrically coupled to the integrated circuit. The
`plurality of metallization layers include a first metallization
`
`

`

`US 2006/0012012 A1
`
`Jan. 19, 2006
`
`layer and at least one Second metallization layer disposed
`over the first metallization layer, and each metallization
`layer is formed in an insulating layer. The method includes
`forming a trench around at least one of the integrated circuits
`within and proximate the Scribe line, wherein the trench
`extends at least into the at least one Second metallization
`layer. A conductive material is formed over at least the
`trench around the at least one integrated circuit, wherein the
`conductive material within the trench forms a crack preven
`tion ring. The plurality of integrated circuits are then Sepa
`rated at the Scribe lines, wherein the crack prevention ring
`prevents cracking of the insulating layers while Separating
`the plurality of integrated circuits.
`0011. In accordance with another preferred embodiment
`of the present invention, a Semiconductor device includes at
`least a portion of a workpiece, and an integrated circuit
`disposed over the workpiece. The integrated circuit includes
`a plurality of metallization layerS disposed over and being
`electrically coupled to the integrated circuit. The plurality of
`metallization layers include a first metallization layer and at
`least one Second metallization layer disposed over the first
`metallization layer, wherein each metallization layer is
`formed in an insulating layer. A crack prevention ring is
`disposed around an exterior edge of the integrated circuit,
`the crack prevention ring comprising a conductive material
`and extending into at least the at one Second metallization
`layer.
`0012. An advantage of embodiments of the present
`invention includes providing a method of forming a crack
`prevention ring at the edges of an integrated circuit die that
`prevents cracking and delaminating of the dielectric material
`of the integrated circuit during the Separating of the die into
`individual die. The crack prevention ring comprises a con
`ductive material which has a high mechanical Strength and
`is robust. The conductive material of the crack prevention
`ring is formed perpendicular to the crack direction/wafer
`direction, thereby providing structural Support for the edges
`of the integrated circuit die during the Singulation process.
`The crack prevention ring may be formed while test pads of
`the integrated circuit are being formed, for example, in the
`Scribe line region. Device yields are improved, resulting in
`a cost Savings.
`0013 The foregoing has outlined rather broadly the fea
`tures and technical advantages of embodiments of the
`present invention in order that the detailed description of the
`invention that follows may be better understood. Additional
`features and advantages of embodiments of the invention
`will be described hereinafter, which form the subject of the
`claims of the invention. It should be appreciated by those
`skilled in the art that the conception and Specific embodi
`ments disclosed may be readily utilized as a basis for
`modifying or designing other Structures or processes for
`carrying out the same purposes of the present invention. It
`should also be realized by those skilled in the art that such
`equivalent constructions do not depart from the Spirit and
`Scope of the invention as Set forth in the appended claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0.014
`For a more complete understanding of the present
`invention, and the advantages thereof, reference is now
`made to the following descriptions taken in conjunction with
`the accompanying drawings, in which:
`
`0.015 FIGS. 1 through 5 and 6a show cross-sectional
`Views of a Semiconductor device at various stages of manu
`facturing in accordance with an embodiment of the present
`invention, wherein a crack prevention ring is formed proxi
`mate the Scribe lines of an integrated circuit;
`0016 FIG. 6b shows another embodiment of the inven
`tion, wherein the crack prevention ring trench is completely
`filled with a conductive material;
`0017 FIG. 7 shows a top view of the semiconductor
`device shown in FIGS. 1 through 6 prior to the singulation
`process, and
`0018 FIG. 8 shows a cross-sectional view of another
`embodiment of the present invention, wherein the crack
`prevention ring is partially filled with a conductive material
`and also includes an air pocket, an optional Seal ring is
`shown, and wherein the integrated circuit comprises mul
`tiple metallization and via layers formed therein.
`0019 Corresponding numerals and symbols in the dif
`ferent figures generally refer to corresponding parts unless
`otherwise indicated. The figures are drawn to clearly illus
`trate the relevant aspects of the preferred embodiments and
`are not necessarily drawn to Scale.
`
`DETAILED DESCRIPTION OF ILLUSTRATIVE
`EMBODIMENTS
`0020. The making and using of the presently preferred
`embodiments are discussed in detail below. It should be
`appreciated, however, that the present invention provides
`many applicable inventive concepts that can be embodied in
`a wide variety of Specific contexts. The Specific embodi
`ments discussed are merely illustrative of Specific ways to
`make and use the invention, and do not limit the Scope of the
`invention.
`0021. The present invention will be described with
`respect to preferred embodiments in a Specific context,
`namely a Semiconductor device having low dielectric con
`Stant materials as insulating layers. Embodiments of the
`invention may also be applied, however, to other Semicon
`ductor devices comprising more traditional dielectric mate
`rials and ultra-low dielectric constant materials, as
`examples.
`0022 FIGS. 1 through 5 and 6a show cross-sectional
`Views of a Semiconductor device at various stages of manu
`facturing in accordance with an embodiment of the present
`invention. Referring first to FIG. 1, a workpiece 102 is
`provided. The workpiece 102 includes a plurality of inte
`grated circuit regions 104. Only one integrated circuit region
`104 is shown in the drawings herein; however, there may be
`hundreds or thousands of integrated circuit regions 104 on a
`single workpiece 102. After the semiconductor device 100 is
`manufactured, the plurality of integrated circuit regions 104
`will be separated or singulated at a scribe line region 108
`Surrounding each integrated circuit region 104. The work
`piece 102 may include an optional seal ring region 105
`proximate the Scribe line region 108 and proximate each
`edge of the integrated circuit region 104, as shown.
`0023. In accordance with an embodiment of the present
`invention, a crack prevention ring region 106 is defined in
`the workpiece 102 proximate the exterior edge of the
`integrated circuit region 104, adjacent the Scribe line region
`
`

`

`US 2006/0012012 A1
`
`Jan. 19, 2006
`
`108. Optionally, the scribe line region 108 may include the
`crack prevention ring region 106, in one embodiment. In
`another embodiment, the scribe line region 108 may also
`include an optional Seal ring region 105, to be described
`further herein.
`0024. The semiconductor device 100 may include a plu
`rality of insulating, conductive, and Semiconductive layers
`110 formed over the workpiece 102. In one embodiment, in
`the crack prevention ring region 106 and Scribe line region
`108, preferably, layer 110a is absent any conductive layers,
`to be described further herein. The workpiece 102 may
`include portions of integrated circuits 112 formed within the
`workpiece 102. For example, active areas 112 may be
`formed within a top surface of the workpiece 102, wherein
`the active areas 112 comprise transistors and other electrical
`components of an integrated circuit. The various insulating
`layers, conductive layers, and Semiconductive layerS 110
`also comprise a portion of an integrated circuit. A shallow
`trench isolation (STI) region 114, shown in phantom, may be
`formed within portions of the workpiece 102, as shown.
`0025 Preferably, the top surface 121 of a portion of the
`integrated circuit region 104 comprises a conductive mate
`rial. For example, the top Surface 121 may comprise a
`conductive line formed in a metallization layer. Contact pads
`may be formed over the conductive top surface 121 in
`Subsequent process Steps. Also, in accordance with an
`embodiment of the present invention, preferably, no metal
`lization layerS or conductive layers are formed in the crack
`prevention ring region 106.
`0026. A first insulating layer 118 is deposited over the
`workpiece 102, as shown in FIG. 2. The first insulating layer
`118 preferably comprises a dielectric material Such as Silicon
`dioxide, and may alternatively comprise a nitride, or other
`types of passivation material and dielectric materials, as
`examples. The first insulating layer 118 preferably com
`prises a thickness of about 2 um or less, for example. The
`first insulating layer 118 is also referred to herein as a
`passivating layer.
`0.027
`Next, in accordance with embodiments of the
`present invention, the first insulating layer 118 is patterned
`to form an aperture 120 for an optional Seal ring in the Seal
`ring region 104 and a crack prevention ring trench 115 in the
`crack prevention ring region 106. The apertures 120 and
`trench 115 are preferably simultaneously formed in one
`embodiment. Advantageously, the same lithography Step
`may be used to form the aperture 120 for the seal ring and
`the crack prevention ring trench 115. Alternatively, the crack
`prevention ring trench 115 and the seal ring aperture 120
`may be formed in Separate lithography Steps, for example.
`0028. The etch process is adapted to stop upon reaching
`the conductive top surface 121 in the seal ring region 105.
`The aperture 120 for the seal ring is thus preferably formed
`only in the thickness of the first insulating layer 118.
`However, because there are no conductive layers in layer
`110a of the crack prevention ring region 106, in the crack
`prevention ring region 106, the etch process continues
`through the first insulating layer 118, and further into at least
`a portion of the plurality of insulating and Semiconductive
`layers 110a, to a depth indicated at 116a, 116b, 116c, or
`116d, as examples. The crack prevention ring trench 115
`preferably comprises a depth of about 1 to 8 um and a width
`of about 0.3 to 10 tim, for example. The crack prevention
`
`ring trench 115 preferably extends at least through the entire
`thickness of the top-most metallization layer of the inte
`grated circuit (not shown in FIG. 2; see FIG. 8). The crack
`prevention ring trench 115 preferably has an aspect ratio of
`about 3:1 or greater.
`0029. In accordance with preferred embodiments of the
`present invention, the crack prevention ring trench 115
`extends completely through the integrated circuit region 110
`and into a top Surface of the workpiece 102, e.g., at 116a, as
`shown. In one embodiment, the crack prevention ring trench
`115 extends within and into the entire thickness or a portion
`of a thickness of an STI region 114. Alternatively, the crack
`prevention ring trench 115 may extend within the plurality
`of insulating and semiconductive layers 110a by a variety of
`distances into corresponding layers of the integrated circuit
`region 110, e.g., as shown at 116b, 116c, and 116d in
`phantom. Preferably, in accordance with embodiments of the
`present invention, the crack prevention ring trench 115
`extends within the integrated circuit region 110a into an
`entire thickness of at least one metallization layer in inte
`grated circuit region 110 in the integrated circuit region 104.
`0030. A conductive material 124 is deposited over the
`patterned first insulating layer 118, as shown in FIG. 3. In
`one embodiment, the conductive material 124 lines the Seal
`ring trench 115 and does not completely fill the Seal ring
`trench 115. Alternatively, in another embodiment, the con
`ductive material 124 completely fills the Seal ring trench
`115, So that the conductive material 124 comprises a Sub
`Stantially planar Surface 126 over the Seal ring trench 115, as
`shown in phantom (see also FIG. 6b). The conductive
`material 124 may form a recess 128 over the aperture 120 for
`the optional Seal ring, as shown. Preferably, the conductive
`material 124 comprises copper, aluminum, Silver, tungsten,
`metal nitride, metal alloy, copper alloy, aluminum alloy,
`composites thereof, or combinations thereof, as examples,
`although alternatively, other materials may be used for the
`conductive material 124. The conductive material 124 is
`preferably deposited in a thickness of about 2000 nm or less,
`for example. Alternatively, the conductive material 124 may
`comprise other dimensions.
`0031. The conductive material 124 is patterned and
`etched to form (optionally) a seal ring 130 in the integrated
`circuit region 104, and to form the novel crack prevention
`ring 132 or 134 around each integrated circuit region 104 in
`accordance with embodiments of the present invention, as
`shown in FIG. 4. Test pads 156 may also be formed in the
`scribe line region 108 (not shown in FIG. 4; see FIG. 7).
`The test pads 156 may be used to perform electrical tests on
`the integrated circuit in the integrated circuit region 104 at
`various Stages of the manufacturing process. For example, if
`the testing using test pads 156 results in a large number of
`device failures, the workpiece may be Scrapped early in the
`manufacturing process, resulting in avoiding continue to
`manufacture a workpiece that exhibits electrical problems.
`0032 Referring again to FIG. 4, preferably the seal ring
`130 and crack prevention ring 132 or 134 (and also optional
`test pads 156) are patterned simultaneously, using the same
`lithography mask and patterning Step. The conductive mate
`rial 124 may be patterned using traditional lithography
`techniques, for example. A photoresist may be deposited
`over the conductive material 124 (not shown), and the
`photoresist may be patterned and exposed, and then the
`
`

`

`US 2006/0012012 A1
`
`Jan. 19, 2006
`
`photoresist may be used as a mask to pattern the underlying
`conductive material 124. Alternatively, the conductive mate
`rial 124 may be directly patterned, for example.
`0033. Note that in one embodiment, after the patterning
`of the conductive material 124, the crack prevention ring
`132 or 134 may comprise a completely filled trench, as
`shown in phantom at 134, or alternatively, the crack pre
`vention ring 132 may comprise a lined trench having a Void
`or air pocket 142 (not shown in FIG. 4; see FIG. 5) therein.
`0034) Next, a second insulating layer 136 is deposited
`over the first insulating layer 118, seal ring 130, and crack
`prevention ring 132 or 134, as shown in FIG. 5. The second
`insulating layer 136 may comprise Similar materials as
`described for the first insulating layer 118, for example. The
`Second insulating layer 136 preferably comprises a thickneSS
`of about 2 um or less, for example. If the crack prevention
`ring 132 lines the trench 115 rather than filling it, then an air
`pocket 142 is formed within the crack prevention ring 132
`beneath the Second insulating layer 136 in the crack pre
`vention ring region 106, as shown.
`0035. The second insulating layer 136 is patterned using
`lithography to form an aperture 138 over the seal ring 130
`and to form an aperture 140 over a scribe line in the scribe
`line region 108. Advantageously, apertures 138 and 140 may
`be patterned in a single lithography Step. The Second insu
`lating layer 136 preferably remains unpatterned and intact in
`the Seal ring region 106, as shown.
`0036) The workpiece 102 is then subjected to a singula
`tion process in order to Separate the integrated circuit
`regions 104 from one another to form individual integrated
`circuit die 148, as shown in FIG. 6a. In particular, the
`plurality of integrated circuit regions 104 of the workpiece
`102 are separated at the scribe line regions 108 by making
`a cut or saw line 144 along the scribe line regions 108 to
`form individual die 148, as shown. The plurality of inte
`grated circuit regions 104 may be separated utilizing dia
`mond Sawing, laser cutting, liquid jet Scribing, water jet
`cutting, or combinations thereof, as examples. The Separat
`ing of the plurality of integrated circuit regions 104 may
`alternatively comprise other methods. The individual die
`148 may then be packaged, with contact pads (not shown;
`the contact pads reside elsewhere over the workpiece 102)
`being bonded to leads of the package So that electrical
`connection can be made to the die 148.
`0037 FIG. 6b shows another embodiment of the present
`invention, wherein the crack prevention ring 134 is com
`pletely filled with the conductive material 124 (see FIG. 3).
`0.038. In one embodiment, the crack prevention ring 132
`or 134 is located very close to the scribe line 144. The crack
`prevention ring 132 or 134 may be located within the scribe
`line region 108, for example. In this embodiment, the crack
`prevention ring 132 or 134 is removed during the Sawing
`process to singulate the die (not shown). The seal ring 130
`may also be removed during the Sawing process (also not
`shown). In another embodiment, the crack prevention ring
`132 or 134 preferably remains after the singulation process.
`In this embodiment, the crack prevention ring 132 or 134
`may be electrically grounded to reduce noise and/or protect
`against damage from electro-static discharge (ESD), as
`examples.
`0039 FIG. 7 shows a top view of the semiconductor
`device shown in FIGS. 1 through 6 prior to the singulation
`
`process. Shown in FIG. 7 is a view of four integrated circuit
`regions 104 at their corner regions. AS can be seen from this
`top view, the scribe line region 108 extends along the side
`edges of the integrated circuit regions 104 and along the
`bottom and top edges of the integrated circuit regions 104.
`The crack prevention ring 132/134 described herein in
`accordance with embodiments of the present invention is
`formed proximate the scribe line region 108 at the exterior
`edge of the integrated circuit regions 104, as shown. In
`particular, the crack prevention ring 132/134 is formed
`continuously along the perimeter 146 of the integrated
`circuit regions 104. The optional seal rings 130 are shown
`disposed between the crack prevention rings 132/134 and
`the integrated circuit regions 104. Note that the corners 152
`of the integrated circuit regions 104 may be angled rather
`than at a 90 degree angle, as shown. Optional test pads 156
`that may be formed of the conductive material 124 and that
`may be disposed within the scribe line region 108 are also
`shown in FIG. 7. The optional test pads 156 are removed
`during the Singulation process.
`0040 FIG. 8 shows a cross-sectional view of another
`embodiment of the present invention, wherein the integrated
`circuit regions 204 comprise multiple levels of metallization
`M1-9 and vias V1-8 formed therebetween. Similar reference
`numbers are designated for the various elements as were
`used in FIGS. 1 through 7. To avoid repetition, each
`reference number shown in the diagram is not described
`again in detail herein. Rather, similar numbers x02/x04/x06,
`etc., are preferably used for the material layers shown as
`were described for FIGS. 1 through 7, where x=1 in FIGS.
`1 through 7 and X=2 in FIG.8. As an example, the preferred
`and alternative materials listed for the conductive material
`124 in the description for FIGS. 1 through 6 are preferably
`also used for the conductive material 224 in FIG. 8.
`0041 An etch stop layer 250 may be disposed between
`each insulating layer, as shown. The Scribe line region 208
`may optionally include the crack prevention ring region 206,
`or may include both the crack prevention ring region 206
`and a Seal ring region 205, as shown in phantom. The
`materials in the scribe line region 208 are removed or sawed
`away when the die are Singulated, for example.
`0042 Preferably, in the embodiment shown in FIG.8, the
`crack prevention ring 232 or 234 in the crack prevention ring
`region 206 extends down to a corresponding level in the
`integrated circuit region 204 past at least the top metalliza
`tion layer M9, as shown at 216d in FIG.8. Alternatively, the
`crack prevention ring 232 or 234 may extend past Several
`metallization layers M4 through M9 and via levels V4
`through V8, as shown at 216c. Alternatively, the crack
`prevention ring 232 or 234 may extend past all of the
`metallization layers M1 through M9 and via layers V1
`through V8, as shown at 216b. In yet another embodiment,
`the crack prevention ring 232 or 234 may be formed so that
`it extends entirely through the integrated circuit region 210a
`of the semiconductor device 200 and further extends into a
`portion of the workpiece 202, as shown at 216a. In one
`embodiment, the crack prevention ring 232 or 234 may also
`extend at least partially through an STI region 214 formed
`within the workpiece 202, as shown in phantom in FIG. 8.
`0043 Advantages of embodiments of the invention
`include providing a method of forming a crack prevention
`ring 132,134,232, or 234 proximate a scribe line region 140
`
`

`

`US 2006/0012012 A1
`
`Jan. 19, 2006
`
`and 240 of an integrated circuit 100 and 200. The crack
`prevention ring 132, 134, 232, or 234 may be formed at the
`same time as seal rings 130 and 230 and/or test pads 156/256
`that are used to perform electrical tests on the integrated
`circuit die 148. Because the crack prevention ring 132, 134,
`232, or 234 is formed using the Same conductive material
`124 or 224 and lithography masks that are used to form the
`seal rings 130 and 230 that may already be included in a
`Semiconductor device, no additional manufacturing Steps or
`masks are required to manufacture the Semiconductor
`devices 100 and 200 described herein. The crack prevention
`rings 132, 134, 232, and 234 described herein are particu
`larly advantageous when used in semiconductor devices 100
`and 200 having low dielectric constant materials or ultra-low
`dielectric constant materials as insulating layers, although
`they are also useful in other Semiconductor device applica
`tions utilizing other types of insulating materials. The crack
`prevention rings 132, 134,232, and 234 prevent delamina
`tion of the insulating layers of the Semiconductor devices
`100 and 200 during the separation of the individual die 148.
`0044) The conductive material 124 or 224 of the crack
`prevention ring 132,134,232 or 234 comprises a continuous
`metal film formed perpendicular to the wafer Surface
`through one or more layers of a Semiconductor device. The
`crack prevention ring 132, 134, 232, or 234 is formed
`vertically in a plurality of material layers 110/210, prevent
`ing cracks that may otherwise tend to form laterally in a
`direction parallel to the wafer Surface during the Singulation
`process. The conductive material 124 or 2