(12) United States Patent
`Ball
`
`USOO6784O23B2
`(10) Patent No.:
`US 6,784,023 B2
`(45) Date of Patent:
`Aug. 31, 2004
`
`(54) METHOD OF FABRICATION OF STACKED
`SEMCONDUCTOR DEVICES
`
`(75) Inventor: Michael B. Ball, Boise, ID (US)
`(73) Assignee: Micron Technology, Inc., Boise, ID
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/943,880
`(22) Filed:
`Aug. 30, 2001
`(65)
`Prior Publication Data
`
`US 2002/0031864 A1 Mar. 14, 2002
`Related U.S. Application Data
`(63) Continuation of application No. 09/651,394, filed on Aug.
`29, 2000, now Pat. No. 6,337,227, which is a continuation
`of application No. 08/844,669, filed on Apr. 18, 1997, now
`Pat. No. 6,165,815, which is a continuation of application
`No. 08/650,429, filed on May 20, 1996, now abandoned.
`(51) Int. Cl. ................................................ H01L 21/50
`(52) U.S. Cl. ....................... 438/113; 438/122; 438/458;
`438/460
`(58) Field of Search .............................. 438/22, 33, 48,
`438/57, 68, 106, 107, 109, 110, 113, 114,
`118, 119, 455, 458, 459, 460, 462, 464,
`977, 365, 368, 386; 257/678, 685, 686,
`723, 724, 734, 777, 782, 783,786
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`9/1984 Christian et al. ............. 29/577
`4,472,875. A
`4,826,787 A 5/1989 Muto et al. ...........
`... 438/455
`4,862,245 A 8/1989 Pashby et al. ...
`... 257/660
`5,012,323 A 4/1991 Farnworth .................. 257/723
`5,019,943 A 5/1991 Fassbender et al. ........ 361/396
`5,051865 A 9/1991 Kato .......................... 361/386
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`
`JP
`56-62351
`5/1981
`JP
`62-126661
`6/1987
`JP
`63-104343
`5/1988
`JP
`63-179537
`7/1988
`JP
`64-28856
`1/1989
`JP
`O1-3O3730
`12/1989
`JP
`1-158083
`1/1991
`JP
`O3-255657
`11/1991
`JP
`O4-76.946
`3/1992
`JP
`6-177323
`6/1994
`JP
`3-169062
`7/1997
`Primary Examiner Alonzo Chambliss
`(74) Attorney, Agent, or Firm TraskBritt
`(57)
`ABSTRACT
`A method for increasing integrated circuit density compris
`ing Stacking an upper wafer and a lower wafer, each of
`which have fabricated circuitry in Specific areas on their
`respective face Surfaces. The upper Wafer is attached back
`to-back with the lower wafer with a layer of adhesive
`applied over the back side of the lower wafer. The wafers are
`aligned So as to bring complimentary circuitry on each of the
`wafers into perpendicular alignment. The adhered wafer pair
`is then itself attached to an adhesive film to immobilize the
`wafer during dicing. The adhered wafer pair may be diced
`into individual die pairs or wafer portions containing more
`than one die pair.
`
`4.264,917 A 4/1981 Ugon ......................... 257/668
`
`10 Claims, 6 Drawing Sheets
`
`
`
`SAMSUNG EXHIBIT 1015
`Samsung v. Trenchant
`Case IPR2021-00258
`
`

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`US 6,784,023 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`5,104.820 A 4/1992 Go et al. .................... 438/109
`5,146,308 A 9/1992 Chance et al. .............. 257/782
`5,147,815 A 9/1992 Casto
`438/107
`5,229,647 A 7/1993 Gnadinger .................. 257/785
`5,239,198 A 8/1993 Lin et al. .................... 257/693
`5,252,857 A 10/1993 Kane et al. .
`... 257/686
`5,266,833. A 11/1993 Capps ........................ 257/690
`5,291,061 A 3/1994 Ball ........................... 257/686
`5,323,060 A 6/1994 Fogal et al.
`257/777
`5,331,235 A 7/1994 Chun ......................... 257/777
`5,399,898 A 3/1995 Rostoker .................... 257/499
`5,422,435 A 6/1995 Takiar et al.
`174/52.4
`5,426,072 A 6/1995 Finnila ....................... 438/107
`5,432,681 A 7/1995 Linderman .................. 361/790
`
`5,438,224 A 8/1995 Papageorge et al. ........ 257/777
`5,466,634 A 11/1995 Beilstein, Jr. et al. ........ 438/15
`5,471.369 A 11/1995 Honda et al. ............... 361/813
`5,483,024 A 1/1996 Russell et al.
`174/524
`5,484.959 A
`1/1996 Burns ......................... 174/524
`5,547.906 A 8/1996 Badehi ....................... 438/109
`5,567,654 A 10/1996 Beilstein, Jr. et al.
`... 438/4
`5,675,180 A 10/1997 Pedersen et al. ............ 257/685
`5,786.237 A 7/1998 Cockerill .................... 438/109
`5,851,845. A 12/1998 Wood et al.
`... 438/15
`5,917.242 A 6/1999 Ball ........................... 257/737
`5,952,725 A * 9/1999 Ball ........................... 257/777
`6,165,815 A * 12/2000 Ball
`438/113
`6,380,630 B1
`4/2002 Kinsman .................... 257/777
`* cited by examiner
`
`
`
`

`

`U.S. Patent
`US. Patent
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`1
`METHOD OF FABRICATION OF STACKED
`SEMCONDUCTOR DEVICES
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`This application is a continuation of application Serial
`No. 09/651,394, filed Aug. 29, 2000, pending, which is a
`continuation of U.S. patent application Ser. No. 08/844,669
`filed Apr. 18, 1997, now U.S. Pat. No. 6,165,815, issued
`Dec. 26, 2000, which is a continuation of U.S. patent
`application Ser. No. 08/650,429, filed May 20, 1996, aban
`doned.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to an apparatus and a
`method for increasing Semiconductor device density. In
`particular, the present invention relates to a method for
`producing vertically Superimposed multi-chip devices
`uSable with combined flip-chip, wire bond, and/or tape
`automated bonding (“TAB") assembly techniques to achieve
`densely packaged Semiconductor devices.
`2. State of the Art
`Definitions: The following terms and acronyms will be
`used throughout the application and are defined as follows:
`BGA-Ball Grid Array: An array of minute solder balls
`disposed on an attachment Surface of a Semiconductor die
`wherein the Solder balls are refluxed for simultaneous
`attachment and electrical communication of the Semicon
`ductor dice to a printed circuit board. A BGA may also
`employ conductive polymer balls.
`COB-Chip On Board: The techniques used to attach
`Semiconductor dice to a printed circuit board, including
`flip-chip attachment, wirebonding, and TAB.
`Flip-chip: A chip or die that has a pattern or array of
`terminations Spaced around the active Surface of the die for
`face down mounting of the die to a Substrate.
`Flip-chip Attachment: A method of attaching a Semicon
`ductor die to a Substrate in which the die is inverted so that
`the connecting conductor pads on the face of the device are
`Set on mirror-image pads on the Substrate (Such as a printed
`circuit board), and bonded by solder reflux or a conductive
`polymer curing.
`Glob Top: A glob of encapsulant material (usually epoxy
`or Silicone or a combination thereof) Surrounding a semi
`conductor die in a COB assembly.
`PGA-Pin Grid Array: An array of small pins extending
`Substantially perpendicular from the major plane of a Semi
`conductor die, wherein the pins conform to a specific
`arrangement on a printed circuit board or other Substrate for
`attachment thereto.
`SLICC Slightly Larger than Integrated Circuit Carrier:
`An array of minute Solder balls disposed on an attachment
`Surface of a Semiconductor die Similar to a BGA, but having
`a smaller solder ball pitch and diameter than a BGA.
`TAB-Tape Automated Bonding. Conductive traces are
`formed on a dielectric film Such as a polyimide (the structure
`also being termed a “flex circuit”), and the film is precisely
`placed to electrically connect a die and a circuit board or
`leadframe through the traces. Multiple connections are
`Simultaneously effected.
`State-of-the-art COB technology generally consists of
`three Semiconductor die-to-printed circuit board conductive
`attachment techniques: flip-chip attachment, wirebonding,
`and TAB.
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`US 6,784,023 B2
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`Flip-chip attachment consists of attaching a Semiconduc
`tor die, generally having a BGA, a SLICC or a PGA, usually
`to a printed circuit board, although flip-chip attachment to
`leadframes is also known. With the BGA or SLICC, the
`Solder or other conductive ball arrangement on the Semi
`conductor die must be a mirror-image of the connecting
`bond pads on the printed circuit board Such that a precise
`connection is made. The Semiconductor die is bonded to the
`printed circuit board Such as by refluxing the Solder balls or
`curing the conductive polymer. With the PGA, the pin
`arrangement of the Semiconductor die must be a mirror
`image of the pin recesses on the printed circuit board. After
`insertion, the Semiconductor die is generally bonded by
`Soldering the pins into place. An under-fill encapsulant is
`generally disposed between the Semiconductor die and the
`printed circuit board for environmental protection and to
`enhance the attachment of the die to the board. A variation
`of the pin-in-recess PGA is a J-lead PGA, wherein the loops
`of the Js are Soldered to pads on the Surface of the circuit
`board.
`Wirebonding and TAB attachment generally begins with
`attaching a Semiconductor die, usually by its back Side, to
`the Surface of a printed circuit board with an appropriate
`adhesive, Such as an epoxy. In wirebonding, a plurality of
`bond wires are attached, one at a time, to each bond pad on
`the Semiconductor die and extend to a corresponding lead or
`trace end on the printed circuit board. The bond wires are
`generally attached through one of three industry-standard
`wirebonding techniques: ultraSonic bonding-using a com
`bination of pressure and ultraSonic vibration bursts to form
`a metallurgical cold weld; thermocompression bonding
`using a combination of pressure and elevated temperature to
`form a weld; and thermosonic bonding using a combina
`tion of pressure, elevated temperature, and ultraSonic vibra
`tion bursts. The die may be oriented either face up or face
`down (with its active Surface and bond pads either up or
`down with respect to the circuit board) for wire bonding,
`although face up orientation is more common. With TAB,
`ends of metal leads carried on an insulating tape Such as a
`polyimide are attached to the bond pads on the Semicon
`ductor die and to corresponding lead or trace ends on the
`printed circuit board. An encapsulant is generally used to
`cover the bond wires and metal tape leads to prevent
`contamination; TAB assemblies may be similarly encapsu
`lated.
`Higher performance, lower cost, increased miniaturiza
`tion of components, and greater packaging density of inte
`grated circuits are ongoing goals of the computer industry.
`Greater integrated circuit density is primarily limited by the
`Space or “real estate' available for mounting dice on a
`Substrate Such as a printed circuit board. Conventional
`leadframe design inherently limits package density for a
`given die Size because the die-attach paddle of the leadframe
`must be larger than the die to which it is bonded. The larger
`the die, the leSS space that remains around the periphery of
`the die-bonding pad for wire bonding. Furthermore, the wire
`bonding pads on the Standard leadframe provide anchorage
`for the leads when the leads and the die are encapsulated in
`plastic. Therefore, as the die Size is increased in relation to
`a given package size, there is a corresponding reduction in
`the lateral depth along the Sides of the package for the
`encapsulating plastic which joins the top and bottom of the
`plastic body at the mold part line and anchors the leads.
`Thus, as the leads and encapsulant are Subjected to the
`normal Stresses of Subsequent trimming, forming and assem
`bly operations, the encapsulating plastic may crack, com
`promising package integrity and Substantially increasing the
`probability of premature device failure.
`
`

`

`US 6,784,023 B2
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`A so-called “leads over chip’ (LOC) arrangement elimi
`nates the die-attach paddle of the leadframe and Supports the
`die by its active surface from the inner lead ends of the
`leadframe. This permits a wider variety of bond pad patterns
`on the die, extends the leads-to-encapsulant bond area and,
`with appropriate design parameters, can reduce the size of
`the packaged device for a given die size.
`One method of increasing integrated circuit density is to
`stack dice vertically. U.S. Pat. No. 5,012,323 issued Apr. 30,
`1991 to Farnworth teaches combining a pair of dice mounted
`on opposing Sides of a leadframe. An upper, Smaller die is
`back-bonded to the upper surface of the leads of the lead
`frame via a first adhesively coated, insulated film layer. A
`lower, larger die is face-bonded to the lower leadframe
`die-bonding region via a Second, adhesively coated, insula
`tive film layer. The wire-bonding pads on both upper and
`lower dice are interconnected with the ends of their associ
`ated lead extensions with gold or aluminum bond wires. The
`lower die must be slightly larger than the upper die So that
`the die pads are accessible from above through a bonding
`window in the leadframe Such that gold wire connections
`can be made to the lead extensions. This arrangement has a
`major disadvantage from a production Standpoint, Since the
`different size dice require that different equipment produce
`the different dice or that the Same equipment be Switched
`over in different production runs to produce the different
`dice.
`U.S. Pat. No. 5.229,647 issued Jul. 20, 1993 to Gnadinger
`teaches Stacking wafers and using nonmechanically bonded
`electrical connections effected by metal-filled through holes
`contacting aligned conductive bumps of an adjacent wafer.
`U.S. Pat. No. 5,291,061 issued Mar. 1, 1994 to Ball
`teaches a multiple Stacked die device containing up to four
`Stacked dice Supported on a die-attach paddle of a leadframe,
`the assembly not exceeding the height of current Single die
`packages, and wherein the bond pads of each die are
`wirebonded to lead fingers. The low profile of the device is
`achieved by close-tolerance Stacking which is made possible
`by a low-loop-profile wirebonding operation and thin adhe
`Sive layers between the Stacked dice.
`U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et
`al. teaches a multi-chip module that contains Stacked die
`devices, the terminals or bond pads of which are wirebonded
`to a Substrate or to adjacent die devices.
`U.S. Pat. No. 5,422,435 to Takiar et al. teaches stacked
`dice having wire bonds extending to each other and to the
`leads of a carrier member Such as a leadframe.
`U.S. Pat. No. 5,399,898 issued May 21, 1995 to Rostoker
`teaches multi-chip, multi-tier Semiconductor arrangements
`based on Single and double-sided flip-chips. Using these
`dice to form a Stacked die package eliminates the need for
`wirebonding and thus reduces the size of the Stacked die
`package. However, these die Stacks require double-sided
`flip-chips which are expensive and difficult to manufacture.
`See also U.S. Pat. Nos. 5,146,308; 5.252,857; and 5,266,
`833 for additional background regarding die configurations
`and assemblies employing dice.
`Therefore, it would be advantageous to develop a tech
`nique and assembly for increasing integrated circuit density
`using noncustomized die configurations in combination with
`commercially-available, widely-practiced Semiconductor
`device fabrication techniques.
`BRIEF SUMMARY OF THE INVENTION
`The present invention relates to a method for increasing
`integrated circuit density. The method comprises providing
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`a pair of Semiconductor wafers which are each provided on
`a face Side with a desired integrated circuit pattern by
`techniques known in the industry. The completed wafers are
`then mounted back-to-back by a layer of adhesive material
`Such that the back or blank SideS face one another and the
`circuit-carrying or active sides face outward. The layer of
`adhesive, in Some instances an electrically insulative
`adhesive, as required or desired to electrically isolate back
`to-back adjacent dice, is applied over the back Side of one
`wafer. The back side of the other wafer is placed on the
`adhesive, thereby attaching the wafers back-to-back to form
`a two-wafer Stack. Depending on the adhesive, the assembly
`may be cured (as in the case of a thermosetting adhesive) to
`affix the wafers together. It is, of course, understood that the
`other types of adhesives not requiring a cure, Such as
`preSSure Sensitive adhesives, could be used to hold the
`wafers back-to-back.
`Generally, the waferS define identical die sizes, shapes
`and locations to facilitate Singulation after assembly, and
`may include identical circuitry and bond pad arrangements
`on their respective dice, although this is not required. One
`technique for precisely aligning the waferS is to employ the
`wafer flats. It is, of course, understood that the more
`complex techniques Such as pattern recognition Systems
`could be employed to align the wafers through recognition
`of Surface features and markings.
`Once the wafers are aligned and adhered, the wafer Stack
`is mounted onto a Stretchable adhesive film carried by a
`frame, as known in the art. The adhesive film is used to
`immobilize the wafer Stack for Scribing or Sawing to Singu
`late the dice or excise portions or Segments of the wafers,
`Sawing being highly preferred over Scribing due to the
`double thickness of the wafer stack. The wafer stack/film
`frame assembly is then Sent through a dicing or Singulation
`procedure wherein individual Stacked dice pairs or wafer
`portions containing groups of dice pairs are cut from the
`wafer Stack using a wafer dicing Saw. The “Streets of the
`front and back wafers of the Stack are, of course, aligned
`Such that the circuitry on both waferS is not damaged during
`the dicing process.
`It is, of course, understood that the above alignment,
`adherence and Separation process can be employed using
`portions of wafers rather than full wafers, although this is
`not preferred and may be impractical Since handling and
`Sawing equipment is generally designed to accommodate
`full wafers, and proceeding at leSS than wafer level may be
`economically undesirable.
`After the paired dice or wafer portions are removed from
`the wafer Stack and adhesive film frame by a pick-and-place
`apparatus as known in the art, the film being Stretched to
`enhance Separation of component parts of the wafer at the
`Sawing, they may be attached to a carrier Substrate, Such as
`a printed circuit board (PCB) or leadframe. A lower die of
`the dice pair is preferably configured as a flip-chip having,
`for example, BGA or SLICC solder bump connections,
`conductive polymer bumps, pin connections (PGA), or
`Surface mount J-lead connections extending Substantially
`perpendicular from the circuitry face of the lower die for
`attachment and electrical communication of the die to the
`carrier Substrate. The Substrate is configured with a specific
`lead end or trace end pattern compatible with the Specific pin
`out or bump connections on the lower die.
`An upper die of the dice pair can be used to align the dice
`pair to the Substrate. The use of the upper die for alignment
`allows the dice pair to be placed within plus or minus
`0.0002-0.0003 inch of the desired location. Optical align
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`US 6,784,023 B2
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`S
`ment Systems including, without limitation, pattern recog
`nition Systems as known in the art, are Suitable to effect
`alignment to Such tolerances. Once the dice pair is attached,
`an under-fill encapsulant is generally disposed between the
`lower die and the substrate (if other than a leadframe) for
`environmental protection and to enhance the attachment of
`the dice pair to the Substrate.
`Normally, the circuitry Side or active Surface of the upper
`die includes a plurality of bond pads. After attachment of the
`dice pair to the Substrate, the bond pads of the upper die are
`brought into electrical communication with conductors of
`the Substrate with wire bonds or TAB attachment. Bond
`wires and TAB traces of gold, aluminum or other suitable
`materials as known in the art are attached between the upper
`die bond pads and corresponding trace ends or lead ends of
`the Substrate. If the die Stack resides on a Solid Substrate Such
`as a PCB, an encapsulant Such as a glob-top is generally used
`to cover the bond wires or flex circuit to prevent contami
`nation. If the die pair is Secured to a leadframe, the assembly
`may be plastic encapsulated as known in the art, as by
`transfer molding. Of course, preformed ceramic or metal
`packaging as known in the art may also be employed.
`It is, of course, also understood that both the upper and
`lower dice may be flip-chips having an array of minute
`Solder balls or Small pins for respective attachment to two
`opposing Substrates Such as facing PCBs or leadframes, or
`to a two-piece leadframe as known in the art.
`The method of the invention increases Semiconductor
`device density using noncustomized die and bond pad
`patterns and commercially-practiced mechanical and elec
`trical attachment techniques.
`It will also be recognized by those skilled in the art that
`the Stacked waferS may be employed as a wafer level
`assembly, as in the case where extremely large memory
`capacity is required.
`It will also be appreciated that, while the wafers have been
`described as adhered back-to-back, face-to-back adherence
`is also possible, that more than two waferS may be adhered
`with the use of appropriately-placed bond pads and that
`chamfering, undercutting or notching of the upper wafer
`edges may be effected to access lower wafer peripheral bond
`pads.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWINGS
`While the specification concludes with claims particularly
`pointing out and distinctly claiming that which is regarded
`as the present invention, the advantages of this invention can
`be more readily ascertained from the following description
`of the invention when read in conjunction with the accom
`panying drawings in which:
`FIG. 1 is a top plan view of an etched wafer;
`FIG. 2 is a side plan view of an adhered wafer pair;
`FIG. 3 is a side plan view of the wafer pair of FIG. 2
`attached to the adhesive film frame;
`FIG. 4 is a top plan view of the wafer pair of FIG.3 after
`dicing;
`FIG. 5 is a side cross-sectional view of the wafer pair
`along line 5-5 of FIG. 4;
`FIG. 6 is a side plan view of a die assembly of the present
`invention;
`FIG. 7 is a side plan view of an alternative die assembly
`of the present invention;
`FIG. 8 is a side plan view of another alternative die
`assembly of the present invention; and
`
`6
`FIG. 9 is a side plan view of an alternative arrangement
`of an adhered wafer pair according to the invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 illustrates a top plan view of an exemplary
`completed wafer 100 of the present invention. The wafer
`100 comprises an upper surface 102 displaying the active
`sides of a plurality of dice 104. The dice 104 each contain
`identical integrated circuitry which will be independently
`functional after the dice are separated from the wafer. While
`in practice, the dice 104 are extremely closely packed on the
`wafer and essentially contiguous, but for the wafer material
`Sacrificed during Sawing, the dice 104 have been shown as
`more widely spaced for clarity in disclosure of the method
`of the invention. The wafer 100 also includes a flat lateral
`edge 106, as known in the art. The method of the present
`invention comprises fabricating appropriate circuitry in the
`upper wafer Surface 102 at the locations of the dice 104 by
`techniques well known in the industry.
`As shown in FIG. 2, a wafer pair assembly 200 comprises
`completed wafers 202 (upper wafer) and 204 (lower wafer)
`secured with an adhesive 206 disposed between the upper
`wafer 202 and the lower wafer 204. The wafer mounting
`arrangement is such that a back side 208 of upper wafer 202
`and a back side 210 of lower wafer 204 face one another and
`a circuitry or active surface 212 of the upper wafer 202 and
`a circuitry or active surface 214 of the lower die 204 face
`outward.
`Preferably, the upper wafer 202 and the lower wafer 204
`contain complementary die locations, Sizes, shapes and
`orientations such that when the wafers 202 and 204 are
`mounted, the dice of one wafer vertically align with that of
`the other. One technique for precisely aligning the waferS is
`to fabricate each wafer in Such a manner that aligning the
`wafer flat lateral edges 106 (FIG. 1) automatically aligns the
`dice and circuitry. It is, of course, understood that the more
`complex techniques Such as a pattern recognition System
`could be employed to precisely align the wafers.
`FIG. 3 illustrates a side plan view of an immobilized
`wafer assembly 300 comprising the wafer pair 200 of FIG.
`2 attached to an adhesive film 302. Components common to
`FIGS. 1, 2 and 3 retain the same numeric designation. After
`the upper wafer 202 and lower wafer 204 are aligned and
`mutually adhered with adhesive 206, the wafer pair 200 is
`mounted onto the adhesive film 302 carried by a frame (not
`shown). The adhesive film 302 is used to immobilize the
`wafer pair 200. This immobilization prevents the movement
`of the wafer pair 200 when the immobilized assembly 300
`is Sent through a separation or Singulation procedure, which
`may cut individual Stacked dice pairs or groups of dice pairs
`(or other wafer portions) from the wafer pair 200 using a
`wafer dicing saw (not shown) as known in the art for cutting
`Single wafers.
`FIG. 4 illustrates a top plan view of a partially kerfed or
`sawed wafer pair assembly 400. FIG. 5 illustrates a side
`cross-sectional view along line 5-5 of FIG. 4. Components
`common between FIGS. 1-5 retain the same numeric des
`ignation. The partially kerfed wafer pair assembly 400
`shows the wafer pair 200 immobilized on the adhesive film
`302 after a pass of a wafer dicing Saw in one direction
`creating parallel kerfs 402. The wafer dicing Saw is, per
`normal practice, preferably Set to cut Substantially through
`the wafer pair 200 without cutting the adhesive film 302 (see
`FIG. 5). If the dice 104 are to be singulated as dice pairs for
`use, the partially kerfed assembly 400 is rotated 90 and cut
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`US 6,784,023 B2
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`in the transverse direction (see broken lines on FIG. 4) with
`parallel saw cuts, again as known in the art for cutting Single
`wafers.
`After the pairs of dice or wafer portions are cut and
`removed from the adhesive film by a pick-and-place appa
`ratus or other known apparatus in the art, they may be
`attached to a Substrate or printed circuit board. At least one
`Side of the dice pair will preferably have an array of minute
`solder balls or other conductive elements (BGA or SLICC)
`or an array of small pins (PGA) disposed thereon for
`face-down attachment and electrical communication of the
`die to at least one Substrate, again Such as a PCB or
`leadframe.
`The die Surface which is opposite to the die Surface being
`attached to the Substrate can be used to align the dice pair.
`AS noted previously, the alignment technique allows the dice
`pair to be placed within plus or minus 0.0002-0.0003 inch
`of the desired location.
`FIG. 6 illustrates an exemplary die assembly 600 of the
`present invention. The assembly 600 comprises an upper die
`602 and an opposing lower die 604 which is connected to a
`leadframe or other Substrate 606. Fabrication of the assem
`bly 600 comprises providing the lower die 604 having a face
`surface 608 with at least one flip-chip electric connection
`610 (such as a C4 solder bump connection, conductive
`polymer bump or pin connection, these and other alterna
`tives being known in the art, by way of example) extending
`from a bond pad or other terminal 612 on the lower die face
`surface 608. Aback side 622 of the upper die 602 is adhered
`to the lower die 604 with a layer of adhesive 618 applied
`over a lower die back side 620, as previously described. An
`adhesive requiring a curing Step, Such as an epoxy, is
`preferred, although many adhesives (thermoplastic, contact,
`etc.) known in the art are Suitable.
`The flip-chip electric connections 610 are then made to a
`Surface 614 of the Substrate 606 in Such a manner that the
`flip-chip electric connections 610 provide both mechanical
`Securement and electrical contact with lead ends, trace ends,
`terminals or other electrical contact elements 616 in or on
`the Surface 614 of the Substrate 606.
`A face side 624 of the upper die 602 has a plurality of
`bond pads 626 disposed thereon. A plurality of exemplary
`gold or aluminum bond wires 628 is shown attached
`between the upper die bond pads 626 and corresponding
`trace or lead ends or other terminals 630 on the upper surface
`614 of the Substrate 606.
`Preferably, a sealing (underfill) compound 632 as known
`in the art is disposed between the lower die 604 and the
`substrate 606 (if solid rather than a leadframe) to prevent
`contamination of the flip-chip electric connections 610 and
`to more firmly secure the lower die 604 to the Substrate 606.
`A glob top 634 may be applied over assembly 600
`individually, as shown in broken lines, or over the entire
`substrate 606, which may support a plurality of assemblies
`600. The subsequently-described embodiments may simi
`larly be glob-topped, as desired. If substrate 606 is a
`leadframe, the assembly may be packaged in molded plastic
`or a preformed ceramic or metal package.
`Substrate 606, if an insulative substrate, may itself be
`connected to a chassis or mother board by edge connections,
`bump connections, pin connections, or other conductive
`arrangements as known in the art. If substrate 606 is a
`leadframe, the outer lead ends may engage a higher-level
`package as known in the art.
`FIG. 7 illustrates a side plan view of alternative die
`assembly 700 of the present invention. FIG. 7 shows a TAB
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`attachment assembly rather than the wirebonding shown in
`FIG. 6. The alternate die assembly 700 is similar instructure
`to the die assembly 600 of FIG. 6; therefore, components
`common to both FIG. 6 and FIG. 7 retain the same numeric
`designation. A plurality of traces 704 on dielectric TAB films
`702 is attached between the upper die bond pads 626 and
`corresponding trace or lead ends or other terminals 630 on
`the upper surface 614 of the Substrate 606. It may be
`desirable to employ a heat sink member 912 between the
`upper die 602 and the lower die 604, either embedded in the
`adhesive or located between two adhesive layers, to promote
`heat transfer from the upper die 602 and the lower die 604.
`FIG. 8 illustrates a side plan view of another alternative
`die assembly 800 of the present invention. FIG. 8 shows the
`use of a pair of Substrates Such as printed circuit boards or
`leadframes (or two parts of a two-part leadframe) for elec
`trical connection of the adhered dice pair. The die assembly
`800 is similar in Structure to the die assemblies 600 and 700
`of FIGS. 6 and 7, respectively. Therefore, components
`common between FIGS. 6, 7, and 8 retain the same numeric
`designation. The upper die 602 has at least one flip-chip
`electric connection 802 on the upper die face surface 624
`which extends from a bond pad or other terminal 804 on the
`upper die face Surface 624. The flip-chip electric connec
`tions 802 extend to a Surface 806 of a Substrate 808 in Such
`a manner that the flip-chip electric connections 802 physi
`cally (mechanically) attach to, and make electrical contact
`with lead ends, trace ends, terminals or other electrical
`contact elements 810 in or on the Surface 806 of the Substrate
`808.
`FIG. 9 depicts yet another alternative embodiment 900 of
`the present invention comprising a die, partial wafer or
`wafer stack comprising first and Second semiconductor
`substrates 902 and 904, each having bond pads 906 thereon
`communicating with integrated circuitry on each respective
`substrate. Unlike the previous embodim