(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0054140 A1
`(43) Pub. Date:
`Mar. 10, 2005
`Kim et al.
`
`US 2005.0054140A1
`
`(54) APPARATUS FOR STACKING
`SEMICONDUCTOR CHIPS, METHOD FOR
`MANUFACTURING SEMCONDUCTOR
`PACKAGE USING THE SAME AND
`SEMCONDUCTOR PACKAGE
`MANUFACTURED THEREBY
`(75) Inventors: Min-Ill Kim, Gyeonggi-do (KR);
`Dong-Kuk Kim, Gyeonggi-do (KR);
`Chang-Cheol Lee,
`Chungcheongnam-do (KR); Tae-Hoe
`Hwang, Chungcheongnam-do (KR);
`Jae-Young Hong, Chungcheongnam-do
`(KR)
`Correspondence Address:
`MARGER JOHNSON & McCOLLOM, P.C.
`1030 S.W. Morrison Street
`Portland, OR 97205 (US)
`(73) Assignee: Samsung Electronics Co., Ltd., Suwon
`City (KR)
`(21) Appl. No.:
`10/916,094
`(22) Filed:
`Aug. 10, 2004
`(30)
`Foreign Application Priority Data
`
`Sep. 9, 2003 (KR)....................................... 2003-63132
`
`Publication Classification
`
`51) Int. Cl."
`nt. Cl. ..........................
`
`H01L 21/66; GO1R 31/26
`HO1L 21/44; HO1L 21/48;
`H01L 21/50; H01L 23/34
`(52) U.S. Cl. ............................................ 438/109; 257/724
`
`(57)
`
`ABSTRACT
`
`The present invention relates to an apparatus for Stacking
`Semiconductor chips, a method for manufacturing a Semi
`conductor package using the same and a Semiconductor
`package manufactured thereby. The apparatus for Stacking
`Semiconductor chips may comprise two tables for Support
`ing wafers, a picker for picking up Semiconductor chips and
`a picker transfer unit for moving the picker vertically and
`horizontally. The method for manufacturing a Semiconduc
`tor package using the same may allow easy and rapid
`Stacking of Semiconductor chips, thereby improving the
`productivity of Semiconductor package manufacture. Fur
`ther, a Semiconductor chip having a relatively thick film is
`attached onto another Semiconductor chip having a rela
`tively thin film. The thicker semiconductor chip may protect
`the thinner Semiconductor chip from faults Such as chipping
`or warpage which may occur due to external shockS Such as
`that caused by a picker, thereby improving the reliability of
`the package.
`
`
`
`f I Hith
`
`241.
`
`SAMSUNG EXHIBIT 1013
`Samsung v. Trenchant
`Case IPR2021-00258
`
`

`

`Patent Application Publication Mar. 10, 2005 Sheet 1 of 7
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`US 2005/0054140 A1
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`Patent Application Publication Mar. 10, 2005 Sheet 2 of 7
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`US 2005/0054140 A1
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`O
`CN
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`Patent Application Publication Mar. 10, 2005 Sheet 3 of 7
`FIG. 3a
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`US 2005/0054140 A1
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`Patent Application Publication Mar. 10, 2005 Sheet 4 of 7
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`US 2005/0054140 A1
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`FIG. 3C
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`
`
`FIG. 3d
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`

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`Patent Application Publication Mar. 10, 2005 Sheet 5 of 7
`FIG. 3e
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`US 2005/0054140 A1
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`
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`FIG. 4
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`

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`Patent Application Publication Mar. 10, 2005 Sheet 6 of 7
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`US 2005/0054140 A1
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`FIG. 5
`
`First table
`
`First Wafer
`
`".
`First
`semiconductor :
`chip
`...:
`Dual chip
`
`8 o a g o O U
`
`a e g g g o p a s a
`
`a a a
`
`Third Wafer
`
`d is a
`
`A P. a. A 9
`
`h
`
`P A
`
`a h is a A a
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`Fifth Wafer
`
`a e o u Po a
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`e. e. e. e o e o s v e o a o o a u fle
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`"n"th Wafer
`
`a . .
`
`.
`
`.
`
`multi-chip
`nply
`
`.
`
`.
`
`.
`
`.
`
`.
`.
`w a
`
`.
`
`e s
`.
`as a 8 e o is s a s e o
`
`0
`
`a
`
`8
`
`u v e o p - a v. e. e. e. e o 0 8 e s a e o e o o so a e
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`
`
`
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`Patent Application Publication Mar. 10, 2005 Sheet 7 Of 7
`FIG. 6
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`US 2005/0054140 A1
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`100
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`

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`US 2005/0054140 A1
`
`Mar. 10, 2005
`
`APPARATUS FOR STACKING SEMCONDUCTOR
`CHIPS, METHOD FOR MANUFACTURING
`SEMCONDUCTOR PACKAGE USING THE SAME
`AND SEMCONDUCTOR PACKAGE
`MANUFACTURED THEREBY
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`0001. This U.S. non-provisional application claims pri
`ority under 35 U.S.C. S 119 to Korean Patent Application No.
`2003-63132 filed Sep. 9, 2003, the contents of which are
`incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`0002) 1. Field of the Invention
`0003. The present invention relates to an apparatus for
`Stacking Semiconductor chips, a method for manufacturing
`a Semiconductor package using the same and a Semiconduc
`tor package manufactured thereby.
`0004 2. Description of the Related Art
`0005 The recent trend towards miniaturization of elec
`tronic equipment requires high integration density on Semi
`conductor packages. One of the methods for manufacturing
`high integration density Semiconductor packages involves
`Stacking Semiconductor chips.
`0006 Referring to FIG. 1, the conventional apparatus for
`Stacking Semiconductor chips 10 comprises a table 11, a
`wafer transfer unit 16, a picker 13 and a picker transfer unit
`15. The table 11 may be configured to support a first wafer
`W1 including a plurality of first semiconductor chips 1 and
`a Second wafer W2 including a plurality of Second Semi
`conductor chips 2. The wafer transfer unit 16 may be
`configured to transfer the first and second wafers W1 and
`W2 to/from the table 11. The picker 13 may be configured
`to pick up the first Semiconductor chip 1. The picker transfer
`unit 15 may transfer the picker 13.
`0007. The first wafer W1 is loaded on the table 11. The
`picker 13 picks up one first Semiconductor chip 1 of the first
`wafer W1. The first wafer W1 is then unloaded from the
`table 11. The second wafer W2 is loaded on the table 11. The
`first Semiconductor chip 1 is die-attached on one Second
`semiconductor chip 2 of the second wafer W2. The overall
`StepS are repeated So the plurality of first Semiconductor
`chips 1 vertically Stack on the plurality of Second Semicon
`ductor chips 2.
`0008. The conventional apparatus for stacking semicon
`ductor chips has disadvantages of loading/unloading the
`wafers on/from the wafer table for every stack of the
`Semiconductor chips, thereby increasing the operation time
`and reducing the productivity of the Semiconductor manu
`facturing process.
`0009 Further, when thin semiconductor chips are picked
`up or die-attached using the vacuum absorption of the
`picker, faults Such as chipping or warpage may occur on the
`Semiconductor chips, leading to the reduced reliability of a
`Semiconductor package.
`
`SUMMARY OF THE INVENTION
`0.010 The present invention is directed to an improved
`apparatus for Stacking Semiconductor chips, a method for
`
`manufacturing a Semiconductor package using the same and
`a Semiconductor package manufactured thereby.
`0011. An apparatus for Stacking Semiconductor chips
`may comprise a first table, a picker, a picker transfer unit and
`a Second table. The first table may be configured to Support
`a first wafer including a plurality of first Semiconductor
`chips. The picker may be configured to pick up the first
`Semiconductor chip. The picker transfer unit may be con
`figured to transfer the picker. The Second table may be
`configured to Support a Second wafer including a plurality of
`Second Semiconductor chips and may be spaced apart from
`the first table.
`0012. The picker transfer unit may move the picker
`horizontally between the first table and the second table and
`move the picker Vertically above each table.
`0013 The apparatus for stacking semiconductor chips
`may further comprise a first wafer transfer unit transferring
`the first wafer to/from the first table and a second wafer
`transfer unit transferring the Second wafer to/from the Sec
`ond table.
`0014.
`In accordance with an exemplary embodiment of
`the present invention, a method for manufacturing a Semi
`conductor package may comprise providing a first wafer
`including a plurality of first Semiconductor chips and a
`Second wafer including a plurality of Second Semiconductor
`chips. The first and Second waferS have first and Second
`adhesive layers formed on the bottom Surfaces thereof,
`respectively. The first wafer is loaded on the first table and
`the Second wafer is loaded on the Second table Spaced apart
`from the first table. A first semiconductor chip of the first
`wafer is picked up by the picker and is die-attached on a
`Second Semiconductor chip of the Second wafer. The die
`attaching Step repeats to Vertical Stack a plurality of multi
`chips. A first remainder of the first wafer is unloaded from
`the first table and a Substrate panel including a plurality of
`substrates is then loaded on the first table. The dual chip is
`picked up by the picker and is die-attached on the Substrate.
`The dual chip may be wire-bonded to the substrate for
`interconnection. Solder balls may be formed on the bottom
`Surface of the Substrate. The Substrate panel is Singulated.
`0015 The first semiconductor chip has a first chip height
`and a first chip area, or a first active Surface area. The Second
`Semiconductor chip has a Second chip height and a Second
`chip area, or a Second active Surface area. A first ratio of the
`first chip area to the first chip height may be Smaller than or
`the same as a Second ratio of the Second chip area to the
`Second chip height.
`0016. The first chip height may be larger than the second
`chip height and the first chip area may be Smaller than the
`Second chip area.
`0017. The first ratio may be between 100 mm and 1,000
`mm and the second ratio may be between 1,000 mm and
`5,000 mm.
`0018. In accordance with another exemplary embodiment
`of the present invention, a method for manufacturing a
`Semiconductor package may comprise providing a first
`wafer including a plurality of first Semiconductor chips and
`a Second wafer including a plurality of Second Semiconduc
`tor chips. The first and Second wafers have first and Second
`adhesive layers formed on the bottom surfaces thereof,
`
`

`

`US 2005/0054140 A1
`
`Mar. 10, 2005
`
`respectively. The first wafer is loaded on the first table and
`the second wafer is loaded on the second table. A first
`Semiconductor chip of the first wafer is picked up by the
`picker and is die-attached on a Second Semiconductor chip of
`the Second wafer. The first chip die-attaching Step is repeated
`to form a plurality of dual chips configured in a vertical
`stack. A first remainder of the first wafer is unloaded from
`the first table and a third wafer including a plurality of third
`semiconductor chips is then loaded on the first table. The
`third wafer has a third adhesive layer formed on the bottom
`Surface thereof. The dual chip is picked up by the picker and
`is die-attached on a third Semiconductor chip of the third
`wafer. The dual chip die-attaching Step is repeated to verti
`cally Stack a plurality of triple chips. A Second remainder of
`the dual chip is unloaded from the second table. The above
`overall Steps are repeated to form multi-chips. A Substrate
`panel including a plurality of Substrates is loaded on any
`table where the multi-chips are not loaded. The multi-chip is
`picked up by the picker and is die-attached on the Substrate.
`The multi-chip is wire-bonded to the substrate for intercon
`nection. Solder balls are formed on the bottom Surface of the
`Substrate. The Substrate panel is singulated.
`0019. The upper semiconductor chip has a third chip
`height and a third chip area, or a third active Surface area and
`the lower Semiconductor chip has a fourth chip height and a
`fourth chip area, or a fourth active Surface area, when two
`adjacent Semiconductor chips are Selected from the multi
`chip. A third ratio of the third chip area to the third chip
`height may be Smaller than or the same as a fourth ratio of
`the fourth chip area to the fourth chip height.
`0020. The third chip area may be smaller than the fourth
`chip area.
`0021. In accordance with still another exemplary
`embodiment of the present invention, a method for manu
`facturing a Semiconductor package may comprise providing
`a first interposer panel including a plurality of interposers
`and a first wafer including a plurality of first Semiconductor
`chips. The first interposer panel and the first wafer have first
`and Second adhesive layerS formed on the bottom Surfaces
`thereof, respectively. The first interposer panel may be
`loaded on the first table and the first wafer may be loaded on
`the second table. The first table may be spaced apart from the
`Second table. A first interposer of the first interposer, panel
`may be picked up by the picker and may be die-attached on
`a first semiconductor chip of the first wafer. The first
`interposer die-attaching Step may be repetitively performed
`to form at least one first Semiconductor chip Set having a
`Vertical Stack configuration. The first interposer panel may
`be unloaded from the first table and a substrate panel
`including a plurality of Substrates may be then loaded on the
`first table. The first Semiconductor chip Set may be picked up
`by the picker and may be die-attached on the substrate. The
`substrate panel may be unloaded from the first table and the
`remainder of the first Semiconductor chip Set may be
`unloaded from the Second table. A Second Semiconductor
`chip Set may be formed through the same Steps as the first
`Semiconductor chip Set. A Second Semiconductor chip may
`be the same as the first Semiconductor chip and a Second
`interposer may be the same as the first interposer. The first
`semiconductor chip may be wire-bonded to the substrate for
`interconnection. The Second Semiconductor chip Set may be
`die-attached on the first Semiconductor chip Set. A Second
`Semiconductor chip of the Second Semiconductor chip Set
`
`may be wire-bonded to the Substrate for interconnection. A
`third Semiconductor chip being the same as the Second
`Semiconductor chip may be die-attached on the Second
`Semiconductor chip Set. The third Semiconductor chip may
`be wire-bonded to the Substrate for interconnection. Solder
`balls may then be formed on the bottom surface of the
`Substrate. The Substrate panel is singulated.
`0022 A Semiconductor package may comprise a first
`Semiconductor chip, a Second Semiconductor chip Set
`including at least one Semiconductor chip, a Substrate having
`the Second Semiconductor chip Set attached on the top
`Surface thereof, Solder balls formed on the bottom Surface of
`the Substrate and bonding wires electrically connecting the
`first Semiconductor chip and a Second Semiconductor chip of
`the Second Semiconductor chip Set to the Substrate. The first
`Semiconductor chip can have a first chip height and a first
`chip area, or a first active Surface area. The Second Semi
`conductor chip can have a Second chip height and a Second
`chip area, or a Second active Surface area. A first ratio of the
`first chip area to the first chip height may be Smaller than a
`Second ratio of the Second chip area to the Second chip
`height.
`0023 The first ratio may be between 100 mm and 1,000
`mm and the second ratio may be between 1,000 mm and
`5,000 mm.
`0024. The first chip height may be larger than the second
`chip height.
`BRIEF DESCRIPTION OF THE DRAWINGS
`0025 These and other objects, features and advantages of
`the present invention will be readily understood with refer
`ence to the following detailed description thereof provided
`in conjunction with the accompanying drawings, wherein
`like reference numerals designate like Structural elements,
`and in which:
`0026 FIG. 1 is a schematic perspective view of a con
`ventional apparatus for Stacking Semiconductor chips,
`0027 FIG. 2 is a schematic perspective view of an
`apparatus for Stacking Semiconductor chips in accordance
`with an exemplary embodiment of the present invention;
`0028 FIGS. 3a through 3e are cross-sectional views of a
`method for manufacturing a Semiconductor package using
`the apparatus for Stacking Semiconductor chips in accor
`dance with an exemplary embodiment of the present inven
`tion;
`0029 FIG. 4 is a perspective view illustrating the stack
`ing of Semiconductor chips,
`0030 FIG. 5 is a schematic diagram illustrating the
`Stacking of a plurality of Semiconductor chips,
`0031
`FIG. 6 is a cross-sectional view of a semiconductor
`package in accordance with another exemplary embodiment
`of the present invention; and
`0032 FIG. 7 is a cross-sectional view of a semiconductor
`package in accordance with Still another exemplary embodi
`ment of the present invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`0033 Exemplary embodiments of the present invention
`will be described below with reference to the accompanying
`drawings.
`
`

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`US 2005/0054140 A1
`
`Mar. 10, 2005
`
`0034) Referring to FIG. 2, the apparatus for stacking
`Semiconductor chips comprises a first table 21 and a Second
`table 22, a first wafer transfer unit 26 and a second wafer
`transfer unit 27, a picker 23 and a picker transfer unit 25.
`0035) The first table 21 supports a first wafer W1 includ
`ing a plurality of first Semiconductor chipS 1. The Second
`table 22 Supports a Second wafer W2 including a plurality of
`Second Semiconductor chips2. The Second table 22 is spaced
`apart from the first table 21. The first wafer W1 and the
`second wafer W2 may be loaded on a first wafer support 21b
`and a Second wafer Support 22b, respectively.
`0.036 The first wafer transfer unit 26 loads/unloads the
`first wafer W1 on/from the first table 21. The second wafer
`transfer unit 27 loads/unloads the second wafer W2 on/from
`the second table 22. The first and second wafer transfer units
`26 and 27 may include a guide rail or an elevator device.
`0037. The picker 23 picks up a first semiconductor chip
`1. The picker 23 is Supported by a picker Support 24
`connected to the picker transfer unit 25. The picker 23 may
`include a vacuum absorption picker using vacuum pressure.
`0038. The picker transfer unit 25 transfers the picker 23
`between the first table 21 and the second table 22. In an
`embodiment the picker 23 may be transferred in a horizontal
`movement (H). The picker transfer unit 25 also transfers the
`picker 23 upward and downward over the first and second
`tables 21 and 22 in a vertical movement (V).
`0039 FIGS.3a through 3e are cross-sectional views of a
`method for manufacturing a Semiconductor package using
`the apparatus for Stacking Semiconductor chips in accor
`dance with an exemplary embodiment of the present inven
`tion.
`0040. A first wafer and a second wafer (W1 and W2 of
`FIG.2) are provided. The first wafer W1 includes a plurality
`of first semiconductor chips 1. The second wafer W2
`includes a plurality of Second Semiconductor chips 2. The
`first wafer W1 has a first adhesive layer (31 of FIG. 3a)
`formed on the lower Surface thereof and the second wafer
`W2 has a second adhesive layer (32 of FIG. 3b) formed on
`the lower surface thereof. A first adhesive tape (33 of FIG.
`3a) is formed on the bottom surface of the first adhesive
`layer 31. A second adhesive tape (34 of FIG. 3b) is formed
`on the bottom surface of the second adhesive layer 32.
`0041 As shown in FIG. 2, the first wafer W1 is moved
`in the direction H2 to be loaded on the first table 21. The
`Second wafer W2 is moved in the direction H1 to be loaded
`on the second table 22.
`0.042
`Referring to FIG. 3a, a first semiconductor chip 1
`of the first wafer W1 is picked up by the picker 23.
`0.043
`Referring to FIG. 3b, the first semiconductor chip
`1 is die-attached on a Second Semiconductor chip 2 by the
`picker 23. This step is repeated to form a plurality of
`multi-chips 42 having vertical Stack configurations. The
`multi-chips may be dual chips, triple chips, or any other
`multiple of Single chips.
`0044) Referring to FIG. 4, the first semiconductor chip 1
`may be an 8 mmx8 mmx100 um chip (lengthxwidth}xheight)
`and the Second Semiconductor chip 2 may be a 10 mmx10
`mmx30 um chip (lengthxwidth×height).
`
`0045 Referring back to FIG. 2, a first remainder (not
`shown) of the first wafer W1 is unloaded from the first table
`21. A substrate panel (35 of FIG. 3d) including a plurality
`of substrates (36 of FIG.3d) is then loaded on the first table
`21.
`0046 Referring to FIG. 3c, the multi-chip 42 is picked
`up by the picker 23.
`0047 Referring to FIG. 3d, the multi-chip 42 is then
`die-attached on the Substrate 36.
`0048 Referring to FIG. 3e, bonding wires 37 are
`attached between the multi-chip 42 and the substrate 36 to
`electrically connect the multi-chip 42 and the substrate 36.
`Solder balls 38 are formed on the bottom Surface of the
`substrate 36. The substrate panel (35 of FIG. 3d) is singu
`lated. An encapsulant 39 seals the top surface of the Sub
`strate 36, and the multi-chip 42 and the bonding wires 37. In
`this way, the manufacture of a Semiconductor package 30 is
`completed.
`0049. The first semiconductor chip 1 has a first chip
`height measured in a normal direction (P) and a first chip
`area, or a first active Surface (1a) area. The Second semi
`conductor chip 2 has a Second chip height measured in a
`normal direction (P) and a Second chip area, or a second
`active Surface (2.a) area.
`0050. A first ratio of the first chip area to the first chip
`height may be Smaller than or the same as a Second ratio of
`the Second chip area to the Second chip height.
`0051. The first height may be larger than the second
`height and the first chip area may be Smaller than the Second
`chip area. The first ratio may be between 100 mm and 1,000
`mm and the second ratio may be between 1,000 mm and
`5,000 mm.
`0052 Although this embodiment shows the multi-chips
`in which two Semiconductor chips are vertically Stacked,
`three Semiconductor chips or more may be vertically
`Stacked.
`0053) Referring to FIG. 5, a first wafer including a
`plurality of first Semiconductor chips is loaded on a first
`table. A Second wafer including a plurality of Second Semi
`conductor chips is loaded on a Second table. A first Semi
`conductor chip may be die-attached on a Second Semicon
`ductor chip to form a dual chip. A first remainder of the first
`wafer is unloaded from the first table. A third wafer includ
`ing a plurality of third Semiconductor chips is loaded on the
`first table. The dual chip is die-attached on a third semicon
`ductor chip to form a triple chip. A Second remainder of the
`Second wafer is unloaded from the second table. A fourth
`wafer including a plurality of fourth Semiconductor chips is
`loaded on the Second table. The triple chip is die-attached on
`a fourth Semiconductor chip to form a quadruple chip. In this
`way, a “n-1”th semiconductor chip of a “n-1”th wafer is
`die-attached on a “n'th Semiconductor chip to form a n-ply
`multi-chip. Here “n” is a natural number of two or more.
`Although FIG. 5 shows that the “n”th wafer including the
`“n”th semiconductor chip is loaded on the first table, the
`“n”th wafer including the “n”th semiconductor chip may be
`loaded on the Second table.
`0054 Accordingly, a method for manufacturing a semi
`conductor package using an apparatus for Stacking Semicon
`
`

`

`US 2005/0054140 A1
`
`Mar. 10, 2005
`
`ductor chips in accordance with the present invention may
`achieve easy and rapid Stacking of Semiconductor chips.
`0.055 The second semiconductor chip has a relatively
`thin film of about 30 lum, while the first semiconductor chip
`has a relatively thick film of about 100 um and a chip area
`sufficient to prevent faults from external shocks. The first
`Semiconductor chip may protect the Second Semiconductor
`chip from faults Such as chipping or warpage which may
`occur due to external shockS Such as that caused by a picker.
`0056 FIG. 6 is a cross-sectional view of a semiconductor
`package in accordance with another exemplary embodiment
`of the present invention.
`0057 Referring to FIG. 6, a semiconductor package 100
`has a Same-die Stack configuration. The Semiconductor
`package 100 comprises a first Semiconductor chip 113, a
`Second Semiconductor chip 123, a third Semiconductor chip
`133, a first interposer 111, a second interposer 121, a first
`bonding wire 151, a second bonding wire 152, a third
`bonding wire 153 and an encapsulant 160.
`0.058 A substrate 140 has solder balls 141 formed on the
`bottom Surface thereof. The first, second and third semicon
`ductor chips 113, 123 and 133 are stacked on the substrate
`140. The first, second and third semiconductor chips 113,
`123 and 133 have second, fourth and fifth adhesive layers
`114, 124 and 134 on the back surfaces thereof, respectively.
`The first, second and third semiconductor chips 113,123 and
`133 have substantially equal sizes. The first and second
`interposers 111 and 121 have first and third adhesive layers
`112 and 122 formed on the bottom surfaces thereof, respec
`tively. The first interposer 111 interposes between the first
`Semiconductor chip 113 and Second Semiconductor chip
`123. The second interposer 121 interposes between the
`Second Semiconductor chip 123 and third Semiconductor
`chip 133. The first, second and third bonding wires 151,152
`and 153 electrically connect the first, second and third
`semiconductor chips 113, 123 and 133 to the substrate 140,
`respectively. The encapsulant 160 seals the top surface of the
`Substrate 140, the first, second and third semiconductor
`chips 113, 123 and 133, and the first, second and third
`bonding wires 151, 152 and 153.
`0059 A first semiconductor chip set 110 comprises the
`first interposer 111 having the first adhesive layer 112, and
`the first semiconductor chip 113 having the second adhesive
`layer 114. A Second Semiconductor chip Set 120 comprises
`the Second interposer 121 having the third adhesive layer
`122, and the Second Semiconductor chip 123 having the
`fourth adhesive layer 124.
`0060 An exemplary method for manufacturing the semi
`conductor package 100 comprises loading a first interposer
`panel (not shown) on the first table (21 of FIG. 2). A first
`wafer (not shown) is loaded on the second table 22.
`0061 A first interposer 111 is picked up by the picker (23
`of FIG. 2) and is die-attached on a first semiconductor chip
`113 to form a first semiconductor chip set 110.
`0062) The first interposer panel is unloaded from the first
`table (21 of FIG. 2). The substrate panel (not shown)
`including the substrate 140 is loaded on the first table (21 of
`FIG. 2).
`0.063. The first semiconductor chip set 110 is picked up
`by the picker (23 of FIG. 2) and is die-attached on the
`Substrate 140.
`
`0064. The substrate panel is unloaded from the first table
`(21 of FIG. 2). The remainder of the first semiconductor
`chip set 110 is unloaded from the second table (22 of FIG.
`2).
`0065. The second semiconductor chip set 120 is formed
`through the same processes as the first Semiconductor chip
`Set 110. A second wafer is the same as the first wafer and a
`Second interposer 121 is the Same as the first interposer 111.
`0066. The first semiconductor chip 113 is electrically
`connected to the substrate 140 by a first bonding wire 151.
`0067. The second semiconductor chip set 120 is die
`attached on the first semiconductor chip set 110. At this time,
`the apparatus for stacking semiconductor chips (20 of FIG.
`2) may be used.
`0068 The second semiconductor chip 123 is electrically
`connected to the substrate 140 by a second bonding wire
`152.
`0069. A third semiconductor chip 133, similar to the
`Second Semiconductor chip, is die-attached on the Semicon
`ductor chip Set 120. The apparatus for Stacking Semicon
`ductor chips (20 of FIG. 2) may then be used.
`0070 The third semiconductor chip 133 is electrically
`connected to the substrate 140 by a third bonding wire 153.
`0071 Solder balls 140 are formed on the bottom surface
`of the substrate 140. An encapsulant 160 is formed. The
`Substrate panel is Singulated.
`0072 Although this embodiment shows that the semi
`conductor package 100 comprises three Semiconductor
`chipS and two interposers, the present invention may have
`variations in the number of Semiconductor chips and inter
`pOSerS.
`0073) Referring to FIG. 7, a semiconductor package 200
`comprises a Substrate 240, first to Seventh Semiconductor
`chips 211 to 217, first to seventh bonding wires 251 to 257
`and an encapsulant 260.
`0074 The substrate 240 has solder balls 241 formed on
`the bottom Surface thereof. The first to seventh semiconduc
`tor chips 211 to 217 are stacked on the substrate 240. The
`first semiconductor chip 211 may be a 8 mmx8 mmx100 um
`chip (lengthxwidth:xheight) and the Second semiconductor
`chip 212 may be a 10 mmx10 mmx30 um chip (lengthx
`width:xheight). The third to seventh semiconductor chips
`213 to 217 may all have equal thickness, but the upper
`Semiconductor chip may be Smaller in chip area than a lower
`semiconductor chip. The first to seventh bonding wires 251
`to 257 electrically connect the first to seventh semiconductor
`chips 211 to 217 to the substrate 240, respectively. The
`encapsulant 260 seals the top surface of the substrate 240,
`the first to seventh semiconductor chips 211 to 217 and the
`first to seventh bonding wires 251 to 257.
`0075) When two adjacent semiconductor chips are
`selected from the first to seventh semiconductor chips 211 to
`217, the upper Semiconductor chip has a first chip height and
`a first chip area and the lower Semiconductor chip has a
`Second chip height and a Second chip area. A first ratio of the
`first chip area to the first chip height may be Smaller than a
`Second ratio of the Second chip area to the Second chip
`height. Specifically, the first Semiconductor chip 211 is a 8
`mmx8 mmx100 um chip (lengthxwidthxheight) and the
`
`

`

`US 2005/0054140 A1
`
`Mar. 10, 2005
`
`second semiconductor chip 212 is a 10 mmx10 mmx30 um
`chip (lengthxwidth:xheight). The first ratio is 640 mm and
`the second ratio is about 3,333 mm. Therefore, the first ratio
`is Smaller than the Second ratio.
`0076) The first ratio may be between 100 mm and 1,000
`mm and the second ratio may be between 1,000 mm and
`5,000 mm. The upper semiconductor chip may be thicker
`than the lower Semiconductor chip.
`0077. In accordance with the present invention, an appa
`ratus for Stacking Semiconductor chips may comprise two
`tables Supporting wafers, a picker picking up Semiconductor
`chips and a picker transfer unit moving the picker vertically
`and horizontally. A method for manufacturing a Semicon
`ductor package using Such an apparatus for Stacking Semi
`conductor chips may allow easy and rapid Stacking of
`Semiconductor chips, thereby improving the productivity of
`Semiconductor package manufacture.
`0078. Further, a semiconductor chip having a relatively
`thick film is die-attached on another Semiconductor chip
`having a relatively thin film. The thicker Semiconductor chip
`may protect the thinner Semiconductor chip from faults. Such
`as chipping or Warpage which may occur due to external
`ShockS Such as that caused by a picker, thereby improving
`the reliability of the package.
`0079 Although the exemplary embodiments of the
`present invention have been described in detail, it should be
`understood that many variations and/or modifications of the
`basic inventive concepts herein taught, which may appear to
`those skilled in the art, will still fall within the spirit and
`Scope of the present invention as defined in the appended
`claims.
`
`What is claimed is:
`1. An apparatus for Stacking Semiconductor chips, the
`apparatus comprising:
`a first table to Support a first wafer including a plurality of
`first Semiconductor chips,
`a picker to pick up a first Semiconductor chip;
`a picker transfer unit to move the picker; and
`a Second table to Support a Second wafer including a
`plurality of Second Semiconductor chips.
`2. The apparatus of claim 1, wherein the picker transfer
`unit can horizontally move the picker between the first table
`and Second table.
`3. The apparatus of claim 1, further comprising:
`a first wafer transfer unit to load the first wafer on the first
`table; and
`a Second wafer transfer unit to load the Second wafer on
`the second table.
`4. A method for manufacturing a Semiconductor package,
`the method comprising:
`providing a first wafer and a Second wafer, the first wafer
`having a first adhesive layer on a bottom Surface
`thereof and including a plurality of first Semiconductor
`chips, the Second wafer having a Second adhesive layer
`on a bottom Surface thereof and including a plurality of
`Second Semiconductor chips,
`loading the first wafer on a first table and the second wafer
`on a Second table;
`
`picking up a first Semiconductor chip and attaching the
`first Semiconductor chip onto a Second Semiconductor
`chip;
`repeating the attachment of the first Semiconductor chips
`to form a plurality of multi-chips having a vertical Stack
`configuration;
`unloading a first remainder of the first wafer from the first
`table and loading a Substrate panel including a plurality
`of Substrates on the first table;
`picking up the multi-chip and die-attaching the multi-chip
`on the Substrate;
`wire-bonding the multi-chip to the Substrate for intercon
`nection, forming Solder balls on the bott