`
`
`
`
`5:
`PATENT APPLICATION
`2 mswm
`
`Only for new nonprovisionai applications under .1? CFR 1.53“»)
`3
`
`
`
`APPLICATION ELEMENTS
`“
`.
`‘
`SeeMPEPchansrBOOconcemin
`
`
`
`Fee Transmittai Form (e.g..PTOlSBi17}
`
`(Submit an original and a duplicate for fee processing)
`
`
`
`2_ UpAppllcant claims small entity statue.
`9- El Assignment Papers (cover sheet 8. document(s)}
`See 37 CFR ‘I .27.
`
`
`
`20
`3.
`Specification
`[Total Page:
`Name of Aseignee
`
`
`
`Both the cialrne and abstract must start on a new page
`
`
`(For interruption on the preferred anengernent. see ”PEP 6011 title);
`
`4_ E Drawingis)(35U.S.C.113)
`[TotaiSheets 5
`1
`5. Oath or Declaration
`[Total Sheets
`g
`a. El Newly executed (original or copy)
`
`
`
`
`
`
`
`
`
`
`
`
`]
`
`]
`
`
`
`
`
`10. [:l 37 CFR 3.73leStatement
`[:| Power or
`
`{Mien there is an assigned)
`Attorney
`11. I:I English Translation Document (if applicable}
`
`
`12. E Information Disclosure Statement {PTo'seioa or Pro-1449}
`
`
`|:| Copies of foreign patent documents.
`puglications & other iniormation
`
`13. El Preliminary Amendment
`
`
`14
`Return Receipt Postcard {MPEP 503)
`
`
`'
`(Should be specificaih/ itemized)
`
`
`
`15.
`Certified Copy of Priority Documentls}
`[if foreign priority is claimed)
`
`
`
`
`15_ D Nonpubllcatlon Request under 35 U.S.C.122{h}(2)(B){I}.
`
`
`Applicant must attach form PTOlSBi35 or equivalent.
`
`
`
`
`17. D Other:
`
`
`
`bI:I A °°9Y from a poor application I37 CFR 1 63 Id”
`{for oontinuetionfdivisional with Box 18 completed)
`l. [:l DELETION OF INVENTORiS}
`Signed statement attached deleting Inventorte}
`name in the prior application. see 3? CFR
`133(c)(2) and 1.3mm.
`
`5, El Application Data Sheet. See 37 CFR 1.76
`7 I] CD-ROM or CD—R'II"I duplicate. large table or
`'
`Computer Program (Appendix)
`
`[:1 Landscape Table on CD
`Nucleotide andtor Amino Acid Sequence Submission
`(if applicable, Items 3. — c. are required)
`
`a. Computer Readable Form (CRF)
`
`i. B Computer Readable Form (CRF)
`
`Transfer Request (37 CFR 1.821(e))
`
`Specification Sequence Listing on:
`i.
`CD-ROM or CD-R (2 copies); or
`
`II
`
`Paper
`
`b.
`
`PTOlSBiOS {0545
`Approved for use throu h 0?i31l2003 OMB 0651 4103
`US. Petenl and Trademark 011th U S EPARTMENT OF COMMERCE
`
`-reorie are r- uired to res- -nd to a collection ofintermation unless it die-la = a valid 0 5:541 i- .L ..n r.
`
`§
`
`UTILITY
`
`£06080
`
`
`
`Express Mail Label ND.
`
`EW2?616815US
`
`ADDRESS T0:
`
`Commieeloner for Patents
`Po. Box 1450
`Alexandria. VA 22313-1450
`
`ACCOMPANYING APPLICATION PARTS
`
`
`
`
`
`
`
`
`c. [:I Statements verifying identity of above copies
`
`
`If a CONTINUING APPLICATION check appropriate box, and supply the requisite intonnelion below and in the first sentence
`18.
`citication following the title or in an Application Data Sheet under 3? CFR 1. 76:
`of the s
`Cmiinuetion
`[:I Divisional
`|:| Continuation—impart (CIP)
`ofpriorapplioaiion Na:
`
`WSW” inmbbfl: Examiner
`M Unil-
`
`
`
`'
`
`19. CORRESPONDENCE ADDRESS
`
`El The address associated with customer rim-rm
`
`43859
`
`OR I: Correspondence address below
`
`m Slater& Matsil. L.L.P.
`17950 Preston Rd., Suite 1000
`
`‘Ruojien ’dng
`
`75252-5793
`
`Email Address
`
`slater@slater—malsil.com
`
`
`
`
`
`
`
`__— 972-732-1001
`WI”:—
`pm
`NorrieI
`This collection of Inlermationis required by 3? CFR 1.5331). The inionnatlon'is required to obtain or retain a benefit by the public whim is to tile (and by the
`USPTO to process} an application. Confidentiality is governed by 35 1.1.8.0. 122 and 3? CFR 1.11 and 1.14. This collection Is estimated to take 12 minutes
`to complete. including gathering. preparing, and submitting the completed application form to the USPTO. Time will vary depending upon the individual
`case. Any comments on the amount of time you require to complete this form andlor suggestions for reducing this burden. should be sent to the Chief
`information Officer. US. Patent and Tredernanr. Office. U.S. Department of Commerce. PO. Box 1450. Alexandria, VA 22313-1450. DO NOT SEND FEES
`OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commleeioner for Patents. P.O. Box 1450. Alexandria. VA 22313-1450.
`inrou need assistance in completing the forth. cal! 1-800-PTO-9199 and select option 2.
`1
`SAMSUNG EXHIBIT 1012
`1
`SAMSUNG EXHIBIT 1012
`Samsung v. Trenchant
`Samsung v. Trenchant
`Case |PR2021-00258
`Case IPR2021-00258
`
`

`

`PTOISBH T (12-04}
`llllllllll
`Approved for use through 07131t2000. 0MB 0051-0032
`01980
`U.S. Patent and Trademark Office: US. DEPARTMENT OF COMMERCE
`
`-uiredtorsa--mtoaoollemionofinformalion unless iid -:
`-elralid OMBconlrol number.
`Underli'leP -n~olkReductionAetof1995. no -rsonsare
`
`
`
`
`
`C
`Efisctive on 1mm.
`
`
`
`we pursuant to the Consolidated Appropriations Act. 2005 (HR 4818}.
`
`
`
`For FY 2005
`
`
`
`
`
`
`
`
`
`
`TSMOS—OSIIB
`
`
`
`
`
`osFEE TRANSM'TTAL
`
`alt—moral
`
`-
`
`TOTAL AMOUNT OF PAYMENT
`
`
`
`(fl
`
`1 £00.00
`
`Attomey Docket No.
`
`METHOD or PAYMENT diedt all that a on
`
`
`
`|:| omarplmsoidmfiry):
`El Check CI CmditCard E] Money on: |:] None
`Deposit Account Name: Sfir 8. Mi} LLP.
`El Deposit Account Deposit Amunt Number: 50-1065
`Forthe above-identified deposit account. the Director is hereby authorized to:
`cried-r all that apply)
`El Charge feats) indicated below
`Charges feelsiind‘mtad below.exceptforthsiilingfeo
`
`m Chal'geanyaddilionalfee(s)crunderpaments oilee(s}
`Creditarly overpayment
`
`onder37CFR1.16and1.17
`.
`mamas: Wonmlshxmmaybeoomepuhflc. Oedltoaldhlfarmationatultdnoteemciudedonwsm Provldoaedtteardinionnstionsnd
`Wanna-seas
`
`
`
`FEE CALCULATION
`
`
`
`
`
`1. BASIC FIIJNG. SEARCH. AND EXAMINATION FEES
`
`FILING FEES
`SEARCH FEES
`
`Sl'nall gong
`Small Englx'
`5921mm Foam Foam
`Feelfl
`Utility
`300
`150
`250
`
`Design
`200
`100
`50
`Plant
`200
`100
`l 50
`
`Reissue
`300
`150
`250
`Provisional
`200
`IOU
`0
`
`2. EXCESS CLAIM FEES
`mus
`.FGLDEG—cflm
`50
`Each claim over 20 or, for Reissues, each claim over 20 and more than in the original patient
`
`200
`Each independent claim over 3 or. for Reissues, each independent claim more than in the original patent
`360
`Multiple dependent claims
`
`meager W
`Eats!
`
`T_.._.._._.°|=3Claim
`musClal
`s 0.00
`Bali}
`Essialoalfl
`=
`$50.00
`at
`-2t.‘lorHP=
`15
`0
`
`
`
`HP=higimmrthdhfllchim—upaidh.dgleetarm20—fl— — $350.00
`0.00
`Im Clair-no
`Extra Claims
`Fee it]
`Fee Paid
`__ _ '
`
`
`3:
`- 3 or HP =
`2
`0
`$200.00
`s 0.00
`
` Hp=noeolmmormeoamm. ilgreeterlhana
`3. APPLICATION SIZE FEE
`
`
`Feeffl
`500
`100
`300
`500
`0
`
`=
`
`EXAMINATION FEES
`Small m
`Foam
`100
`65
`80
`300
`0
`
`Feefi}
`200
`130
`160
`600
`0
`
`Foosealnisl
`$1,000.00
`
`M
`$15.!
`25
`100
`I80
`
`'
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Ifthe specification and drawings exceed 100 sheets of paper, the application size fee due is $250 ($125 for small entity)
`for mil additional 50 sheets or fiaction dieiecf. See 35 use 41 (a)(i)(G) and 37 CFR 1.16(s).
`TotalSheets
`Exh-aSheeB
`Numberefeach additiorlaifiiiorfracflonthereof
`Feefi)
`-100=
`25
`0
`0
`(round uptoamOenwnber)
`x
`$250.00
`4. OTHER FEEiS)
`Non-English Specification,
`Other.
`
`r50:
`
`$130 fee (no small entity discount)
`
`=
`
`FeePaid
`s 0.00
`W
`
`
`
`
`
`
`
`
`
`
`
`
`SUBMITIEDBY
`
`
`-Wa”
`gfigfig‘fiflggnfi“
`54.595
`Telephone
`972-732—1001
`Nan-lo (Pm-mm)
`Ruojian 2 'ng _ Date
`March 9, 2007
`This collection of information is required by 3? CFR 1.130.
`‘i‘he Information is required to obtain or retain a benefit by the public which is to file {and by the
`USPTO to process} an application. Confidentiality is governed by 35 U.5.C. 122 and 3? CFR 1.14. This collection ls estimated to take 30 minutes to
`complete. including gathering. preparing. and submitting the completed application form to the USPTO. Time will vary depending upon the Individual case.
`Any comments on the amount at time you require to cornplete this form andtor suggestions for reducing this burden. should he sent to the Chief Information
`Officer. US. Patent and Trademark Oiflce. LLS. Department of Commerce. PO. Box 1450. Alexandria. VA 22313-1450. DO NOT SEND FEES OR
`COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents. P.O. Box 1650. Alexandria. VA 22313-1450.
`it you need assistance in completing the icon. call r-aOD-PTO-aiss and select option 2.
`
`2
`
`

`

`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicant:
`
`Hsu, er (:1.
`
`Docket No.: TSM06-0548
`
`Serial No.:
`
`TBD
`
`Art Unit:
`
`TED
`
`Filed:
`
`Herewith
`
`Examiner:
`
`TBD
`
`For:
`
`.
`
`Design Techniques for Stacking Identical Memory Dies
`
`Certificate of Mailing via Express Mail
`
`EXPRESS MAIL mailing label number: EV727616815US
`
`Date of Deposit:
`
`March 9, 2007
`
`I hereby certify that the following documents, which are enclosed, are being deposited
`with the United States Postal Service "Express Mail Post Office to Addressee" service
`under 37 CPR. § 1.10 on the date indicated above in an envelope addressed to:
`Commissioner for Patents, P. O. Box 1450, Alexandria, VA 22313-1450:
`
`Certificate of Mailing via Express Mail (1 page)
`Utility Patent Application Transmittal (1 page)
`Fee Transmittal (1 original and 1 copy)
`Complete Copy of Patent Application (25 pages), to include:
`Specification (20 pages)
`Formal Drawing sheets (5 pages)
`Declaratiou and Power of Attorney (2 pages)
`Information Disclosure Statement (1 page)
`Form PTOISBIOSA (1 page), citing 1 reference
`Return Postcard
`
`Respectfully submitted,
`
`ane M. Roberts
`
`Legal Assistant
`
`Slater & Matsil, L.L.P.
`
`17950 Preston Rd., Suite 1000
`
`Dallas, Texas 75252-5793
`Tel: 972-732-1001
`
`Fax: 972-732-9218
`
`3
`
`

`

`Design Techniques for Stacking Identical Memory Dies
`
`TECHNICAL FIELD
`
`[0001]
`
`This invention relates generally to integrated circuits, and more particular to
`
`manufacturing and packaging techniques for forming stacked memory dies.
`
`BACKGROUND
`
`[0002]
`
`Since the invention of integrated circuits, the semiconductor industry has
`
`experienced continuous rapid growth due to constant improvements in the integration density of
`
`various electronic components (i.e., transistors, diodes, resistors, capacitors, etc). For the most
`
`part, this improvement in integration density has come from repeated reductions in minimum
`
`feature size, which allow more components to be integrated into a given chip area.
`
`[0003]
`
`These integration improvements are essentially two-dimensional (2D) in nature, in
`
`that the volume occupied by the integrated components is essentially on the surface of the
`
`semiconductor wafer. Although dramatic improvement in lithography has resulted in
`
`considerable improvements in 2D integrated circuit formation, there are physical limitations to
`
`the density that can be achieved in two dimensions. One of these limitations is the minimum size
`
`needed to make these components. Also, when more devices are put into one chip, more complex
`
`designs are required.
`
`[0004]
`
`An additional limitation comes from the significant increase in the number and
`
`length of interconnections between devices as the number of devices increases. When the
`
`number and length of interconnections increase, both circuit RC delay and power consumption
`
`increase.
`
`TSM06-0548
`
`- l -
`
`4
`
`

`

`[0005]
`
`- Among the efforts for resolving the above-discussed limitations, three-dimensional
`
`integrated circuit (3 DIC) and stacked dies are commonly used. Through-silicon vias (TSV) are
`
`often used in 3DIC and stacked dies. Figure 1 illustrates a conventional semiconductor package
`
`including stacked dies, wherein TSVs 4 are formed in the dies. Dies 10 and 12 each comprise
`
`semiconductor substrate 2, on which integrated circuits (not shown) are formed. TSVs 4
`
`penetrate through semiconductor substrate 2, and are connected to the integrated circuits in the
`
`respective dies and bonding pads 6. Dies 10 and 12 are bonded through bonding pads 6. Further,
`
`bonding pads 6 of die 10 are used to connect die 10 to bumps 8, which are further connected to
`
`package substrate 14.
`
`[0006]
`
`Compared to the conventional wire-bonding, TSVs are more effective in connecting
`
`multiple dies. However, when used for stacking memory dies, TSVs suffer shortcomings.
`
`Typically, in the process for forming memory dies, it is preferred to have low inventory, short
`
`cycle time, low fabrication cost (which means only one mask set is preferred), and full sharing of
`
`inputfoutput (U0) pads. Therefore, it is preferred that memory dies 10 and 12 have exactly the
`
`same design, and can be fabricated using a same set of masks.
`
`[0007]
`
`Since memory dies need to have unique addresses in order to distinguish from each
`
`other, the identical memory dies cannot be simply stacked one on top of the other.
`
`Conventionally, different redistribution lines are formed for stacking dies. However, this method
`
`still needs different mask sets for forming the redistribution lines of the memory dies.
`
`Alternatively, interposers are designed. This way, the identical dies can be distinguished by
`
`attaching different interposers to dies, so that the memory dies and the attaching interposers in
`
`combination are distinguishable. Apparently, this method introduces extra cost for forming and
`
`attaching interposers.
`
`TSM06—0548
`
`- 2 -
`
`5
`
`

`

`[0008]
`
`Accordingly, what is needed in the art is a semiconductor structure and methods for
`
`forming the same that take advantage of stacked memory dies, while at the same time incurring
`
`as low cost as possible.
`
`TSM06-0548
`
`- 3 -
`
`6
`
`

`

`SUMMARY OF THE INVENTION
`
`[0009]
`
`In accordance with one aspect of the present invention, a semiconductor structure
`
`includes a first semiconductor die and a second semiconductor die identical to the first
`
`semiconductor die. The first semiconductor die includes a first identification circuit; and a first
`
`plurality of input/output (U0) pads on the surface of the first semiconductor die. The second
`
`semiconductor die includes a second identification circuit, wherein the first and the second
`
`identification circuits are programmed differently from each other; and a second plurality of U0
`
`pads on the surface of the second semiconductor die. Each of the first plurality of U0 pads is
`
`vertically aligned to and connected to one of the respective second plurality of 1/0 pads. The
`
`second semiconductor die is vertically aligned to and bonded on the first semiconductor die.
`
`[0010]
`
`In accordance with another aspect of the present invention, a semiconductor structure
`
`includes a first memory die and a second memory die. The first memory die includes a first
`
`identification circuit comprising at least one first programmable element; at least one first chip-
`
`select pad on a first side of the first memory die, wherein each of the at least one first chip-select
`
`pad is connected to one of the at least one first programmable elem ent; at least One second chip-
`
`select pad on a second side of the first memory die opposite the first side of the first memory die,
`
`wherein each of the at least one second chip-select pad is vertically aligned to and electrically
`
`connected to one of the at least one first chip-select pad through a through-silicon via; a first
`
`plurality of U0 pads on the first side of the first memory die; and a second plurality of DO pads
`
`on the second side of the first memory die, wherein each of the second plurality of U0 pads is
`
`vertically aligned to and electrically connected to one of the first plurality of I/O pads through a
`
`through-silicon via. The second memory die is identical to the first memory die. The second
`
`memory die includes a second identification circuit comprising at least one second
`
`TSM06-0548
`
`- 4 -
`7
`
`

`

`programmable element programmed difi'erently from the at least one first programmable
`
`element; at least one third chip-select pad on a first side of the second memory die, wherein each
`
`of the at least one third chip~select pad is connected to one of the at least one second
`
`programmable element; at least one fourth chip-select pad on a second side of the second
`
`memory die opposite the first side of the second memory die, wherein each of the at least one
`
`fourth chip-select pad is vertically aligned to and electrically connected to one of the at least one
`
`third chip-select pad through a through—silicon via; a third plurality of 1/0 pads on the first side of
`
`the second memory die; and a fourth plurality of U0 pads on the second side of the first memory
`
`die, wherein each of the fourth plurality of U0 pads is vertically aligied to and electrically
`
`connected to one of the third plurality of U0 pads through a through-silicon via, and wherein
`
`each of the fourth plurality of 1/0 pads is physically bonded to a respective pad in the first
`
`plurality of U0 pads.
`
`[0011]
`
`In accordance with yet another aspect of the present invention, a method of forming a
`
`semiconductor structure includes forming a first semiconductor die and a second semiconductor
`
`die identical to the first semiconductor die. Each of the first and the second semiconductor dies
`
`includes an identification circuit; and a plurality of U0 conductive paths connected to memory
`
`circuits in the respective first and second semiconductor dies, wherein the plurality of I/O
`
`conductive paths comprises through-silicon vias. The method further includes programming the
`
`identification circuit of the second semiconductor die to a different state from the identification
`
`circuit of the first semiconductor die; and bonding the second semiconductor die onto the first
`
`semiconductor die, wherein the first and the second semiconductor dies are vertically aligned,
`
`and wherein each of the plurality of U0 conductive paths in the first semiconductor die is
`
`connected to a respective 1/0 conductive path in the second semiconductor die.
`
`TSM06-0548
`
`- 5 -
`8
`8
`
`

`

`[0012]
`
`In accordance with yet another aspect of the present invention, a method of forming
`
`and Operating a semiconductor structure includes forming a first memory die and a second
`
`memory die identical to the first memory die, wherein each of the first and the second memory
`
`dies include an identification circuit; and a plurality of conductive paths connected to memory
`
`circuits and the identification circuit, wherein each of the conductive paths comprises a first and
`
`a second HO pads on opposite sides of the respective first and second memory dies, and wherein
`
`the first and the second U0 pads are vertically aligned. The method further includes
`
`programming the identification circuit of the first memory die; programming the identification
`
`circuit of the second memory die to a different state from the identification circuit of the first
`
`memory die; and stacking the second memory die onto the first memory die by physically
`
`bonding the second HO pads of the second memory die to the first L’O pads of the first memory
`
`die, wherein the first and the second memory dies are vertically aligned.
`
`{0013]
`
`The present invention provides ability for stacking identical dies without the need of
`
`redistribution lines andfor interposers. This significantly reduces the design and manufacturing
`
`cost, the inventory and cycle time.
`
`TSM06-0548
`
`_ 6 _
`9
`
`

`

`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0014]
`
`For a more complete understanding of the present invention, and the advantages
`
`thereof, reference is now made to the following descriptions taken in conjunction with the
`
`accompanying drawings, in which:
`
`[0015]
`
`Figure 1 illustrates a conventional structure including stacked dies;
`
`[0016]
`
`Figure 2 illustrates four identical memory dies;
`
`[0017]
`
`Figure 3 illustrates an exemplary decoding circuit for distinguishing dies, wherein the
`
`decoding circuit includes an AND gate;
`
`[0018]
`
`Figure 4 illustrates four identical memory dies with their identification circuits
`
`programmed differently; and
`
`[0019]
`
`Figure 5 illustrates the stacking of the identical memory dies.
`
`TSM06—0548
`
`_ 7 _
`10
`10
`
`

`

`DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
`
`[0020]
`
`The making and using of the presently preferred embodiments are discussed in detail
`
`below. It should be appreciated, however, that the present invention provides many applicable
`
`inventive concepts-that can be embodied in a wide variety of specific contexts. The specific
`
`embodiments discussed are merely illustrative of specific ways to make and use the invention,
`
`and do not limit the scope of the invention.
`
`[0021]
`
`In the following discussion, an embodiment for stacking four memory dies is
`
`provided for explaining the concept of the present invention. Figure 2 illustrates four identical
`
`dies, namely die 1, die 2, die 3 and die 4. Dies l, 2, 3 and 4 may include commonly used
`
`memories, such as static random access memory (SRAM), dynamic random access memory
`
`(DRAM), flash memory, magnetoresistive random access memory (MRAM), and the like. Dies
`
`1, 2, 3 and 4 may be dies sawed from a same semiconductor wafer, which includes a plurality of
`
`identical memory dies, or from different semiconductor wafers. Throughout the description, dies
`
`1, 2, 3 and 4 are equally referred to as memory dies 1, 2, 3 and 4, although they can be non—
`
`memory cells. Accordingly, the teaching provided by the present invention may be used for
`
`stacking identical non-memory dies.
`
`[0022]
`
`Each of dies 1, 2, 3, and 4 includes a substrate, on which integrated circuits (not
`
`shown) may be formed. A plurality of input/output (U0) pads P101 through PIOn is connected to
`
`the integrated circuits. In an exemplary embodiment, the integrated circuits include memory
`
`circuits. Accordingly, the plurality of IIO pads PIOI through PIOn may include a portion
`
`connected to the address lines (not shown), and a portion connected to the data lines. Preferably,
`
`each of the U0 pads P101 through PIOn is connected to a respective U0 pin P101_B through
`
`PlOn_B, which are on the opposite side of the die than the respective pads P101 through PIOn,
`
`TSM06-0548
`
`- g -
`11
`1 1
`
`

`

`through a through-silicon via (TSV). Further, each of the U0 pads P101 through PlOn is
`
`vertically aligned to the respective connecting U0 pads PIOl_B through PIOn_B.
`
`[0023]
`
`Each of dies 1, 2, 3 and 4 includes a programmable identification (ID) circuit
`
`(denoted as ID), which comprises at least one, and likely more, programmable elements. In an
`
`exemplary embodiment, the programmable elements are fuses, which may be either electrical
`
`fuses or laser fuses, and are denoted as F1, F2, F3 and F4 in Figure 2. Throughout the
`
`description, the programmable elements are equally referred to as fuses F1, F2, F3 and F4.
`
`However,'it is to be realized that the programmable elements may be other non-volatile devices,
`
`such as flash memories, providing they can be programmed after the fabrication of the dies.
`
`Typically, flash memories have higher fabrication costs than electrical fuses and laser fiises.
`
`However, if dies 1, 2, 3 and 4 comprise flash memories as part of the memory circuits, the
`
`programmable elements may be advantageously manufactured with no additional cost. Each of
`
`the programmable elements has a first end connected to a chip-select pad on one side of the
`
`respective die, wherein the chip-select pads connected to programmable elements F1, F2, F3, and
`
`F4 are denoted as Pl , P2, P3 and P4, respectively. On the opposite side of the die, chip-select
`
`pads P1_B, P2_B, P3_B and P4_B are formed, and are connected to the respective chip-select
`
`pads P1, P2, P3 and P4 through one of the TSVs. Preferably, chip—select pads P1_B, P2_B, P3_B
`
`and P4_B are vertically aligned to the connecting chip-select pads P1, P2, P3 and P4,
`
`respectively.
`
`[0024]
`
`The second ends of the programmable elements F1, F2, F3, and F4 are connected to a
`
`decoding circuit, wherein an exemplary decoding circuit is illustrated in Figure 3. The decoding
`
`circuit includes an AND gate, wherein the inputs lnputl , Input2, Input 3 and Input4 of the
`
`decoding circuit are connected to programmable elements, and an output of the AND gate is
`
`TSM06-0548
`
`- 9 -
`12
`12
`
`

`

`connected to a chip-enable (CE) line for the enablement and the identification of the respective
`
`die.
`
`[0025]
`
`The programmable elements in the ID circuit of each die are programmed differently
`
`from the programmable elements in the ID circuits of other dies. Table 1 illustrates exemplary
`
`states of the programmable elements on each of the dies 1, 2, 3 and 4, wherein the programmable
`
`elements are fuses. Letter “S” indicates that the corresponding fuse is shorted, or not blown,
`
`while letter “0” indicates that the corresponding fuse is open, or blown. Chip-select pads P1, P2,
`
`P3 and P4 are applied with signals CSO, CSO_B, CS] and CSl_B, respectively, wherein letter
`
`“H" indicates a higher potential, and letter “L” indicates a lower potential. Signal CSO_B has an
`
`inversed phase as signal C80, and signal CSl_B has an inversed phase as signal CS]. Therefore,
`
`the combination of the states of the fuses F1 , F2, F3 and F4 acts as a unique address of the
`
`correSponding die. The illustrated states of C80 and CSI are the required C80 and CSI signals
`
`for the chip-enable CE signal of the respective die to output a high potential.
`
`
`
`Table l
`
`
`
`
`
`TSM06-0548
`
`- 10 -
`13
`
`

`

`[0026]
`
`Referring to Figure 3, with different signals CSO, CSO_B, CSI and CSl_B applied,
`
`the output CE of the AND gates on dies 1, 2, 3 and 4 have different states. Using the
`
`identification circuit in die 1 as an example, assuming the input potential at node Inputl is high if
`
`time F1 is open, and the input potential is the same as signal CSO if fuse F l is shorted, then the
`
`chip-enable CE of die 1 is high when both CSO and CS] are high. The chip-enable CE of dies 2,
`
`3 and 4 are also determined by the input signals C30 and CS]. At one time, there is at most one
`
`die enabled by signals CSO and CS].
`
`[0027]
`
`In the case the programmable elements are flash memories or other types, the
`
`decoding circuits are designed to output a chip-enable CE signal according to the state stored in
`
`the flash memories.
`
`[0028]
`
`Figure 4 illustrates the states of the programmable elements F1, F2, F3 and F4 in
`
`each of the dies 1, 2, 3 and 4, wherein the programmable elements F1, F2, F3 and F4 are
`
`programmed according to Table 1. Preferably, after the formation of each die, the dies are
`
`programmed, wherein the programming may be performed before or after the sawing of dies
`
`from the respective wafer. In the case the programmable elements are laser fuses or electrical
`
`fuses, the programmable elements are blown by a laser ray or an electrical current. In the case the
`
`programmable elements are flash memory cells, the desired states of the programmable elements
`
`are written into the flash memory cells.
`
`[0029]
`
`Referring to Figure 5, dies 1, 2, 3 and 4 arestacked, with the corresponding chip-
`
`select pads P1_B, P2_B, P3_B and P4_B bonded to chip-select pads P1, P2, P3 and P4 of the
`
`underlying dies, respectively. Further, each of the U0 pads P101_B through PIOn_B are bonded
`
`to U0 pads PIOl through P1011 of the underlying die, respectively. In the preferred embodiment,
`
`TSM06-0548
`
`- ll -
`14
`14
`
`

`

`copper-to-copper bonding is performed. Accordingly, each of the chip-select pads Pl through P4
`
`on one die is connected to the respective chip-selected pads on other dies, and each of the U0
`
`pads PIOl through PIOn on one die is connected to respective I/O pads on other dies.
`
`[0030]
`
`In the stack structure, even though dies 1, 2, 3 and 4 are all interconnected, the
`
`distinction may be made through chip-select pads P1, P2, P3 and P4, by applying different
`
`combinations of signals CSO, CSO_B, CSI and CSl_B, respectively. Accordingly, each die is
`
`able to tell that the signal transferred on U0 pads PIOl through PIOn are destined for itself or
`
`not. Similarly, external circuits connected to the stack structure can also tell the signals applied
`
`on the 1/0 pads are read from the memories of which die. Accordingly, by applying the chip-
`
`select signals, any of the dies 1, 2, 3 and 4 can be read from and written into as desired.
`
`[0031]
`
`In the previous discussed embodiment, each ID circuit includes four programmable
`
`elements, which provide the ability for stacking up to 16 dies without changing the design. One
`
`skilled in the art will realize that for uniquely identifying four or less dies, only two
`
`programmable elements are needed in each die, wherein the state combinations of (0, 0), (0, l),
`
`(1 , 0) and (1, 1) are used to uniquely identifying four dies. If more dies are to be stacked, more
`
`programmable elements may be added. If only two dies are to be stacked, one programmable
`
`element may be used, wherein each of the states 0 and I (or open and short state for fuses) is
`
`used to identify one die. In this case, the programming operation may be performed after the
`
`stacking of two dies, wherein the t0p die is programmed to a different state from the bottom die.
`
`[0032]
`
`The stacked structure shown in Figure 5 is referred to back-to-front stacking, wherein
`
`the backside of one die is attached to the front side of another die. In alternative embodiments,
`
`back-to—back and front-to-front stacking schemes may be used. Such stacking schemes, however,
`
`requires the dies to have symmetric structure with same types of U0 pads and chip-selected pads
`
`TSM06-0548
`
`- 12 -
`15
`15
`
`

`

`on exactly the same positions when a die is flipped, so that a pad (such as chip-selected pads and
`
`U0 pads) may be connected to a'same type of pad on another die. In addition, one or more of the
`
`stacked dies may be thinned. For example, die 4 may have a greater thickness than dies 1, 2 and
`
`3. In this case, the only difference between die 4 and dies 1, 2 and 3 are the thickness of
`
`substrates (hence the lengths of TSVs), and programming states of the programmable elements.
`
`Accordingly, die 4 is still considered to be identical to dies 1, 2 and 3.
`
`[0033]
`
`In the previously illustrated examples, die-to-die stacking is performed. In other
`
`embodiments, wafer-to—wafer stacking and die-to-wafer stacking may be performed. In this case,
`
`dies on each wafer may be programmed first, and then bonded to dies on other wafers. Dies I, 2,
`
`3 and 4 may be bonded using solder bumps or other commonly used meanings.
`
`[0034]
`
`The embodiments of the present invention have several advantageous features. Since
`
`the stacked dies are identical, there is no need to manufacture more than one set of memory dies
`
`with different designs. The equipment and process for manufacturing and testing are thus
`
`simplified. This not only results in the reduction in cost, but also the improvement of the
`
`inventory and cycle time. In addition, there is no need to form different redistribution lines in the
`
`stacked dies. Interposers are also not necessary.
`
`[0035]
`
`Although the present invention and its advantages have been described in detail, it
`
`should be understood that various changes, substitutions and alterations can be made herein
`
`without departing from the spirit and scope of the invention as defined by the appended claims.
`
`Moreover, the scope of the present application is not intended to be limited to the particular
`
`embodiments of the process, machine, manufacture, and composition of matter, means, methods
`
`and steps described in the specification. As one of ordinary skill in the art will readily appreciate
`
`from the disclosure of the present invention, processes, machines, manufacture, compositions of
`
`“Mos-0548
`
`- 13 -
`16
`16
`
`

`

`matter, means, methods, or steps, presently existing or later to be developed, that perform
`
`substantially the same function or achieve substantially the same result as the corresponding
`
`embodiments described herein may be utilized according to the present invention. Accordingly,
`
`the appended claims are intended to include within their scope such processes, machines,
`
`manufacture, compositions of matter, means, methods, or steps.
`
`TSM06-0548
`
`_ 14 _
`17
`l7
`
`

`

`WHAT IS CLAIMED IS:
`
`1.
`
`A method of forming a semiconductor structure, the method comprising:
`
`forming a first semiconductor die and a second semiconductor die identical to the first
`
`semiconductor die, wherein each of the first and the second semiconductor dies comprises:
`
`an identificatiou circuit; and
`
`a plurality of inputfoutput (1/0) conductive paths connected to memory circuits in
`
`the respective first and second semiconductor dies, wherein the plurality of U0 conductive paths
`
`comprises through-silicon vias;
`
`programing the identification circuit of the second semiconductor die to a different state
`
`from the identification circuit of the first semiconductor die; and
`
`10
`
`11
`
`12
`
`bonding the second semiconductor die onto the first semiconductor die, wherein the first
`
`and the second semiconductor dies are vertically aligned, and wherein each of the plurality of 1/0
`
`conductive paths in the first semiconductor die is connected to a respective U0 conductive path
`
`13
`
`in the second semiconductor die.
`
`2.
`
`The method of claim 1, wherein each of the [HO conductive paths comprises a first and a
`
`second U0 pad on opposite sides of the respective first and second semiconductor dies, and
`
`wherein the