(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2004/0232559 A1
`Adelmann
`(43) Pub. Date:
`Nov. 25, 2004
`
`US 2004O232559A1
`
`(54) INTERCONNECT METHOD FOR DIRECTLY
`CONNECTED STACKED INTEGRATED
`CIRCUITS
`
`(76) Inventor: Todd C. Adelmann, Boise, ID (US)
`Correspondence Address:
`HEWLETTPACKARD COMPANY
`Intellectual Property Administration
`P.O. BOX 272400
`Fort Collins, CO 80527-2400 (US)
`(21) Appl. No.:
`10/440,815
`(22) Filed:
`May 19, 2003
`
`Publication Classification
`
`(51) Int. Cl. .................................................. H01L 23/48
`
`(52) U.S. Cl. .............................................................. 257/777
`
`(57)
`
`ABSTRACT
`
`A method and related configuration for Stacking and inter
`connecting multiple identical integrated circuit Semiconduc
`tor die. A die designed in accordance with the present
`invention can be directly interconnected with other identical
`die by placing a Second die on a first die. The Second die is
`substantially identical to the first die and has a rotation with
`respect to the first die. A plurality of electrical interconnec
`tions on the first die are contacted with a plurality of
`electrical interconnections on the Second die, forming elec
`trical interconnects between adjacent Stacked dies.
`
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`SAMSUNG EXHIBIT 1011
`Samsung v. Trenchant
`Case IPR2021-00258
`
`

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`Patent Application Publication Nov. 25, 2004 Sheet 1 of 5
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`US 2004/0232559 A1
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`Patent Application Publication Nov. 25, 2004 Sheet 2 of 5
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`US 2004/0232559 A1
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`Patent Application Publication Nov. 25, 2004 Sheet 3 of 5
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`US 2004/0232559 A1
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`Patent Application Publication Nov. 25, 2004 Sheet 4 of 5
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`US 2004/0232559 A1
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`Patent Application Publication Nov. 25, 2004 Sheet 5 of 5
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`US 2004/0232559 A1
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`

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`US 2004/0232559 A1
`
`Nov. 25, 2004
`
`INTERCONNECT METHOD FOR DIRECTLY
`CONNECTED STACKED INTEGRATED CIRCUITS
`BACKGROUND
`0001 Modern-day semiconductor devices, commonly
`called integrated circuits, or “dies,” are fabricated on wafers,
`and the wafers are then sawn into grids, Separating the
`individual dies prior to assembly in a package. Integrated
`circuits are fabricated in a variety of sizes, but typically
`range from only a few millimeters to a couple of centimeters
`or more in width. Each die may have numerous electrical
`Signals for input or output. Processors, for example, may
`have Several hundred signals.
`0002 Provisions must be made to electrically connect a
`die to the printed circuit board with which it is used and also
`to protect the die from damage or other external conditions
`that could hinder its operation. Package engineering, or
`packaging, is the field within Semiconductor engineering
`that addresses these needs. Integrated circuits are generally
`mounted on printed circuit boards in "packages, i.e., Struc
`tures that provide an electrical interface with a printed
`circuit board (or simply “board”) and also protect a bare die
`and its electrical interconnects from damage, including
`damage due to moisture, Vibration, and impact. A packaged
`die is generally attached to a metal leadframe or a Substrate,
`electrically connected to the leadframe or Substrate, and
`encapsulated with a ceramic enclosure or plastic "mold
`compound” for protection.
`0.003
`Occasionally, conventional packaging solutions
`may not afford adequate Space Savings on a printed circuit
`board. Especially in the case of memory devices, the func
`tionality of multiple dies may be required while Space for
`only one packaged die is available on a board. In Such cases,
`using a "multi-chip module' (MCM), or single package
`containing multiple dies, is often considered. In Some
`MCMS, dies are arranged Side-by-Side on a single Substrate.
`However, depending on the application, this approach may
`not provide Significant Space Savings over Simply packaging
`multiple dies Separately, a more common assembly process.
`Accordingly, it may be desired to Stack multiple dies within
`a single package.
`0004. There are several benefits to stacked die packages.
`More functionality within a given area of board Space may
`be achieved, Since more Silicon functions per area of board
`Space (and per unit volume of application space) are pos
`Sible. Eliminating individual packages for each die can
`contribute to Significant size and weight reductions of
`printed circuit boards and electronic devices in which they
`are installed. Including two or more dies in one package
`decreases the number of components mounted on an appli
`cation board, potentially reducing overall System cost. In
`addition, providing a single package for package assembly,
`electrical testing and handling may reduce manufacturing
`COStS.
`0005. In some cases, it is desirable to package multiple
`identical dies in a single package, Such as in the case of
`certain memory devices. AS an example, four identical
`8-megabyte (Mb) dies could be interconnected to act as a
`single 32-Mb device. In addition, a 16- or 24-Mb device
`could be assembled on the same package Substrate or board
`by interconnecting two or three of these dies, respectively,
`without the need for designing and fabricating an additional
`die design.
`
`0006 Stacking and electrically interconnecting several
`identical dies has proved problematic, Since each identical
`die will have the exact Same internal Structures, circuitry,
`and pattern of bond pads. Consequently, it is difficult to route
`multiple identical dies to a SubStrate or motherboard through
`those dies below it, Since an active feature on one die would
`require an area free of active circuitry on the die beneath it
`in order to pass through and connect with the Substrate or
`board. A need exists to provide a low-profile Solution for
`interconnecting multiple identical Stacked dies.
`
`BRIEF SUMMARY
`0007 Disclosed is a method and system for interconnect
`ing an integrated circuit die including a Surface having an
`integrated circuit and a plurality of bond pad Sets, with each
`bond pad Set having Substantially identical pad layouts on
`the die Surface. A die designed in accordance with the
`present invention can be directly interconnected with other
`identical die by placing a Second die on a first die. The
`Second die is Substantially identical to the first die and has
`a rotation with respect to the first die. A plurality of electrical
`interconnections on the first die are contacted with a plu
`rality of electrical interconnections on the Second die, form
`ing electrical interconnects between adjacent Stacked dies.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0008 For a detailed description of the embodiments of
`the invention, reference will now be made to the accompa
`nying drawings in which:
`0009 FIG. 1 shows a system-level schematic of an
`electronic device;
`0010 FIG. 2A shows a cross-sectional view of a first
`embodiment of the present invention, with a package con
`taining four identical Stacked dies,
`0011 FIG. 2B shows a top view of a die design in
`accordance with a representative embodiment;
`0012 FIG. 2C shows a perspective view of four stacked
`dies in accordance with a representative embodiment;
`0013 FIG. 2D shows a cross-sectional view of four
`Stacked dies in accordance with a representative embodi
`ment,
`0014 FIG. 3A shows a top view of an alternative
`embodiment of a die design for Stacking more than four dies,
`0.015 FIG. 3B shows a cross-sectional view of an alter
`native embodiment of a die design for Stacking more than
`four dies, and
`0016 FIG. 4 shows a top view of a die having an
`alternative bond pad configuration.
`
`NOTATION AND NOMENCLATURE
`0017 Certain terms are used throughout the following
`description and claims to refer to particular System compo
`nents. AS one skilled in the art will appreciate, Semiconduc
`tor companies may refer to processes, components, and
`Sub-components by different names. This document does not
`intend to distinguish between components that differ in
`name but not function. In the following discussion and in the
`claims, the terms “including” and “comprising are used in
`
`

`

`US 2004/0232559 A1
`
`Nov. 25, 2004
`
`an open-ended fashion, and thus should be interpreted to
`mean “including, but not limited to . . . . '
`0.018. The term “integrated circuit” refers to a set of
`electronic components and their interconnections (internal
`electrical circuit elements, collectively) that are patterned on
`the Surface of a microchip. The term "semiconductor
`device” refers generically to an integrated circuit (IC), which
`may be integral to a Semiconductor wafer, Singulated from
`a wafer, or packaged for use on a circuit board. The term
`“die” (“dies” for plural) refers generically to a semiconduc
`tor microchip, in various Stages of completion, whether
`integral to a wafer or Singulated from a Semiconductor wafer
`and including an integrated circuit fabricated on its Surface.
`The term "wafer' refers to a generally round, Single-crystal
`Semiconductor Substrate upon which integrated circuits are
`fabricated in the form of dies.
`0019. The term “interconnect” refers to a physical con
`nection providing possible electrical communication
`between the connected items. The term “bond pad” refers
`generically to a conductive site used for routing Signals or
`other electrical connections to or from a die, and may apply
`to sites for use with wirebond, C4 ball attach or other
`interconnect methods. It will be understood that, when the
`term “side' is used in the context of bond pads, a “side”
`refers to a periphery area on a top or bottom Surface of a die
`closest to a particular die edge face. The term "pin” refers to
`the terminating point on a die Surface of an electrical
`connection (Such as a signal address, power, ground or no
`connect) and generally corresponds to a specific bond pad.
`The term “land” refers to a conductive interconnection site
`on a package Substrate or printed circuit board. To the extent
`that any term is not specially defined in this specification, the
`intent is that the term is to be given its plain and ordinary
`meaning.
`
`DETAILED DESCRIPTION
`0020. The following discussion is directed to various
`embodiments of the invention. Although one or more of
`these embodiments may be preferred, the embodiments
`disclosed should not be interpreted, or otherwise used, as
`limiting the Scope of the disclosure, including the claims. In
`addition, one skilled in the art will understand that the
`following description has broad application, and the discus
`Sion of any embodiment is meant only to be exemplary of
`that embodiment, and not intended to intimate that the Scope
`of the disclosure, including the claims, is limited to that
`embodiment.
`0021. In accordance with the present invention, a method
`and System are disclosed for interconnecting multiple iden
`tical stacked semiconductor dies. Referring now to FIG. 1,
`a system-level schematic is shown of an electronic device 10
`incorporating dies 60 Stacked in accordance with the pre
`ferred embodiments. An electronic device 10 typically
`includes one or more printed circuit boards 20 to which a
`plurality of packages 30 are interconnected. The electronic
`device 10 may be a computer, mobile telephone or any
`typical electronic device incorporating a printed circuit
`board 20. Within a package 30, a plurality of identical dies
`60 are Stacked and interconnected to the package. Alterna
`tively, the package 30 may be absent, and the lowermost of
`the stacked dies 60 may be interconnected directly to the
`board 20. Dies 60 typically process input and/or provide
`information for operation of the electronic device 10.
`
`0022. A first embodiment of the present invention is
`shown in FIG. 2A, wherein four identical stacked dies 60
`are packaged on a Substrate 34 and covered with an encap
`Sulant 32. For the purposes of this disclosure, the Stacked
`dies 60 are assumed to be identical and are distinguished by
`position, from bottom to top, with reference numerals 61,
`62, 63 and 64, respectively. In the embodiment shown, the
`identical dies 61, 62, 63 and 64 are all rotated 90 degrees
`from one another, about an axis 65 perpendicular to the die
`Surfaces and passing Vertically through the geometric center
`of the dies.
`0023. A die typically includes integrated circuits with
`output pads, or “bond' pads (not shown), on at least one
`Surface of the die. For die designed in accordance with the
`present invention, both the top and bottom faces of a die
`have matching patterns of bond pads, with each pair of
`matching bond pads linked by connections passing from the
`top face to the bottom face. The die is designed to be usable
`in various rotational positions relative to the Substrate 34. In
`the following description, the number of rotational positions
`is assumed to equal four.
`0024. It will be understood that, while four dies 60 are
`shown, more or fewer dies could be assembled in this
`manner without departing from the Spirit of the invention. It
`will also be understood that the dies will be described as
`having bumped interconnections 40 with one another, but
`can have any Suitable method for direct interconnection in
`accordance with the representative embodiments. It will also
`be understood that the dies may be interconnected to a
`printed circuit board or packaging Solution other than a
`Substrate.
`0025 Adie designed in accordance with various embodi
`ments may have pads along all four Sides of the die Surface,
`with each Side having a different Set of pins assigned to the
`bond pads (see FIG. 2B). When used in the context of die
`orientation, the term "Side” refers generically to a periphery
`area of a die, whether an end face or Surface area near Such
`an end face. In a configuration having four identical, Stacked
`dies, each of the four sides on each die will have a different
`pad assignment order. However, it will be understood that
`each die will have the same pad layout, Such that the
`spacings between and locations of bond pads on each side
`will be identical on each of the four sides. When the dies are
`assembled according to certain embodiments, only one side
`is used per die for routing all signals.
`0026. Each die is designed for electrical interconnection
`with other identical Stacked dies. The pad layout may be
`chosen So that certain pads exist in each Set, and other pads
`operate to distinguish each Set. Distinguishing pads do not
`have to be “select” lines, but may alternatively be “address”
`lines with four different logic maskS. Electrical interconnec
`tions between two dies are formed So one set of pads from
`each die is in electrical communication with the other dies.
`AS an example, if four dies are to be interconnected, and
`each die represents one megabyte (Mb) of memory, pad
`locations for data Signals and address Signals may be in each
`Set. ESSentially, on each Side of the die, a particular address
`Signal pad has the same location on every Side of the die, no
`matter how the die is rotated.
`0027. The embodiments of the present invention do not
`require connecting multiple unique dies, but allow direct
`interconnection of more than one of the same dies, rotated
`
`

`

`US 2004/0232559 A1
`
`Nov. 25, 2004
`
`from the die layered with it. The rotation between adjacent
`dies is determined by the symmetry, and for a four-fold
`Symmetry, the rotation may be Some multiple of 90 degrees.
`In addition to four-way rotational Symmetry, other poten
`tially useful Symmetries include two-way, three-way and
`Six-way Symmetries. Accordingly, rotations may correspond
`to integer multiples other than 90, including 45, 60, 120
`and 18O.
`0028 Many semiconductor devices are “pad limited.”
`meaning all available Space in on the perimeter of a die
`Surface is used for bond pads. On memory devices, however,
`all bond pads could frequently be placed on one side of the
`perimeter, leaving the other three sides free for repeating the
`pads in a matching pattern. This configuration allows more
`than one of the same die to be Stacked, when rotated, in
`accordance with the described embodiments.
`0029 Dies designed according to the interconnect
`method of various embodiments are specially designed
`having conductive pathways, or Vias (not shown), passing
`through a die between electrical connections on top and
`bottom Surfaces of the die. These electrical interconnections
`may be conductive “bond' pads upon which a conductive
`ball, or "bump,' is deposited for connecting the Surface of
`one die to the Surface of another. Each bond pad is typically
`associated with a certain signal or other pin (Such as a power,
`ground, or no connect) within the die.
`0030) A representative embodiment is shown in FIG.2B,
`in which a top view of a die 60 is shown having bond pads
`70 arranged into sets 78, with each set 78 having an
`operational relationship to the integrated circuit of the die
`that is unique to the particular Set. Each Set 78 includes one
`or more bond pads 70, with each bond pad having an
`operational relationship to the integrated circuit that is
`operationally indistinguishable to a corresponding bond pad
`in another bond pad set. Each set 78 is coupled to the
`integrated circuit by an address range unique to the Set.
`0.031) Each bond pad 70 is typically associated with a pin,
`with a portion of the pins labeled as “B” for blanks 72, “S”
`for Select lines 74, and “A” (where Ax represents Succes
`sive address pins from A to AN) for address lines 76. The
`address pins on each die Side are collectively referred to as
`an “address/data bus,” in which the address and data pins
`may be multiplexed. Blank pads 72 are simply placeholders
`within a pad configuration, Serving as unused spaces through
`which Vias and other lines may vertically pass to adjacent
`dies, and may not require electrical connection to internal
`circuitry within the die. Select lines 74 determine which of
`the multiple die is currently being addressed, and conse
`quently, which of the multiple dies has control of the
`address/data bus. Collectively, blank pads 72 and select lines
`74 within a set 78 are referred to as “selection bond pads.”
`Typically, only one Select Signal is active at a single time. On
`each die Side, the assignment of Select pads and blank pads
`are varied to allow the rotated, identical die to be used in
`accordance with the present invention.
`0032. In an exemplary implementation, address/data
`lines A.N. and AN2 from the host computer/micropro
`cessor (not shown) would be decoded to provide individual
`addressing lines that would be connected to the Select lines
`on pads 61-64. This would allow the four dies to each cover
`a different address space and be selected (enabled) only at
`the appropriate time. For example, there may be 16 address/
`
`data lines, A through A. That means each die would have
`64K addressable bytes. Two additional address lines, A7
`and As, for example, would be routed to the Select lines
`such that die 61 is enabled for accesses in the range 0-64KB,
`die 62 in the range 64-128KB, die 63 in the range 128K-192
`KB and die 64 in the range 192-256 KB.
`0033. In this first embodiment of the present invention,
`each of the four dies 60 have internal circuitry connected to
`one of the Select lines. When the appropriate Select line is
`asserted, the die responds to the address Signals and may
`Store or provide data on data signal lines (not shown).
`Address lines 76 respond and return data. It will be under
`stood that, in addition to the pin types illustrated herein,
`power, ground, and other control lines may be present on the
`die. As an example, between layered address lines 76 on four
`Stacked dies, all four aligned address positions are connected
`and active at the same time. Select pins vary locations on
`each side of a die, Such that, when aligned with adjacent
`Stacked dies in accordance with the present invention, die
`pins above or below the certain select position will be blank
`pins. Address pins have the Same location on each side of a
`die, Such that A1 on one die will be aligned with A1 on an
`adjacent die, no matter the rotational orientation of the
`adjacent die.
`0034. The first embodiment of the present invention is
`illustrated more clearly in the perspective view of FIG. 2C,
`where four identical dies 60 are stacked and electrically
`interconnected with one another. In this embodiment, die 60
`has a particular pattern and spacing of bond pads 70, which
`may follow a conventional “bond ring design, wherein pads
`are laid out on the die Surface, near the perimeter of the die
`60. Each side (81, 82, 83, 84, respectively) of die 60 has a
`unique order of pin assignments, Such that when each
`Subsequent die is rotated 90 degrees and Stacked on top of
`the previous die, the physical bond pads are repeated in the
`Same pattern, but the pins assigned to each pad are often
`varied, depending on pin type, in order to allow electrical
`interconnection through all Stacked dies. Again, it will be
`understood that, while four dies are shown as an example,
`more or fewer dies may be assembled in accordance with the
`representative embodiments without departing from the
`spirit of the invention.
`0035). As with FIG. 2A, for the purposes of differentia
`tion, the identical stacked dies 60 shown in FIG. 2C are
`labeled from bottom to top as 61, 62, 63 and 64. Each die 60
`generally has four sides 81, 82, 83 and 84, rotating a die by
`90 degrees will present a different side in a side view. When
`four identical dies 60 are interconnected together, four
`unique end faces are preferably lined up with those above
`and below it. If more than four dies are interconnected, a die
`end face may be repeated on a face of the Stack, as necessary
`to achieve the required routing.
`0036). In a cross-sectional view of a first embodiment of
`the present invention, as shown in FIG. 2D, identical dies
`61, 62, 63 and 64 are stacked with end faces 81, 82, 83 and
`84 lining up, respectively. When a chip select 74 is to be
`activated on die 64, this signal can be communicated from
`a device (not shown) on Substrate 34 and pass up through
`blanks 72 on the three dies 60 below die 64. When a chip
`select 74 is to be activated on die 63, this signal can be
`communicated from substrate 34 and pass through blanks 72
`on the two dies 60 below die 64. When a chip select 74 is
`
`

`

`US 2004/0232559 A1
`
`Nov. 25, 2004
`
`to be activated on die 62, this signal can be communicated
`from a device (not shown) on Substrate 34 and pass through
`blanks 72 on the single die 60 below die 64. When a chip
`select 74 is to be activated on die 61, this signal can be
`passed directly from the Substrate 34. When any of the
`addresses 76 (from address A to address AN) are active, all
`four layered address locations are active at the same time,
`Such that when A is active on die 64, A1 is also active on
`dies 61, 62 and 63 as well.
`0037 Generally, the number of dies stacked will corre
`spond to the number of Sides per die used for interconnec
`tion. However more than one bond pad ring may be present
`on each Side of a die, allowing more than four dies to Stacked
`and interconnected. As shown in a top view in FIG. 3A, an
`alternative embodiment of the present invention features
`more than one set 100 of bond pads 70 per die side, there
`generally being one Set 90 of bond pads on a die Surface per
`die 90 to be stacked. It will be understood that, while Such
`sets have been shown in FIG. 3A as linearly arranged rings
`of bond pads 70 near the die periphery, the bond pads may
`conform to any pattern on the die Surface, linear or other
`wise, as long as this pattern is repeated as the die 90 is
`rotated in 90-degree increments.
`0038 FIG. 3B shows a side view of a possible pin
`arrangement for a die having more than four Sets of bond
`pads per Side, in order to accommodate Stacking more than
`four dies. Six dies 90 are shown, distinguished by position,
`from bottom to top, with reference numerals 91, 92,93, 94,
`95 and 96, respectively. In order to facilitate such a con
`figuration, a different set 100 of pads 70 is targeted by
`varying the interconnection pattern between the fourth and
`fifth dies, as designated from the bottom of the stack, for die
`configurations with four unique pad Sets. For example, it can
`be seen in FIG. 3B that the pattern of interconnections 40
`used for dies 91-94 is no longer needed for dies 95 and above
`since all four configurations of the outer set 102 have been
`used in rotation.
`0039. It will be understood that, in dies 95 and 96, outer
`set 102 is still present, but is not shown in the side view of
`FIG. 3B for the purposes of clarity. This first pattern of
`interconnections 40 between the pads of set 102 can be
`terminated at the fourth die, or die 94, and a new pattern can
`be used between the pads of set 104 connecting the fourth
`die 94 and every subsequent die (95 and 96). It will be
`understood that, although not shown, set 104 includes suf
`ficient blank pads 72 to allow routing of dies above the
`fourth die (e.g., dies 95 and 96) through the first four dies
`(e.g., dies 91-94) to the substrate 34. Each die is designed
`and rotated in the Stack Such that only one die is paying
`attention to activated address lines.
`0040. It will also be understood that the bond pads do not
`have to conform to a conventional “ring” design, requiring
`placement on the perimeter of a die Surface. AS bumped dies
`often have interconnects on the area of a die Surface, any
`routable configuration of bond pads may be used, without
`restriction to a certain geographic location on the die Sur
`face, as long as they are repeated as the die is rotated in
`90-degree increments. This is illustrated in FIG. 4, a top
`View of a die 110 having a repeating pattern of bond pads
`120, not arranged in a typical peripheral ring configuration,
`but repeating when rotated by 90-degree increments, none
`theless.
`
`Dies will be attached to one another by known
`0041
`electrical interconnect method, including C4 ball attach, or
`other Suitable method known in the art. In essence, all
`interconnected dies are working as one. For memory
`devices, this arrangement can allow customization of
`memory needs, as each additional die Stacked can contribute
`more memory, allowing a degree of customization within the
`Space used for one package. In addition to the benefits
`already mentioned, there is only one device to design,
`fabricate, test and assemble for use with a representative
`embodiment, which can potentially lead to Supply chain
`benefits, more Straightforward troubleShooting and yield
`management. Numerous variations and modifications will
`become apparent to those skilled in the art once the above
`disclosure is fully appreciated.
`What is claimed is:
`1. A method for electrically interconnecting a plurality of
`identical Stacked integrated circuit dies, comprising the Steps
`of:
`placing a Second die on a first die, wherein the Second die
`is identical to the first die, the Second die having a
`rotation with respect to the first die;
`contacting a plurality of electrical interconnections on the
`first die with a plurality of electrical interconnections
`on the Second die; and
`forming electrical interconnects between adjacent Stacked
`dies.
`2. The method of claim 1, wherein the plurality of
`identical dies includes three or more identical dies.
`3. The method of claim 1, wherein the electrical inter
`connections are C4 bumps.
`4. The method of claim 1, wherein the electrical inter
`connections are Solder columns.
`5. The method of claim 1, wherein the dies are mounted
`directly to a printed circuit board.
`6. The method of claim 1, wherein the dies are packaged
`on a Semiconductor package Substrate.
`7. The method of claim 6, wherein the package is mounted
`to a printed circuit board.
`8. An integrated circuit die that comprises:
`a Surface having an integrated circuit; and
`a plurality of bond pad Sets each having Substantially
`identical pad layouts on the Surface, wherein the Sub
`Stantially identically pad layouts are mutually related
`by rotations about an axis perpendicular to the Surface,
`wherein each bond pad Set includes one or more corre
`sponding Selection bond pads that, as a group, have an
`operational relationship to the integrated circuit that is
`unique to the bond pad Set.
`9. The die of claim 8, wherein the bond pad sets are
`coupled by conductive paths to matching bond pad Sets on
`an opposite Surface of the die.
`10. The die of claim 8, where each bond pad set further
`includes one or more bond pads that each have an opera
`tional relationship to the integrated circuit that is operation
`ally indistinguishable from a corresponding bond pad in
`each other bond pad Set.
`11. The die of claim 8, wherein each of the selection bond
`pads in the group transports a Select Signal, and wherein each
`of the bond pad Sets couples only one of the Selection bond
`pads from the Set to the integrated circuit.
`
`

`

`US 2004/0232559 A1
`
`Nov. 25, 2004
`
`12. The die of claim 8, wherein the rotations correspond
`to integer multiples of 45.
`13. The die of claim 8, wherein the rotations correspond
`to integer multiples of 60.
`14. The die of claim 8, wherein the rotations correspond
`to integer multiples of 90.
`15. The die of claim 8, wherein the rotations correspond
`to integer multiples of 120.
`16. The die of claim 8, wherein the rotations correspond
`to integer multiples of 180.
`17. The die of claim 8, wherein the sets of one or more
`corresponding bond pads transport address Signals, and
`wherein each of the Sets is coupled to the integrated circuit
`by a unique address range.
`18. An integrated circuit die that comprises:
`an integrated circuit; and
`bond pads having a rotationally Symmetrical layout,
`wherein each bond pad is electrically connected to a
`corresponding aligned bond pad on an opposite Surface
`of the die.
`19. The die of claim 18, wherein the integrated circuit is
`designed for correct operation in each rotational alignment
`of bond pads to a set of Supplied operating Signals.
`20. The die of claim 19, wherein the integrated circuit
`operation is enabled in a rotation-dependent fashion.
`21. The die of claim 18, wherein the rotational symmetry
`is two-fold or four-fold.
`22. The die of claim 18, wherein the rotational symmetry
`is three-fold, six-fold, or eight-fold.
`23. An integrated circuit package that comprises:
`a plurality of identical dies Stacked and electrically
`bonded to adjacent dies, wherein each die is rotated
`with respect to adjacent dies,
`an encapsulant that Surrounds the plurality of identical
`dies, and
`a package Substrate upon which the Stacked dies are
`connected.
`24. The integrated circuit package of claim 23, wherein
`the plurality of identical dies includes three or more identical
`dies.
`
`25. The integrated circuit package of claim 23, wherein
`the identical dies are aligned along an axis of rotational
`Symmetry.
`26. An interconnection means for electrically intercon
`necting a plurality of identical Stacked integrated circuit
`dies, comprising the Steps of
`placing a Second die on a first die, wherein the Second die
`is identical to the first die, the Second die having a
`rotation with respect to the first die;
`contacting a plurality of electrical interconnections on the
`first die with a plurality of electrical interconnections
`on the Second die; and
`forming electrical interconnects between adjacent Stacked
`dies.
`27. An electronic System comprising:
`an electronic device, wherein the electronic device
`includes a printed circuit board;
`a plurality of identical dies Stacked and electrically
`bonded to adjacent dies, wherein each die is rotated