||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
`
`US 20020185337A1
`
`(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2002/0185337 A1
`(43) Pub. Date: Dec. 12, 2002
`
`Miura ct al.
`
`(S4) SEMICONDUCTOR DEVICE WITH
`NON-VOLATILE MEMORY AND RANDOM
`ACCESS MEMORY
`
`(75)
`
`Inventors: Seiji Mlura, Ilachioji (JP); Kazushige
`Ayukawa, Kokuhunji (JP)
`
`Corresrxtndence Address:
`Stanley 1’. Fisher
`Reed Smith [.[.P
`Suite 1400
`3110 Fairview Park Drive
`Falls Church, VA 22042-4503 t US)
`
`(73) Assignee: Hitachi, Ltd.
`
`(21) Appl. No.:
`
`101164305
`
`(22)
`
`Filed:
`
`Jun. 10, 21002
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 11, 2001 (JP) 2001-174978
`
`Publication Classification
`
`(51)
`
`Int. CI.’ ....................................................... GllC amt)
`
`(52) U.S. Cl.
`
`......................................... 1851'11; 365.r'23ft.03
`
`(57)
`
`ABSTRACT
`
`A semiconductor device including a large capacityr non-
`volatile memory and at least one random access memory,
`said the access time of said device being matched to the
`access time of each random access memory. The semicon-
`ductor memory device is comprised of:
`a non—volatile
`memory FLASH having a
`first
`reading,
`time; a
`random
`access memory DRAM having a second reading time which
`is more than 100 times shorter than the first reading time; a
`circuit that includes a control circuit connected to both the
`FLASH and the DRAM and enabled to control accesses to
`
`those FLASH and DRAM; and a plurality of ltU terminals
`connected to the circuit. As a result, I-‘LASII data is trans-
`ferred to the DRAM before the DRAM is accessed. thereby
`matching the access time between the l-‘LASt-l and the
`DRAM. Data is written back from the DRAM to the FLASH
`
`thereby keeping data matched between the
`as needed.
`FLASH and the DRAM and storing the data.
`
`~01 —D015
`
`_""“D1—VCCO
`
`D1—/CAS-— .
`" “D1—VSSQ
`D1-/WE -—___—
`
`—‘D1—DQMU/DQML
`D1 nan .__fl--
`
`~D‘i-A14
`
`
`
`
`CHIP2
`
` {CTL_LOGIC}
`
`
`
`
`F—/FtES
`
`
`F_-CDE
`DOMU/DQML 0
`_lOO~l/O?
`
`
`WAIT O
`
`
`
`F-VCC
`
`o
`
`CHIPt
`(FLASH)
`
`F—/OE
`F—/WE
`
`/ BUSY
`
`F—VSS
`
`(cid:54)(cid:36)(cid:48)(cid:54)(cid:56)(cid:49)(cid:42)(cid:3)(cid:40)(cid:59)(cid:43)(cid:44)(cid:37)(cid:44)(cid:55)(cid:3)(cid:20)(cid:19)(cid:20)(cid:19)(cid:3)
`SAMSUNG EXHIBIT 1010
`(cid:54)(cid:68)(cid:80)(cid:86)(cid:88)(cid:81)(cid:74)(cid:3)(cid:89)(cid:17)(cid:3)(cid:55)(cid:85)(cid:72)(cid:81)(cid:70)(cid:75)(cid:68)(cid:81)(cid:87)(cid:3)
`Samsung v. Trenchant
`(cid:38)(cid:68)(cid:86)(cid:72)(cid:3)(cid:44)(cid:51)(cid:53)(cid:21)(cid:19)(cid:21)(cid:20)(cid:16)(cid:19)(cid:19)(cid:21)(cid:24)(cid:27)(cid:3)
`Case |PR2021-00258
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 1 0f 43
`
`US 2002/018533'? A]
`
`FIG.
`
`1
`
`“~D1-VCC
`D1 V38
`“~01 VCCQ
`“*D1-VSSQ
`#1 D1—DQMU/DQML
`“mm—000
`~D1-D015
`
`D1—CLK~.._”_
`D1-CKE~W
`311233
`‘
`D1‘/CAS*‘"
`311315;!
`~D1-A14
`S-VCC .
`gévss o
`L—VCC o
`L—VSS o
`
`F—/OE
`CHIP2
`CLK
`
`
`(CTL_LOGIC)
`CKE
`
`
`
`F—/WE
`/CS
`CHIP1
`/RAS
`
`Fn/RES
`(FLASH)
`/CAS
`
`
`/WE
`IF_—CDE
`
`I/OO—I/O
`DQMU/DOMLO
`
`
`WAIT 0
`
`5%}
`A0—A15 0
`DQO—3—63150
`
`F—VCC
`
`F-VSS
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 2 of 43
`
`US 2002/0185337 A1
`
`FIG. 2
`
`
`
`CHIP2£CTL_LOGIC)
`
`
`
`0 D1 —CKE
`0 D1 —/CS
`0 D1 -/RAS
`0 D1—/CAS
`o D1—/WE
`0 D1 —DQMU/DQML
`
`CKE
`/CS
`mas
`/CAS
`/WE
`DQMU/DOML o
`WAIT o
`
`
`
`
`A0-A15 0
`
`
`ps 0
`O D1—A0~Di—A14
`
`L-VCC o
`o D1—VCC
`
`L-VSS 0
`o m-vss
`
`o D1—DOO~D1-DO15
`
`
`o D1—CLK
`
`CLK o
`
`1/00~I/015 o
`
`
`F—HDY/BUSY RB
`
`F—/CE
`
`= F—/OE
`- F-SC
`Fa/RES
`I F—/CDE
`= I/OD~l/O7
`
`_
`g vgg
`'V
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 3 0f 43
`
`US 2002/0185337 A1
`
`FIG. 3
`
`FLASH
`(256+8)Mb
`
`A1
`
`64Mb
`
`A2
`
`2—Mb
`
`DRAM
`256W”)
`
`Fall Area C
`
`MD—Area
`Fail Area Bx-
`
`
`
`
`FLASH Copy
`Area
`
`A0~A15
`
`REG
`
`h'
`
`__
`
`E1
`8Mb
`
`E2
`0.!)25M
`
`Work Area
`128Mb
`
`Rep—Area
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 4 of 43
`
`US 2002/018533’? A]
`
`FIG. 4
`
`FLASH
`(255+§)Mb
`
`
`DRAM
`256Mb‘“"
`
`FLASH Copy
`Area
`
`
`
`“Fail Area C
`
`--
`
`Rep—A—rea
`
`FIG. 5
`
`
`T1
`T2
`T3
`T4
`..
`
`POWER ON RESET DRAM INITIALIZATION
`
`IDLE S:
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 5 0f 43
`
`US 2002/0185337 A1
`
`FIG. 6
`
`
`
`STEP2
`LOAD & ADDRESS
`
`
`
`STEP3
`READ from FLASH
`
`STEPS
`
`ERROR CORRECTION
`
` STEPS
`
`WRITE to BUFFER
`
`
`
`
`
`STEP?
`REFRESH
`REQUEST
`
`
`
`STEPS
`
`REFRESH
`
`
`
`
`STEP9
`
`WRITE to DRAM
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 6 0f 43
`
`US 2002/0185337 A1
`
`FIG. 7
`
`STEP2
`STORE & ADDRESS
`
`STEPS
`REFRESH
`REQUEST
`
`STEP4
`REFRESH
`
`REPLACE
`
`STEP5
`READ from DRAM
`
`STEPS
`
`WRITE to BUFFER
`
`STEP?
`WRITE to FLASH
`
`STEP9
`ADDRESS
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 7 0f 43
`
`US 2002/0185337 A1
`
`FIG. 8(A)
`
`FIG. 8(8)
`
`STEP2
`ACTIVE & ROW ADDRESS
`
`STEPS
`READ & COLUMN ADDRESS
`
`
`
`
`
`
`
`STEP4
`PRECHARGE
`
`STEP2
`ACTIVE & FIOW ADDRESS
`
`STEPS
`WRITE & COLUMN ADDRESS
`
`
`
`
`
`
`
`STEF4
`PRECHARGE
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 8 0f 43
`
`US 2002/018533? A]
`
`FIG. 9
`
`
`
`
`COPY AREA
`
`
`
`
`STE P2
`
`
`
`STEP1
`
`WRITE to FLASH
`
`WRITE FLAG to
`
`REGISTER
`
`
`COMPLETE
`
`
`YES
`
`STEPS
`
`CLEAR FLAG
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 9 0f 43
`
`US 2002/0185337 A1
`
`FIG. 10
`
`STEP1
`
`POWER OFF
`COMMAND
`
`
`
`
`
`
`
`
`
`STE P2
`
`Search Address
`
`=Start Address
`
`
`
`
`
`STEPS
`
`
`FIND FLAG
`
`
`STEP4
`DRAM to FLASH
`
`STEPS
`Search Adress
`=End Adress
`
`
`
`YES
`
`STEPS
`POWER OFF
`
`
`
`
`
`
`STEPS
`CLEAR FLAG
`
`
`
`
`
`STEP?
`Search Address=
`
`Start Address+1
`
`
`
`
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 10 0f 43
`
`US 2002/0185337 A1
`
`EXTERNAL
`
`_CLK
`
`HHI‘II‘II‘II‘II‘II‘II‘II‘II'UIJLILIIJIJIJIJUI
`
`
`
`
`
`F D1-CLK WWW
`D1—COM DDDODOOCJ
`915$9A15 OOODDDDCI W
`9155’9801sooooooodmmnmmmmnu
`_WAIT ___—l—_‘—I_
`
`EEG'ERNAL
`CLK
`
`JUUUUUUUUUUUUUUUUUUUI
`
`
`
`D1—COM IIIIIIaImII Mill-.13..-
`915$?” IIIIIIGDIGDIIDEDDODDOC)
`DDD_IIIIIIIIII@» IcommcomtaII
`__WA1T —[———|__
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 11 0f 43
`
`US 2002/018533? A]
`
`EXTERNAL
`
`FIG. 13(A)
`
`CLK
`
`COM
`
`AwwAw
`
`
`
`100~4cn5 IIIIIIIIIIIlllIlllllllflflflflflbflblilliiilli
`
`
`
`DRAMI
`
`D1—CLK
`
`||||||||||||||||||||||||||||||||||||||||
`
`
`
`EXTERNAL
`
`CLK AD~A15
`
`EOO~IO15 .CDCIGGEQCCECDCDCBIIIII
`
`DRAM1
`
`D1—CLKW
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 12 0f 43
`
`US 2002/0185337 A1
`
`EXTERNAL
`
`CLK
`
`ILFIIU'IJULIUU'IJ'LI'LI'IJ'LI'U'IJ'LI'LI'LI'LI'I
`
`
`IL100~1015 @®@I...@@@@IIIIG§®@®®
`
`DRAMi
`
`fD1—CLK
`
`J'LI'LI'LI'IJ'LI'LI'LI'IILJ‘U'IJ'IJ‘IJ'IJ'U—U'LIU'LI'I
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 13 0f 43
`
`US 2002/0185337 A1
`
`FIG. 15
`
`
`
`IIIIIIIII
`
`—
`
`Dl—BUFII lDC
`
`Y-GATE/SENS AMP.
`
`
`
`I MA(AND TYPE)
`SA—BUF
`X—DEC
`
`I:
`
`
`
`magi
`
`
`
`
`
`IIL- DO—BUF
`
`
`
`
`Y— DEC
`
`*'
`
`Y—CT
`
`F-/CE o
`
`F~/OE o
`
`F-/WE o
`F-SC
`o
`
`F—/RESO
`F—/CDE0
`
`F-RDY .
`/BUSY
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 14 0f 43
`
`US 2002/0185337 A1
`
`FIG. 16
`
`_1_25ns
`
`5—/_
`
`5—/_
`
`5—
`
`r:
`50n5
`50n3
`50a 5
`_'1'1 SJ—
`
`Inn-SEX;-
`5——
`5——
`
`45“ S
`
`ms
`
`F—/CE
`
`F—/OE
`
`F-/WE
`
`F'/CDE
`we
`
`100~107
`F—/RES
`F—HDY
`/BUSY
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 15 0f 43
`
`US 2002/018533'? A1
`
`FIG. 17
`
`.v
`
`F—VCC
`
`Di—CLK
`
`D1—Ofimxdr
`—“DFWE
`31 £3254 W
`
`“D1—VCCQ
`—
`fi*—*
`
`W01 -vsse
`9‘ VCAS
`
`D1-/WE ~—~——
`H
`
`_
`“"“D1—DQO
`
`
`D1 A14 *vD1-D015
`s—vcc o
`
`84/53 0
`
`PS
`{3333'
`F
`°
`
`
`
`
`CHIP2
`'
`
`(CTL_LOGIC)
`F'CLE
`CLK
`
`
`—:_fiIWEE
`o
`BEES
`
`
`”3Q? :
`WHE
`(FLASH)
`ng .
`
`DGMUABDgySLO
`I/OO~I/O7
`D00— 0015 o
`F‘R/B
`RB F—VSS
`
`-
`
`CHIP1
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 16 0f 43
`
`US 2002/0185337 A1
`
`FIG. 18
`
`F—VCC F—VSS
`
`??
`
`
`
`
`
`1/07.? £624} “ID—MEGI—lflrI
`
`
`I:
`fi—SENSEAMP
`LL 0‘
`Po: Pi
`
`”3 “I(-NAND TYPE)
`
`
`COMREG
`
`DATA— REG
`
`g g
`
`M
`
`F-/CE
`
`F—CLE
`
`F—/WE
`F-/FIE
`
`F_/WP
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 17 0f 43
`
`US 2002/0185337 A1
`
`FIG. 19
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002
`
`Sheet 18 0f 43
`
`MM3
`
`$2.2:00
`
`mum
`
`mm:0...DmwmKEsmQAUEM28-52830wawmmmmm
`oooooooIEtaEtaw0694858
`5&85%:
`
`
` ......522%mv_932%WY_222%Fwem3
`.m28%;ammgamma2.Emm38%;GnP.m.mP.n.”a_
`oimmx”m3%»3%2Exw,1maxm,max
`
`S
`
`S
`
`ENSE AMP. & 1/0 BUS
`
`Y—DEC
`
`$2
`
`o<-xz<m
`
`Rom—mawm
`
`2238
`
`:mmrx
`
`max
`
`S
`
`ENSE AMP. & I/O BUS
`
`
`
`
`
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 19 0f 43
`
`US 2002/0185337 A1
`
`D1 -/CS ~— +#
`D1 -/RAS ~—
`
`D1 -VSS
`_ ED1—VCCO
`
`D1 —VSSQ
`
`
`
`
`*fiD1-DQMU/DQML
`
`“‘ “D1-DOO~D1—DQ15
`
`0 A0~A24
`I/OO~I/O15
`
`F—VCC
`O
`
`(SRAM+CTL_LOGIC)
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 20 of 43
`
`US 2002/018533? A]
`
`FIG. 22
`
`CHIP2(SF{AM + CTL_LOGlC)
`
`I [/OO~l/O15
`
`
`
`O D1—DOO‘VD1—0015
`
`o D1—A0~D1-A14
`o D1—CKE
`o D1-/CS
`I D1n/FIAS
`o D1—/CAS
`O D1—/WE
`o D1-DOMU/DQML
`
`o D1-CLK
`o D1-VCC
`
`o Dt—VSS
`
`O F-/CE
`O F-/OE
`O F-/WE
`I F—SC
`O F—/HES
`O F—/CDE
`O I/OUNI/OB
`0 F—RDY/BUSY
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 21 0f 43
`
`US 2002/0185337 A1
`
`FIG. 23
`
`
`
`Fail Area D _
`
`A1
`64Mb
`
`A2
`2Mb
`
`
`
`A0~A24
`
`WORK Area
`128Mbit m.
`
`
`
`16Kbit
`
`F-/CE
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 22 0f 43
`
`US 2002/0185337 A1
`
`FIG. 24
`
`FLASH
`(256+81Mb\
`
`NIB—Area-
`
`Fail Area D ~—
`
`
`
`
`
`Fail Area Cy
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 23 0f 43
`
`US 2002/0185337 A1
`
`FIG. 25
`
`FLASH
`[256+8)M
`
`MID—Area»!
`
`A1
`64Mb
`
`A2
`2Mb
`
`Fail Area Dv_
`
`Fail Area C\
`
`DRAM
`256Mb‘“
`
`FLASH Copy
`Area
`
`“”24
`
`REG
`
`
`
`WORK Area
`128Mbit
`
`
`
`Rep—Area
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 24 0f 43
`
`US 2002/0185337 A1
`
`FIG. 26
`
`FLASH
`(256+E)Mb
`
`MD—Areaw- .
`
`A1
`64Mb
`
`A2
`2Mb
`
`Fail Area D _—
`
`Fail Area C\
`
`DRAM 1Mb
`SRAM16Kb
`
`
`
`
`Rep—Area
`
`DRAM
`256Mb
`
`FLASH
`Copy Area
`
`WORK A
`128Mb
`
`rea
`
`
`
`
`
`
`REG
`—'
`
`
`
`
`DRAM 1Mb
`
`SFIAM 16Kb
`
`DRAM 1Mb
`SRAM 16Kb
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 25 0f 43
`
`US 2002/018533’? A]
`
`FIG. 27(A)
`EXECUTION PRIORITY ®>®>©
`
`@EXT. ACCESS
`
`
`
`70ns
`
`I
`
`70ns
`
`FIG. 27(3)
`I
`mns
`I
`115ns
`?0n5
`
`@READ
`@READ
`
`I
`
`EXT. ACCESS
`
`REF ACCESS
`
`
`WAIT __-..._
`DRAM ——__ll
`
`
`@READ
`
`
`
`
`
`FIG. 27(0)
`I
`70ns
`115ns
`
`70ns
`
`
`70ns_
`
`_+_
`
`_I
`
`m ACCESS
`
`|
`
`REF ACCESS
`
`WAIT
`
`DRAM
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 26 0f 43
`
`US 2002/0185337 A1
`
`FIG. 28(A)
`
`70ns
`
`EXT. ACCESS -S
`
`WAIT —|——_—|_
`
`
`DRAM
`
`|
`
`j?
`
`|®WRITE[®WRITE| S( @WFHTEI
`
`FIG. 28(8)
`
`I
`?0ns
`EXT. ACCESS _5
`
`WAIT __I__—l
`
`DRAM ———
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 27 0f 43
`
`US 2002/0185337 A1
`
`FIG. 29(A)
`
`
`|__ 70ns *l,
`|__
`115ns___|
`
`EXT. ACCESS ®LOAD |
`53
`| @READ |
`
`|
`
`WAIT _._l
`
`DRAM Elma "5
`
`I
`® READ
`
`FIG. 29(8)
`
`5ns
`I“ 70ns_ 4|
`m access -|- ©me —
`
`11
`
`-
`
`WAIT _.J
`
`DRAM ————ll
`
`5
`
`@HEAD
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 28 0f 43
`
`US 2002/0185337 A1
`
`IWG.30
`
`SRAM
`' AU-A24
`
`J-
`
`70"5
`
`A-.._?9£15__ .il
`
`
`
`DRAM
`
`Di -CLK
`
`
`
`1
`
`DI—COM Ifl.fl.fl..fl.fi-I.IEII
`
`glflm I®I®C®II®I®IC®I®II
`01—000
`
`~Di—DO15
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 29 0f 43
`
`US 2002/0185337 A1
`
`FIG. 31
`
`SHAM
`’ AU-AQO
`
`L____11_5ns
`
`- —-4
`
`
`
`
`___/
`REFRESH iiERIOD
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 30 0f 43
`
`US 2002/018533’? A]
`
`FIG. 32
`
`A9
`
`A0
`
`WL
`
`|
`
`D
`
`|
`
`/D
`
`MA(SRAM)
`
`
`
`1/00 0
`
`1/015.
`
`S-/CE1O
`
`S—CE2 O
`
`CONTROL
`LOGIC
`
`S—/LB 0
`
`S-/UB 0
`S—/WE 0
`
`S-/OE .
`
`F—VCC O—
`
`F—VSS O-——
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 31 0f 43
`
`US 2002/0185337 A1
`
`FIG. 33(A)
`
`CHIP2
`(CTL_LOGIC)
`
`CHIP1
`(FLASH)
`
`PATH3
`
` 000000000
`
`FIG. 33(5)
`
`COVER
`
`PATH1
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 32 0f 43
`
`US 2002/018533? Al
`
`FIG. 34(A)
`
`CHIP?
`(CTL_LOGlC)
`
`CHIP1
`(FLASH)
`
`
`
`FIG. 34(8)
`
`CHIP2
`COVER (CTL_LOGIC)
`
`CHIPS
`(DRAM)
`
`CHIP1
`(FLASH)
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 33 0f 43
`
`US 2002/018533’? A]
`
`FIG. 35
`
`BT’ICAS‘T
`
`"
`
`“IE—mm—vsgg
`
`D1—VC
`
`*D1—VCC
`D1 —CKE-
`311323:
`Hm—vss
`
`
`
`'“D1-DQMU/DQML
`D1I£3VE:'
`
`
`”'“D1—DQO~D1—DQ15
`~D1-A14
`
`
`O A0~A24
`
`0 8—1/OO~S-I/O1 5
`
`34/00
`S-VSS
`PS
`t‘égg
`S—/CE1
`S'CE2
`giVQVEE
`S-/LB
`S-/UB
`RB
`
`
`F
`O F-VCC
`
`
`CHIP?
`F-/OE
`
`(SRAM+CTL_LOGIC)
`_ F-/WE
`
`
`
`CHIP1
`
`F—/HES
`(FLASH)
`
`F——CDE
`_IOO~I/O'f
`
`F— RDY
`
`/ BUSY
`
`
`‘
`
`“H
`
`‘““ D2—VCCO
`
`D2—CLKM**
`0 F—VSS
`
`D2—CKE-~._.—
`D2-VCC
`35‘5825
`“‘02-‘58
`B§Z§%%S:_—
`Eoz—vsso
`
`024m ,w,
`n DZ-DQMU/DOML
`
`~D2—A14
`flD2#DQO~D2—DQ15
`
`
`
`(DRAW)
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 34 of 43
`
`US 2002/0185337 A1
`
`FIG.
`
`36
`
`‘Cu‘ldljil‘f’jggSRAM-i-ICTLLOGIC}
`
`S-/ LB 0
`S-/UB 0
`S—/ WE .
`S—/ CE1 O
`S—CE2 O—
`S—/OE 0
`
`A0~A24 O
`
`S>-
`
`—|unr—-
`
` 'iiiiiiii“
`0.III_—-
`3%SC) I—h_I
`[ET
`
`
`
`
`
`I
`A 0O2 _|
`
`Ia_|
`_|EI
`III-"E5+J
`
`COM
`C) ['11 Z
`
`:' o DI-DQO~D1—DQ15
`H/W
`BUFFER j
`O DE—DQOWDQ—DQIS
`
`r CACHE 3
`
`man(i
`
`0 I/OU~I/O15
`
`o 01—Ao~a1—A14
`o 02—Ao~D—A14
`«- owes
`DT‘CKE
`I D1-/HAS
`o Di-/CAS Di-/WE
`O Di—DQMU/DOML
`o D2-/CS ' Dz'CKE
`. 02 /CAS. D2~/FIAS
`'
`o DZ—/WE
`o D2~DOMU/DQML
`O Di—CLK . DQ—CLK
`° DWCC o U1-Vss
`' D2“VCC o oz—vss
`F-/CE
`F-/OE
`F—/WE
`F—SC
`F-/FIES
`F—/CDE
`1/ OO~I/ OB
`F—RDY/ BUSY
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 35 0f 43
`
`US 2002/0185337 A1
`
`FIG. 37
`
`FLASH
`(256+8)Mb
`
`NIB—Area”:
`
`A1
`'6de
`
`
`
`A2
`2Mb
`
`
`
`
`
`
`
`Fa” Area D __
`Fail Area C
`""""""" -----
`‘
`81
`B2
`
`2Mb
`
`
`K"“‘--.
`
`
`.
`0‘25Mb
`
`
`E2
`
`
`
`
`DRAM
`256Mb ’/
`
`.
`
`FLASH
`Copy Area
`
`' _—
`...................
`
`A0~A24
`
`----------------
`
`WORK Area
`
`E1
`8Mb
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 36 0f 43
`
`US 2002/018533’? A]
`
`BOns
`
`DRAM?
`
`{WORK}
`
`FIG. 38(A)
`EXECUTE (D ONLY
`@EXT. ACCESS
`
`@m -(WRITE BACK) CACHE
`
`
`
`
`
`
`@
`
`©L0AD 8‘
`STORE
`
`?0ns
`
`DRAM2
`
`eee
`
`EXECUTION PRIORITY ®>©>@>©
`
`
`
`FIG. 38(8)
`i
`80ns
`
`@READ
`I
`I
`I
`I
`
`
`
`FIG. 38(0)
`I
`
`I
`
`80ns
`
`
`I
`I
`I
`@WHITE
`@WRITE @meE
`I,
`.
`“a“ \ \‘
`
`I
`
`\
`‘
`
`ns
`
`-
`
`-
`
`-
`
`EXT. ACCESS
`
`IIISIII,
`
`DRAM?
`
`(HER)
`
`EXT. ACCESS
`
`[IVESIIIQ
`I
`(
`DRAM2
`(new
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 37 0f 43
`
`US 2002/018533’? A]
`
`Ex: ACCESS
`
`W;
`
`”(2331?
`
`FIG. 39(A)
`
`.
`BOnS
`@READ
`1
`
`(BREAD
`I
`
`®READ
`I
`
`@HEAD
`1
`
`---
`
`H35
`
`70ns
`
`FIG. 39(3)
`I
`
`80ns
`
`-
`
`-
`
`.
`
`
`i
`1
`l
`l
`(DVERITE
`®W|1|:E
`@VIRITE
`®IIIRITE
`©WRITE |©WRITE |©WRITE [@meE _$WRITE
`70ns
`_
`
` L
`
`EXT. ACCESS
`
`DRAM}
`
`(womq
`[#ng
`
`FIG. 39(0)
`i
`
`80ns
`
`EXT. ACCESS
`
`(REE)
`
`CDWRITE
`I
`
`(DWFHTE
`i
`
`i
`
`1
`©me
`W)
`DRAM2 \ \ \H‘
`L®film 4
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 38 0f 43
`
`US 2002/018533’? A]
`
`FIG. 40(A)
`
`
`Temp<T5°C
`
`___+
`tFlEF=64ms
`
`DRAW
`
`WORK
`
`REF WORK
`
`REF WORK
`
`REF
`
`| 8m '
`
`1
`T1___;
`(REFRESH)
`
`T2
`(WRITE BACK)
`
`.4... T3
`-._|
`(EgAABA “99155530
`
`or
`
`i
`0.5?3ms
`(70nsxa192)
`
`i
`7ms
`(TOnsx 100000)
`
`i
`0.287ms
`(7Dns><4096)
`
`FIG. 40(5)
`
`T1
`
`T2
`
`[F'Onsxs192]
`
`[70n5XtREF/8/80ns]
`
`HIGH
`
`NORMAL
`
`LOW
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 39 0f 43
`
`US 2002/0185337 A1
`
`FIG. 41(A)
`
`DRAW
`
`DRAM2
`
`REF.
`
`----§
`
`
`
`
`
`EXT. ACCESS A
`
`WRITE BACK
`
`CACHE
`
`FIG. 41(3)
`
`dT
`
`DRAW
`
`WORK
`
`i
`
`REF.
`
`WORK
`
`REF.
`
`WORK
`
`EXT. ACCESS B
`
`g WRITE
`
` DHAM2
`fl?
`
`
`1i
`
`CACHE
`
`‘
`
`VALID
`
`l
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 40 0f 43
`
`US 2002/0185337 A1
`
`FIG. 42
`
`SRAM
`AD—A24
`
`
`'
`30n_.S_.
`
`._|_
`
`__8_0.n5-.__.1
`
`1.
`
`
`
`ATD
`
`.
`
`CTD
`‘
`fen-cm
`' D1—COM Inna-amulalnluc'm-m.
`
`k
`i
`mx \
`
`D1 —A0
`
`~D1—A15 IGBIEEIIGDIIIIEEII'IOGDIEBI
`9165108015 Inn-Illlmuumudmolc
`
`.
`
`DRAM2(REF)
`DE—CLK
`
`
`
`REFRESH
`OPERATION
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 41 0f 43
`
`US 2002/0185337 A1
`
`FIG. 43(A)
`
`
`
`PAP-H3CHIP1
`(SHAMEg'II'EQLO‘GIC)
`; (FLASH) ‘
`
`
`
`CHIP4
`(DRAMa
`
`CHIP3
`
`(DRAW)
`
`A—
`
`”9099090"
`----n---
`
`
`--A'
`
`I
`
`PATH1
`
`PATHQ
`
`PATH4
`
`FIG. 43(5)
`
`COVER
`
`PATH1
`
`
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 42 0f 43
`
`US 2002/0185337 A1
`
`FIG. 44(A)
`
`CHIP2
`
`PATH3
`I
`
`CHIP‘i
`
`CHIPS ¥_
`(DRAMH
`
`c
`
`.:
`
`I
`G
`‘-:
`C
`c
`I
`B
`l
`c
`I
`c
`'3
`
`00000
`
`A
`
`A
`
`
`
`
`CH1P4
`~«1DRAM3
`
`"A'
`
`I
`
`a:
`
`,
`
`.
`
`3
`c.
`‘: °
`3
`G
`cl
`9
`9'
`3
`cl
`3
`cl
`3
`
`
`
`
`
`
`In:
`
`PATHS
`
`‘PATH2
`
`PATH4
`
`PATHS
`
`A’
`
`

`

`Patent Application Publication Dec. 12, 2002 Sheet 43 0f 43
`
`US 2002/018533? A]
`
`FIG. 45
`
`ANT
`
`
`
`

`

`US 2002/018533? A1
`
`Dec. 12, 2002
`
`SEMICONDUCTOR DEVICE WITH
`NON-VOLATII.E MEMORY AND RANDOM
`ACCESS MEMORY
`
`CLAIM OI: PRIORITY
`
`[0001] This application claims priority to Japanese Patent
`Application No. 2001474978 filed on Jun. 1], 2001.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`1. Field of the Invention
`
`[0003] The present invention relates to a stacked memory
`semiconductor device that includes various kinds of memo-
`ries, and, more particularly, the present invention relates to
`a combination of said stacked memories, a method for
`controlling those memories, and a structure for integrating
`those memories into a multi-chip module.
`
`[0004]
`
`2. Description of the Background
`
`[0005] The following documents are referenced in this
`specification. The documents are numbered, and hereinafter,
`they will be described with reference to these numbers.
`[“Document 1"]: LR8133? Stacked Chip 32M Flash
`Memory and 4M SRAM Data Sheet (Apr. 21, 2000);
`[“Document 2"]: Oflicial Gazelle of JP-A 29961611991
`(Official Gazette of European Patent No. 566,360, Oct. 20,
`1993); [“Document 3"]: Official Gazette of JP—A 146820!
`1993; and [“Document 4"]: Oflicial Gazette of IP-A 5723i
`2001.
`
`[0006] Document 1 discloses a stacked semiconductor
`memory in which a flash memory (capacity: 32M bits) and
`an SRAM (capacity: 4M bits} are molded together on a
`stacked chip in an FBGA package. The flash memory and the
`SRAM share address input terminals and data ”0 terminals
`connected to the input/output electrodes of the FBGA pack-
`age respectively. However,
`the control
`terminals of the
`memories are independent of each other.
`
`[0007] FIG. 17 in Document 2 shows a stacked semicon—
`ductor memory in which a flash memory chip and a DRAM
`chip are molded together in a lead frame package. FIG. 1 in
`Document 2 shows a stacked memory in which a flash
`memory and a DRAM share address input terminals, data
`IlO terminals, as well as a control terminal connected to the
`inpuli‘output electrodes of the package respectively.
`
`[0008] FIG. 1 in Document 3 shows a system comprised
`of a flash memory used as a main storage, a cache memory,
`a controller, and a CPU.
`
`[0009] FIG. 2 in Document 4 shows a semiconductor
`memory comprised of a flash memory, a DRAM, and a
`transfer control circuit.
`
`[0010] An examination of cellular telephones, as well as
`memory modules used for those cellular phones, confirms
`that, in each of those memory modules, a flash memory and
`an SRAM are mounted together in one package. Cellular
`phones are often provided with various functions (related to
`the distribution of music, games, etc), and the size of the
`corresponding application programs, data, and work areas
`thereof are ever increasing. [t is to be expected that cellular
`phones with larger capacity flash memories and SRAMs will
`soon be needed. Additionally,
`the recent enhancement of
`cellular phone functionalities may also require larger capac-
`ity memories.
`
`Presently, a cellular phone uses a flash memory that
`[0011]
`employs so-called "NOR memory cell arrays.” The NOR
`flash memory employs memory cell arrays that suppress the
`parasitic resistance. The NOR flash memory lowers the
`resistance by providing one through-hole to bit line for two
`cells connected in parallel. This reduces the reading time to
`about 80 ns, which is almost equal to the reading time of a
`large capacity, medium access speed SRAM. On the con-
`trary, because one through-hole to bit line must be provided
`for two cells, the ratio ofthe through—hole to bit line area to
`the chip area increases such that the one-bit memory cell
`area also increases.
`It has been difficult
`to give a large
`capacity to the NOR flash memory. This has been a problem.
`
`[0012] Typical large capacity flash memories are roughly
`classified into two types: AND flash memories that employ
`the AND memory arrays and NAND flash memories that
`employ the NAND memory arrays. In each of these flash
`memories, one through-hole to bit line is formed for 16 to
`123 cells, so that the flash memory can form high density
`memory arrays. Consequently.
`it is possible to reduce the
`one-bit area per memory cell more than that of NOR flash
`memories. A larger capacity can thus be given to those flash
`memories. On the contrary, the reading time for outputting
`the first data becomes about 25 lits to says, so that those flash
`memories can not easily match the read access speed of an
`SRAM.
`
`[0013] A flash memory can keep data even when the
`power supply to the cellular phone (or other device) is shut
`01f. However, power is kept supplied to an SRAM so as to
`hold data therein even when the power to the cellular phone
`is off. To hold data in an SRAM for an extended period of
`time, therefore, the data retention current should be mini—
`mized. Large capacity SRAMs are confronted with prob-
`lems in that the data retention current increases in proportion
`to an increase in the capacity of the memory and the data
`retention current
`increases due to an increase in the gate
`leakage current. This occurs because a tunnel current flows
`to the substrate from a gate when the oxide insulator of the
`MOS transistor is thinned in a micro-machining process
`meant to increase the capacity of the SRAM. As a result, the
`data retention current increases. It has been noted that it is
`increasingly difficult to reduce the data retention current in
`larger capacity SRAMs.
`
`the
`[0014] To address the above-mentioned problems,
`present invention preferably provides a ROM that has an
`increased memory capacity and the ability to read and write
`data quickly, as well as a RAM that has an increased
`memory capacity and requires reduced data retention cur
`rent.
`
`SUMMARY 015 T1113. INVEN'I'ION
`
`In at least one preferred embodiment, the present
`[0015]
`invention provides a semiconductor device comprising: a
`non-volatile memory having a first reading time; a random
`access memory RAM having a second reading time, which
`is more than 100 times shorter than the first reading time; a
`circuit that includes a control circuit that is connected to and
`controls access to both the non-volatile memory and the
`random access memory; and a plurality of inputfoutput
`terminals connected to the circuit.
`
`[0016] The control circuit is preferably adapted such that
`at least part of the data stored in the non-volatile memory
`
`

`

`US 2002/0185337 A1
`
`Dec. 12, 2002
`
`(flash memory) is transferred to the DRAM (random access
`memory) before operation of the device. To write data in the
`non—volatile memory, the data should be initially written to
`the RAM and then written to the non—volatile memory from
`the RAM between access requests from devices located
`outside the semiconductor device. In addition, the control
`circuit may be adapted to control such that refreshment of
`the DRAM is hidden from external when the RAM is a
`DRAM.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`For the present invention to be clearly understood
`[0017]
`and readily practiced. the present invention will he described
`in conjunction with the following figures. wherein like
`rel’erence characters designate the same or similar elements,
`which figures are incorporated into and constitute a part of
`the specification, wherein:
`
`[0018] FIG. I is a block diagram of a memory module of
`the present invention;
`
`[0019] FIG. 2 is a block diagram of the chip 2 shown in
`FIG. I;
`
`[0020] FIG. 3 is an example of address maps of the
`memory module of the present invention;
`
`[0021] FIG. 4 is an example of the address maps of the
`memory module of the present invention;
`
`[0022] FIG. 5 is an example of the operation of the
`memory module of the present invention. executed when the
`module is powered;
`
`flowchart of data transfer from a
`[0023] FIG. 6 is a
`FLASH to a DRAM in the memory module of the present
`invention;
`
`[0024] FIG. 7 is a flowchart of data transfer from the
`DRAM to the FLASII in the memory module of the present
`invention;
`
`[0025] FIGS. 8A and BB are flowcharts of readingj‘writing
`[romtto the DRAM in the memory module of the present
`invention;
`
`[0026] FIG. 9 is an example of the operation of a data
`renewing management circuit CPB shown in FIG. 2;
`
`llowchart of the operation of the
`[0027] FIG. 10 is a
`memory module ofthe present invention, executed when the
`power supply to the module is shut olf;
`
`[0028] FIG. 11 is an example of the operation of the
`DRAM executed with a LOAD command issued from
`external;
`
`[0029] FIG. 12 is an example of the operation of the
`DRAM executed with a STORE command issued from
`external;
`
`[0030] FIGS. 13A and 1313 show an example of reading}
`writing data Eromtto the DRAM in the memory module of
`the present invention;
`
`[0031] FIG. 14 is an example of reading data from the
`DRAM when a read request is issued from external to the
`DRAM while data is read from the DRAM with a STORE
`command;
`
`[0032] FIG. 15 is a block diagram of the FLASH shown
`in FIG. 1;
`
`[0033] FIG. 16 is a timing chart of reading data from the
`FLASH shown in FIG. 15;
`
`[0034] FIG. 17 is another block diagram of the memory
`module of the present invention;
`
`[0035] FIG. 18 is a block diagram of the FLASH shown
`in FIG. 17;
`
`[0036] FIG. 19 is a timing chart for reading data from the
`FLASH shown in FIG. 18;
`
`[0037] FIG. 20 is a block diagram of the DRAM;
`
`[0038] FIG. 21 is another block diagram of the memory
`module of the present invention;
`
`[0039] FIG. 22 is a block diagram of the chip 2 shown in
`FIG. 21;
`
`[0040] FIG. 23 is an example of address maps of the
`memory module of the present invention;
`
`[0041] FIG. 24 is an example of the memory maps of the
`memory module of the present invention;
`
`[0042] FIG. 25 is an example of the operation of the
`memory module of the present invention, executed when the
`module is powered;
`
`[0043] FIG. 26 is an example of the operation of the
`memory module of the present invention, executed when the
`module is powered;
`
`[0044] FIGS. 27A to 27C show an example of the access
`priority order for the operation of the memory module of the
`present invention;
`
`[0045] FIGS. 28A and 2813 show an example of the
`operation of the DRAM, executed with LOAD and STORE
`commands issued from external;
`
`[0046] FIGS. 29A and 298 show an example of the
`operation of the DRAM. executed in response to an access.
`from external while the DRAM is accessed with LOAD and
`STORE commands;
`
`[0047] FIG. 30 is a timing chart for the memory module
`of the present invention;
`
`[0048] FIG. 31 is a timing chart for the memory module
`of the present invention;
`
`[0049] FIG. 32 is a block diagram 01‘ an SRAM;
`
`[0050] FIGS. 3A and 3313 show an example of mounting
`chips on the memory module of the present invention;
`
`[0051] FIGS. 34A and 343 show an example ol‘ mounting
`chips on the memory module of the present invention;
`
`[0052] FIG. 35 is another block diagram of the memory
`module of the present invention;
`
`[0053] FIG. 36 is a block diagram of the chip 2 shown in
`FIG. 35.
`
`[0054] FIG. 37 is an example of memory maps of the
`memory module of the present invention;
`
`[0055] FIGS. 38A to 38C are flowcharts describing a
`process by which the DRAM is accessed and refreshed
`concurrently from external:
`
`

`

`US 2002/018533?‘ A1
`
`Dec. 12, 2002
`
`LA
`
`[0056] FIGS. 39A to 39C are flowcharts describing a
`process by which the DRAM is accessed from external and
`in the memory module of the present invention concurrently;
`
`[0057] FIGS. 40A and 40!} show exemplary DRAM
`refreshing methods;
`
`[0058] FIGS. 41A and 413 are charts which describe a
`process by which an access is taken over when WORK and
`REF. periods are changed over;
`
`[0059] FIG. 42 is a timing chart ofthe memory module of
`the present invention;
`
`[0060] FIGS. 43A and 4313 show an example of mounting
`chips on the memory module of the present invention;
`
`[0061] FIGS. 44A and 443 show an example of mounting
`chips on the memory module of the present invention; and
`
`[0062] FIG. 45 is a block diagram of a cellular phone
`including the memory module of the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVEN’I'ION
`
`It is to be understood that the figures and descrip-
`[0063]
`tions of the present
`invention have been simplified to
`illustrate elements that are relevant for a clear understanding
`of the present invention, while eliminating, for purposes of
`clarity, other elemean that may be well known. Those of
`ordinary skill in the art will recognize that other elements are
`desirable andt‘or required in order to implement the present
`invention. However, because such elements are well known
`in the art, and because they do not
`facilitate a better
`understanding of the present invention, a discussion of such
`elements is not provided herein. The detailed description
`will be provided hereirtbelovir with reference to the attached
`drawings.
`
`the
`the preferred embodiments of
`[0064] Hereunder,
`present invention will be described in detail with reference
`to the accompanying drawings. Although the circuit ele-
`ments of each block in each of the embodiments are not
`specifically limited, the elements are assumed to be formed
`on a semiconductor substrate such as single crystal silicon
`using known integrated circuit techniques, such as CMOS
`(complementary MOS transistor) and the like.
`
`[0065]
`
`First Exemplary Embodiment
`
`[0066] FIG. 1 shows a first embodiment of a memory
`module, which is an example of the semiconductor device of
`the present
`invention. This memory module is preferably
`comprised of three chips. Each of those three chips is now
`described.
`
`[006?] The chip 1 (FLASI'I) is a non-volatile memory.
`This non-volatile memory may be a ROM (Read Only
`Memory}, an EEPROM (Electrically Erasable and Program-
`mable ROM}, a flash memory, or any similar storage ele-
`ment. Atypical example of the non-volatile memory used as
`chip 1 in this embodiment is a NAND flash memory (to be
`described below]
`in the broad sense. The NAND flash
`memory may have a memory capacity of about 256 Mb and
`a reading time (time required between a read request and
`data output) of about 25 ,trs to 50 ,trs. which is comparatively
`slow. On the contrary, the SDRAM used as chip 3 has a large
`memory capacity of about 256 Mb and a reading time of
`about 35 ns. Specifically.
`the reading time of chip 3 is
`
`preferably more than 100 times shorter than that of the chip
`I. This provides an excellent contrast with the NOR flash
`memory whose reading time is about 80 us, which is on the
`same order of magnitude of the reading time ofthe DRAM.
`The present
`invention provides a solution to eflicient
`accesses to memories, like these, with reading times that
`dill'er significantly from each other.
`[0068] The DRAM is preferably divided into various
`kinds such as EDO, SDRAM, DDR-SDRAM, and similar
`types according to differences in the internal configuration
`and the interface type among them. Although any DRAM
`may be used as this memory module,
`this. exemplary
`embodiment employs the SDRAM, which is a
`typical
`DRAM synchronized with aclock. Chip?! (CTL_LOGICJ is
`provided with a control circuit for controlling chips 1 and 3.
`[0069] The present memory module receives addresses
`(A0 to A15), a clock signal (CLK), and command signals
`(CKE, {C8, tRAS, ECAS, fWE, DOMUIDQML} input from
`external.
`it should be noted here that the terms “external"
`and "from external“ refer to devicesfoperations outside of
`the memory module of the present invention. The memory
`module is powered via S-VCC, S-VSS, L-VCC, L-VSS,
`li-VCC. F-VSS. Dl-VCC, and Dl-VSS. The memory mod-
`ule uses D00 to D015 for data inputi‘output. The memory
`module uses a so-called SDRAM interface for operations.
`[0079] Chip 2 supplies signals required to operate chips 1
`and 3. Chip 2 supplies a serial clock (F—SC), addresses (A0
`to A15), flash data {It00 to HOT). and commands (F—CE.
`F—tOE, F—r’WE. FSC, FIRES, FCDE, F—RDYIBUSY) to
`chip I.
`In addition, chip 2. supplies a clock (DI-CLK).
`addresses (DI-A0 to [)l-Al4), commands (tn-(TKE. 01-!
`CS, Dl—IRAS, Dl—tCAS, Dl—fWE, D1~DQMUt’DQML).
`and DRAM data (DI-D00 t0 Dl-DQIS) to chip 3.
`[0071] Hereunder, each command signal will be described
`brielly. The signals input to chip 2 are as follows: the CLK
`is a clock signal; the CKE is a clock enable signal; the iCE
`is a chip select signal;
`the IRAS is a row address strobe
`signal; the (CA8 is a column address strobe signal; the {WE
`is. a write enable signal; and the DOMUTDQML is an ItO
`data mask signal. The signals input to chip 3 are as follows:
`the Dl-CI.K is a clock signal; the DlnCKE is a clock enable
`signal; the Dl-iCS is a chip select signal; the Dl-t’RAS is a
`row address strobe signal; the [)l—iCAS is a column address
`strobe signal; the Dl-leZ is a write enable signal; and the
`Dl-DOMUIDQML is an 110 data mask signal. The signals
`input to chip I are as follows: the F-ECE is a chip enable
`signal; the F-iOE is an output enable signal; the F-XW E is a
`write enable signal; the F-SC is a serial clock signal; the
`F—t’RES is a reset signal;
`the F-CDE is a command data
`enable signal; the F-RDYJBUSY is readyfbusy signal; and
`the It'00 to ”0‘? are [#0 signals used to input addresses, as
`well as inpuh’output data.
`[0072] The control circuit (CTI._I.OGIC) ofchip 2 selects
`a com