(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0023656A1
`Leedy
`(43) Pub. Date:
`Feb. 3, 2005
`
`US 20050O23656A1
`
`(54)
`
`VERTICAL SYSTEM INTEGRATION
`
`Publication Classification
`
`(76)
`
`Inventor: Glenn J. Leedy, Saline, MI (US)
`
`Correspondence Address:
`Michael J Ure
`PO Box 21.87
`Cupertino, CA 95.015-2187 (US)
`
`Appl. No.:
`PCT Fed:
`
`10/485,046
`Aug. 8, 2003
`
`PCT No.:
`
`PCT/US03/25048
`
`Related U.S. Application Data
`Provisional application No. 60/402,112, filed on Aug.
`8, 2002.
`
`
`
`(21)
`(22)
`(86)
`
`(60)
`
`(51) Int. Cl." .......................... H01L 21/44; HO1L 21/50;
`HO1L 23/02
`(52) U.S. Cl. ......................... 257/678; 438/109; 438/106;
`257/686
`
`ABSTRACT
`(57)
`The Vertical System Integration (VSI) invention herein is a
`method for integration of disparate electronic, optical and
`MEMS technologies into a single integrated circuit die or
`component and wherein the individual device layers used in
`the VSI fabrication processes are preferably previously
`fabricated components intended for generic multiple appli
`cation use and not necessarily limited in its use to a specific
`application. The VSI method of integration lowers the cost
`difference between lower Volume custom electronic prod
`ucts and high Volume generic use electronic products by
`eliminating or reducing circuit design, layout, tooling and
`fabrication costs.
`
`SAMSUNG EXHIBIT 1007
`Samsung v. Trenchant
`Case IPR2021-00258
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 1 of 44
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`US 2005/002365.6 A1
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`
`
`FIG - 2A
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`FIG - 2B
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 2 of 44
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`US 2005/002365.6 A1
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`201C
`
`203C
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`202C
`
`-
`
`FIG - 2C
`
`
`
`

`

`Q
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`

`

`Patent Application Publication Feb. 3, 2005 Sheet 4 of 44
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`US 2005/002365.6 A1
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`74a
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`a 72b 71C 76b
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 5 of 44
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`US 2005/002365.6 A1
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`71
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`7b3
`
`FIG - 7B
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`
`
`FIG - 7C
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 6 of 44
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`US 2005/002365.6 A1
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`FIG - 7D
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`
`
`FIG-7F
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`74
`
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 7 of 44
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`US 2005/002365.6 A1
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`81a
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`82a 1
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`82b
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`83
`
`
`
`FIG - 8
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 8 of 44
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`US 2005/002365.6 A1
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`
`
`FIG - 11A
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 9 of 44
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`US 2005/002365.6 A1
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`1101b.
`
`1102b
`
`1103b
`
`FIG - 11B
`
`
`
`1101C
`
`FIG - 11C
`
`

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`Patent Application Publication Feb. 3, 2005 Sheet 10 of 44
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`US 2005/002365.6 A1
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`
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`11d 10
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`FIG - 11D
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 11 of 44
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`US 2005/002365.6 A1
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`
`
`11e4
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`11 e6
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`11 e11
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`11e12
`
`11 e13
`
`11 e 1
`
`11 e5
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`11e31
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`11e22
`
`11 e23
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`11 e2n
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`11e3
`
`FIG - 11E
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`

`

`Patent Application Publication
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`Feb. 3, 2005 Sheet 12 of 44
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`US 2005/002365.6 A1
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`
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`11f
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`11 f52
`
`FIG
`- 11 F
`
`

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`Patent Application Publication Feb. 3, 2005 Sheet 13 of 44
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`US 2005/002365.6 A1
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`
`
`FIG - 11G
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 14 of 44
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`US 2005/002365.6 A1
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`
`
`1205
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 15 of 44
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`US 2005/002365.6 A1
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`1401
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`1403 1402
`
`
`
`FIG - 15A
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 16 of 44
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`US 2005/002365.6 A1
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`1503b
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`1502b
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`1505b.
`
`FIG - 15B
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`
`
`1507C
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`1508C
`FIG - 15C
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 17 of 44
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`US 2005/002365.6 A1
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`1503
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`
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`
`1507d
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`1505
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`FIG - 15D
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`
`1506e
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`1501e
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`FIG - 15E
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 18 of 44
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`US 2005/002365.6 A1
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`1506f
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`1510f
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`1501f
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`1511f
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`1505f
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`1508f
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`1502f
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`
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`1502g
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`FIG - 15G
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 19 of 44
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`1605a
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`US 2005/002365.6 A1
`1604a
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`,
`
`1601a
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`1602a
`FIG - 16A
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`1606b
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`1607b
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`1608b.
`
`1609b.
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`1602b
`FIG - 16B
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 20 of 44
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`US 2005/002365.6 A1
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`
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`1608C
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`FIG - 16C
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 21 of 44
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`US 2005/002365.6 A1
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`1702a
`
`FIG - 17A
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`
`
`1702a
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`FIG - 17B
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 22 of 44
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`US 2005/002365.6 A1
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`1808a
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`1810,
`
`1809a
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`1813a
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`FIG - 18A
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`1803b
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`1805b.
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`1804b2
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`FIG - 18B
`
`

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`Patent Application Publication Feb. 3, 2005 Sheet 23 of 44
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`US 2005/002365.6 A1
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`1907a
`
`1908a.
`
`
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`
`
`444444 47& C
`
`FIG - 19A
`
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`1903b
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`FIG - 19B
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 24 of 44
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`US 2005/002365.6 A1
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`
`
`1901C
`
`
`
`
`
`(2SE
`NZN
`
`
`
`1902d
`
`FIG - 19D
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 25 of 44
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`US 2005/002365.6 A1
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`1901e
`
`A
`
`i FIG - 19E
`
`B
`
`->
`B
`
`--
`
`1902e
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`
`1908e1
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`-
`
`FIG - 19E - AA
`
`1906e1
`
`
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 26 of 44
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`US 2005/002365.6 A1
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`1901f1
`
`
`
`
`
`
`
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`
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`1903f1
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`FIG - 19F1
`
`1901?2
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`1902f2
`
`1903f2
`
`1904f2
`
`19052
`
`1906f2
`
`FIG - 19F2
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 27 of 44
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`US 2005/002365.6 A1
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`1901 f3
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`1908f3
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`1902f3
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`
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`1913f4
`1911f4
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`1912fa
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`FIG - 19F3
`
`1902fa
`1903f4N 1905f4 1901f4 19064
`
`1908fA.
`
`
`
`191Of4
`
`1909fa.
`
`FIG - 19 F4
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 28 of 44
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`US 2005/002365.6 A1
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`
`
`
`
`
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`
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`191Of5 1901 fs
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`1902.f5
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`1909f.5
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`1913fs
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`1907f5
`1912f5
`
`1911 f5
`
`1908.f5
`
`1903f.5
`
`FIG - 19F5
`
`
`
`1902g1
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`1901 g1
`
`1907g1
`
`FIG - 19G1
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 29 of 44
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`US 2005/002365.6 A1
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`1901g2
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`1908g2
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`FIG - 19G2
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`
`
`
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`
`1915g3
`
`1904.g3
`
`1907.g3 1906g3
`1910g3 19099 goes
`
`FIG - 19G3
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 30 of 44
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`US 2005/0023656A1
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`1904.g4
`
`
`
`is 5.
`
`
`
`
`
`1905g4
`1907g4 N1906g4
`1908g4
`1909g4 1910g4
`FIG - 19G4
`
`
`
`
`
`
`
`FIG - 19G5
`
`

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`Patent Application Publication Feb. 3, 2005 Sheet 31 of 44
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`US 2005/002365.6 A1
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`1902h1
`
`1901h1
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`1903h1 1904h 1
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`191Oh1
`
`1905h.1
`
`1907h1
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`1906h1
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`1908h1
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`
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`1909h 1
`
`1912h1
`
`
`
`1911h1
`
`1913h1
`
`FIG - 19H
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 32 of 44
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`US 2005/002365.6 A1
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`2003a
`
`
`
`2001a
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`
`
`FIG - 20A
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`
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`2003C
`
`2003b
`
`2001
`
`FIG - 20B
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`2003C
`
`
`
`2005c
`
`FIG - 20O
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 33 of 44
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`US 2005/002365.6 A1
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`
`
`2006c
`
`2006
`
`FIG - 200
`
`FIG - 20E
`
`2001e 2002e
`
`Dic
`
`-7-7
`
`
`
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`
`
`
`2005f
`
`FIG - 20F
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 34 of 44
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`US 2005/002365.6 A1
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`FIG - 21A
`
`2103a
`
`2101 a E.
`2104a E 2102a
`
`2100b
`
`AL/ \-R-
`E.
`
`asuas-F1)
`FIG - 21B
`
`2105b
`
`2102b
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 35 of 44
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`US 2005/0023656A1
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`2103C
`
`2101C
`
`
`
`2100d 1
`
`21002
`
`2101
`
`2102d
`
`D /
`
`D
`
`2107d 1 N
`
`FIG - 21D
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 36 of 44
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`US 2005/002365.6 A1
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`
`
`2201 a
`
`2204a
`
`FIG - 22A
`
`2205b.
`
`2208b.
`
`2203b
`2204b.
`
`221 Ob
`(
`
`2209
`
`2201) P 2.
`
`a
`
`FIG - 22B
`
`2206b
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 37 of 44
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`US 2005/0023656A1
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`2309a
`
`2302a
`
`2303a
`
`2304a
`
`2305a
`
`2306a
`
`2301 a
`
`FIG - 23A
`
`2307a
`
`
`
`2305b.
`
`2302b
`
`2301C
`
`-
`
`2303C
`
`FIG - 23C
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 38 of 44
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`US 2005/002365.6 A1
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`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`

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`Patent Application Publication Feb. 3, 2005 Sheet 39 of 44
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`US 2005/0023656A1
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`
`
`FIG - 24C
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`

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`Patent Application Publication Feb. 3, 2005 Sheet 40 of 44
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`US 2005/0023656A1
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`
`
`2401d
`
`2402d
`
`2403d
`
`2404d
`
`FIG - 24D
`
`
`
`
`
`2401e
`
`U
`
`TN
`
`- 7 -
`
`IAA
`
`24O2e
`
`2405e
`
`2403e
`FIG - 24E
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 41 of 44
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`US 2005/0023656A1
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`2501 a
`
`2503a
`
`2502a
`
`FIG - 25A
`
`
`
`2503b
`
`FIG - 25B
`
`

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`Patent Application Publication Feb. 3, 2005 Sheet 42 of 44
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`US 2005/0023656A1
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`FIG - 26A
`
`2603a
`
`
`
`2604b.
`
`: 2601 b
`
`2602b
`
`2603b
`
`FIG - 26B
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 43 of 44
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`US 2005/0023656A1
`
`FIG 27
`
`VB1 VB2
`
`27O6
`
`VB3
`
`
`
`2701
`
`O
`
`2702
`
`2703
`
`NP
`Nin
`FGP
`O FFGPm
`CAM 1
`0
`ciM y
`Memory1
`O Memory
`I/O-
`
`2704
`
`2705
`
`I/Os
`Test & Yield
`2707 - Enhancement
`logic
`
`

`

`Patent Application Publication Feb. 3, 2005 Sheet 44 of 44
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`US 2005/0023656A1
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`2810
`
`2812
`
`2803
`
`
`
`

`

`US 2005/0023656 A1
`
`Feb. 3, 2005
`
`VERTICAL SYSTEM INTEGRATION
`0001. The diversity of circuit function and operational
`requirements that underlay the implementation of a broad
`range of integrated circuit applications including what is
`commonly referred to as a SoC System on a Chip demand
`widely varying Semiconductor fabrication processes and/or
`technologies without further consideration being given to
`the integration of optical and MEMS technologies with
`those Semiconductor technologies. Limitations on the elec
`tronic industry's capability to meet these ever greater
`demands has made the implementation of numerous inte
`grated circuit and SoC products impossible or beyond
`acceptable manufacturing costs.
`0002) The Vertical System Integration (VSI) invention
`herein is a method for integration of disparate electronic,
`optical and MEMS technologies into a Single integrated
`circuit die or component and wherein the individual device
`layers used in the VSI fabrication processes are preferably
`previously fabricated components intended for generic mul
`tiple application use and not necessarily limited in its use to
`a Specific application. The VSI method of integration lowers
`the cost difference between lower volume custom electronic
`products and high Volume generic use electronic products by
`eliminating or reducing circuit design, layout, tooling and
`fabrication costs.
`0003) The VSI invention achieves its novel methods of
`integration through high precision alignment and Stacking of
`component layers, fine grain Vertical interconnections, thin
`flexible circuit Substrates fabricated using StreSS-controlled
`dielectricS and low temperature component layer bonding.
`The VSI integration methods are fabrication methods are
`independent of the fabrication process methods used in
`electronic or optical circuit fabrication or MEMS fabrica
`tion.
`0004. The VSI invention enables the integration systems
`or subsystems as a single die or VSI IC which would
`otherwise be collections of multiple planar ICS, optical ICs,
`passive circuit devices and or MEMS. A VSI IC is a stack of
`closely coupled device or component layers the majority of
`which are less than 50 um thick and typically less than 25 tim
`thick. The VSI invention for vertical integration fabrication
`of planar electronic passive and active, optical or MEMS
`device layerS enables on demand fast turn circuit fabrication
`through the use of an inventory of previously fabricated
`generic VSI IC or device layers in combination of various
`proprietary IP generic device layers to achieve custom
`circuitry which, heretofore, would require at a minimum a
`new circuit design, layout and masking before consideration
`of the planar circuit process integration incompatibility of
`various device elements.
`0005. The VSI fabrication methods enable significant
`cost and power reduction and performance enhancement
`through higher levels of integration with higher circuit
`yields than are presently possible with planar circuit fabri
`cation processes. VSI IC device layers are interconnected by
`high density Vertical interconnections which are Scalable So
`that they can be compatible with the on going decreases of
`circuit fabrication geometries used in horizontal intercon
`nections of the planar device layers. The VSI method for
`high density vertical interconnection is enabled through
`wafer to wafer bonding alignment methods capable of
`precisions of less than 25 nm.
`
`0006. The VSI fabrication methods enable the integration
`as one IC or die that are currently System assemblies of
`discreet circuits with the benefit that performance limiting
`circuit interconnect Structures Such as long on on-IC inter
`connections, IC carriers and sockets, PCBs and PCB edge
`connectors are eliminated. The VSI invention enables the
`reuse of post fabrication or inventory circuit device layers
`for multiple IC applications. The primary benefits of the VSI
`technology is a reduction in complexity of IC manufactur
`ing, testing, packaging and an increased in circuit yield
`resulting in a nominal reduction in manufacturing costs of
`approximately 10x and commenSurate with an approximate
`nominal 5x increases in net circuit operating performance.
`0007. The VSI invention enables the implementation of
`SoC circuits which presently cannot be manufactured for the
`commercial or consumer markets due to technological or
`manufacturing costs limitations. This is before consideration
`of the present high costs associated with custom circuit
`tooling, large die Size or the low production quantities.
`
`BACKGROUND OF THE INVENTION
`0008 1. Field of the Invention
`0009. The present invention relates to methods for mak
`ing closely coupled closely aligned Stacked integrated elec
`tronic circuits, optical circuits and MEMS. In particular, the
`present invention relates to methods specific to fabrication
`integration, yield enhancement, performance enhancement,
`power dissipation reduction and cost reduction.
`0010) 2. State of the Art
`0011 Manufacturing Integrated Circuit IC methods are
`most notable for an exponential rate in the integration
`progression of electronic devices per unit area, consistently
`doubling approximately every 18 months over a short forty
`year history. These manufacturing methods are remarkable
`for their abilities of increasing circuit performance while
`Simultaneously reducing circuit cost, power and size, and as
`a result ICS have contributed in no Small measure to today's
`modern way of life.
`0012. The integration progression has repeatedly enabled
`the making of ICs that were not possible or practical only a
`few years earlier. What before prevented the practical imple
`mentation of circuits with 100,000 transistors due to exces
`Sive power dissipation or low fabrication yields, the inte
`gration progression has now enabled practical yields of
`circuits with 100,000,000 transistors and at much lower
`power dissipations despite the dramatic increase in transistor
`count. The integration progression has made possible the
`expectation that ICs with more than 1 billion transistors will
`be in wide spread common use within the next three to four
`yearS.
`0013 The ultimate and widely understood objective of
`the IC integration progression is to reduce all electronic
`Systems or Subsystems composed of multiple ICs to one IC.
`This ultimate IC is often commonly referred to as a SoC
`System on Chip). The result of this objective is ever lower
`cost of manufacturing, higher performance, and hopefully
`therefore, a greater end user utility and social benefit. FIG.
`1 shows in croSS Section a conventional planar IC composed
`of number of IP Intellectual Property circuit blocks 1 a
`which are interconnected by numerous layers of horizontal
`metal interconnect or wiring 1b.
`
`

`

`US 2005/0023656 A1
`
`Feb. 3, 2005
`
`Electronic systems and Subsystems made from
`0.014
`assemblies of Separate planar ICS are performance or cost
`reduction limited foremost by the implementation means for
`off-circuit or off-chip interconnections or I/Os. The perfor
`mance and cost reduction limitations due to IC I/O result
`from manufacturing restrictions in the number of I/Os an IC
`may have, the cost of packaging, the Significantly lower
`transmission performance of off-circuit connections verSuS
`on-circuit connections and the higher power dissipation
`required for off-chip signal transmission. Further, there is
`not presently planar IC fabrication technology that will
`allow the integration onto one planar IC for all of the
`Significantly different IC fabrication processes used to make
`the electronic components of widely used products Such as
`PCs, PDAs or cell phones. This is likely to remain so for the
`foreseeable future, because past demand for greater capa
`bilities from Such electronic products has resulted in greater
`divergence of the IC fabrication processes used to imple
`ment the various types of ICs from which they are made.
`0.015 The usefulness of the integration progression is
`now Strongly challenged by the growing complexity in the
`design, and logical and physical verification development
`and test efforts required to bring ICs to market. The wide
`Spread incorporation of previously designed or off the shelf
`logic functions referred to as IP Intellectual Property is an
`example of efforts being taken to address IC design and
`development complexity. However, the usage of ever greater
`numbers of IP placements across an IC has resulted in
`greater logical, physical and manufacturing interconnection
`complexity.
`0016. The integration progression rate has changed the
`relationship of the primary cost structure components for
`making ICS. The cost of testing ICS is now approaching and
`in a number of cases exceeding IC fabrication cost and the
`cost of IC packaging ranging from 25% to Several times IC
`fabrication cost. The cost dominance of test and packaging
`over IC fabrication increases with each generation of IC
`fabrication technology. It is becoming clear that IC manu
`facturing methods that reduce through IC integration tech
`niques the cost of test and packaging are of most importance.
`0.017. The integration progression is presently challenged
`by the need for methods to integrate as a single die not only
`active electronics, but also passive electronic devices, opti
`cal devices and MEMS Micro-Electro-Mechanical Sys
`tems. This need is particularly evident in networking and
`telecommunication equipment where the Switching of opti
`cal Signals through the conversion of optical signals to
`electronic and back, to optical or electronically controlled
`MEMS of optical mirrors are used. But also in consumer
`products Such as Video devices that use imaging arrayS
`which need higher integration of processing electronics and
`memory or wireleSS communication devices which need
`greater integration of analog and passive circuitry.
`0.018. The primary drivers of the integration progression
`of planar IC manufacturing have been circuit feature size
`reduction through fabrication proceSS methods and
`increased wafer or Substrate diameter. Volume production
`process fabrication methods for the dominate CMOS semi
`conductor technology has presently reached feature sizes of
`0.12 um 120 nm), and wafer sizes of 300 mm 12 inches).
`Methods for forming stacked ICs or stacked IC structures
`
`have been demonstrated and are expected to become one
`more of the primary drivers of the IC integration progres
`Sion.
`IC Stacking methods can be broadly classified as:
`0019)
`0020) 1. Package driven stacked ICs.
`0021 2. Process driven design and fabrication
`Stacked closely coupled ICS.
`0022. The Stacking of ICs through various packaging
`methods or package driven Stacking has a long and varied
`application history that goes back at least twenty years. A
`recent article published in the IEEE Spectrum entitled
`“Packages Go Vertical” by Harry Goldstein, August 2001,
`pages 46-51, is one representative Summary of the more
`recent methods of 3D packaging of Integrated Circuits. The
`primary benefit of package driven Stacking of ICS is reduced
`physical Volume, implemented through the use of conven
`tional ICs with various methods of forming peripheral
`connections from the I/O contacts of each IC to a common
`Set of termination contacts the package envelop enclosing
`the ICS.
`0023 The stacking of ICs through process drive methods,
`typically requires custom designed ICS and wafer level
`processing Steps. The primary benefits of process driven IC
`Stacking are increased performance with Simultaneous
`reductions of cost, Size and power. Process driven Stacked
`ICS can be generally characterized by the following process
`Steps:
`0024. 1. Wafer level bonding with a bonding mate
`rial thickness of a few microns or leSS.
`0025 2. Thinning of wafer circuit layers to less than
`50 um and typically less than 25um and less than 15
`plm.
`0026 3. Vertical through the circuit layer substrate
`interconnections or interconnections that are internal
`to the IC stack.
`0027 Process driven wafer stacking fabrication in the
`above manner will herein also be referred to as Closely
`Coupled Stacked integrated circuits. The Closely Coupled
`Stacked integrated circuit layers of the invention herein are
`thinned to facilitate the fabrication of fine grain vertical
`interconnections passing through the circuit layerS and Sub
`Stantially flexible, and wherein these layers are preferably
`fabricated using low StreSS or StreSS controlled dielectric
`materials. The primary objective of closely coupled wafer
`Stacking is to enhance the integration progression of IC
`fabrication beyond that possible with existing planar wafer
`process fabrication methods and wafer diameter. Closely
`coupled stacked IC prior art by the inventor and referred to
`as 3DS Three Dimensional Structures are U.S. Pat. Nos.
`5,915,167, 6,208,545, 6,133,640, 6,551,857, 6,563,224,
`5,985,693 and 5,654,220.
`0028 Closely coupled wafer bonding requires wafer to
`wafer alignment prior to bonding. Equipment presently
`available has the capability for +1 um wafer to wafer
`alignment. By comparison horizontal interconnection mini
`mum pitch is 0.15 um 150 nm with current state of the art
`Semiconductor processes. The horizontal routing efficiency
`through vertical interconnections is determined by wafer to
`wafer alignment, and is fundamentally important to the
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`Scaling of fine grain vertical interconnections to maintain
`compatibly with reducing horizontal interconnection geom
`etries.
`0029. The state of the art for completed or fabricated
`planar ICS has and presently results in the expectation that
`the utility of a fabricated IC does not allow its reuse for
`Subsequent IC integration in a Single die or Single IC. This
`is to say that Subsequent integration of post-fabricated planar
`semiconductor circuitry with other fabricated ICs that would
`result in device and interconnection integration densities that
`are the same or Similar to any of the planar ICS being
`integrated, and therefore, providing the well known atten
`dant benefits of Single IC integration, is no longer possible.
`Therefore, any and all Subsequent circuit design changes or
`additions placement of circuitry or horizontal interconnect
`routing layers to a completed planar IC requires the IC be
`remade, requiring at a minimum revalidation of electrical
`and functional operation of the circuit, the remaking of mask
`tooling, circuit fabrication and in most cases the obsoles
`cence of previous circuit inventory. This is a clear and
`Significant restriction on the control of cost in the develop
`ment, manufacturing and inventory management of planar
`ICs. Conversely, having the ability to inventory fabricated or
`complete circuitry which can Subsequently be integrated at
`the IC or die level presents a opportunity for cost Savings
`that affects all aspects of IC development and manufactur
`ing, and extends the range of intended end use applications
`beyond that presently possible.
`
`Planar Circuit Integration Progression Limitations
`0030 There presently exists numerous limitations to the
`integration progression of planar ICS, Some of these limita
`tions which are:
`
`1 Die Size in Fabrication, Complexity and
`Performance
`0031. The IC Integration Progression is limited by die
`size. The die Size of planar circuits is limited by current
`Semiconductor fabrication lithographic technology. Die Size
`fabrication lithographic limitations Stem from the maximum
`imaging field size of present Semiconductor lithographic
`processing equipment. The often Sought end objective for
`most electronic products or applications composed of mul
`tiple ICS is to integrate the ICS into a single chip Solution
`referred to generically as a SoCSystem on Chip). The limits
`of circuit integration manufacturing are feature size and
`lithographic Stepper reticle size maximum lithographic
`image size and yield. At this point in time production IC
`feature size is approaching 0.12 um and Stepper reticle
`demagnification size is approximately 25 mm by 30 mm
`which enables presently a die Size limit of approximately
`one Square inch.
`0032) Larger planar ICs, those greater than 100 mm, that
`are fabricated with lithographic processes less than 0.15 um
`are limited in performance by the distances acroSS the
`Surface of a die or chip of Such size resulting in the use of
`additional circuitry to amplify signals that must travel these
`greater distances. Adding further to the complexity of long
`Signal line propagation is the use of lower Voltage levels
`Such as 1.5 V when using 0.15 um fabrication technology
`which result in lower Signal Strength, and Stronger parasitic
`electronic effects due to the use of Smaller lithographic
`
`geometries. And further as a result of large ICS and Smaller
`lithographic geometries, skewed timing of Signals which
`results from the varying distances of circuit Sources makes
`an ever present demand for more precise circuit timing
`analysis and attendant circuit design compensations neces
`Sary to reduce planar circuit Signal skew Sufficiently to bring
`the circuit into acceptable operating ranges without too great
`a reduction in net circuit performance.
`
`2 Levels of Interconnections and Substrate
`Leakage Limit Device Fabrication Density and the
`Use of Complex IP Blocks
`0033. The IC Integration Progression has now reached a
`minimum circuit device feature size of 0.15 um 150 unm
`in Volume production. The end of the IC integration pro
`gression is now anticipated to be Something approaching a
`feature Size of approximately 20 nm. An increase in circuit
`density of approximately 36 times. However, Such circuit
`density gains will be difficult to achieve or to implement
`their effective use without additional horizontal interconnect
`layerS and new methods of power reduction or utilization
`necessary to drive a greater number of low Voltage Signals
`long distances over the Surface of planar circuits. In order to
`implement greater circuit densities resulting from Smaller
`circuit devices, a comparable reduction in the geometries of
`interconnections and an increase in the number of intercon
`nection levels must be achieved. Reduction in power dissi
`pation is necessary to prevent power dissipation from
`becoming a limitation on IC Integration Progression. Reduc
`tion in transistor Substrate leakage could reduce current
`power dissipation by approximately 50%.
`0034. The IC Integration Progression is limited by the
`number of interconnection levels that can be used in a circuit
`design. The number of horizontal wiring levels of a planar
`IC is limited by manufacturing processes, presently nine 9
`layers, which in turn limit the integration density of an IC
`design. Smaller active device circuit geometries and the
`frequent incorporation of hardwired Intellectual Property
`IP in the design of a circuit increases the wiring or
`interconnection complexity between those IP circuit ele
`ments to each other and the rest of the circuitry of an IC. The
`design of most ICS and certainly most large complex ICS
`incorporate IP circuitry into their circuit designs in order to
`Save the time and human resources that would otherwise be
`required in duplicative development of Such circuit IPS.
`Increased die Size and greater use of IPS results most often
`in an increase in the planar horizontal routing intercon
`nection complexity. This interconnect complexity results in
`more layers of interconnections necessary to complete a
`circuit's local and global wiring networks. This interconnect
`complexity is proportional circuit size, resulting in higher
`manufacturing costs.
`0035. The integration progression is physically accom
`plished by the making of ever Smaller circuit devices and
`through the fabrication of denser and denser interconnec
`tions or wiring. Design of most planar circuits posses the
`challenge of routing interconnections from one circuit block
`or functional group of transistors to another circuit block and
`then typically to the portion of the die of the circuit where
`I/O pads or contacts are formed for off circuit or external
`connections. These horizontal interconnections take the
`form of Successive layers first interconnecting adjacent
`circuit devices, then progressing to the interconnection of
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`ever more distant circuit blocks of the circuit. These inter
`connection layers are themselves connected by Structures
`called Vias, or wiring connections typically of less than 1 um
`in length. These horizontal circuit interconnections have
`proved to be the greatest challenge in the design of large
`circuits resulting in a non-Stop evolution of more Sophisti
`cated automatic interconnect routing Software tools for
`completing what is called the physical IC design, and the
`addition of more and more interconnect layerS presently at
`nine 9 and anticipated to exceed twelve 12 by 2005.
`
`4) Limits of SoCs, ASICs and FPGAs.
`0.036 The IC Integration Progression has lead to efforts
`to incorporate all the ICs of a System onto one chip, resulting
`in the reference to such ICs as SoCs System on Chip).
`However, achieving the SoC goal is greatly restricted by the
`limited ability of the semiconductor industry to fabricate
`Single ICS consisting of multiple Semiconductor processes
`Such as 0.5 um analog and 0.18 um logic or DRAM
`processes or multiple semiconductor technologies Such as
`SiGe and GaAs, InP, GaN, etc.).
`0037 Similar problems face the more traditional and
`familiar ASIC and FPGA Field Programmable Gate Arrays
`or CPLD Complex Programmable Logic Devices prod
`ucts. The limitations of ASICs are design complexity due to
`their relentleSS growth in size, and a long and costly of
`product development process. The well established benefit
`of ASIC integration has now also become a limitation that
`requires re-verification and retooling of the entire circuit
`irregardless of the size of a design change and followed by
`prototype fabrication delays measured in months.
`0038. The alternative to ASICs are FPGAs or CPLDs
`with the advantage of a very Short product development
`process, but with the distinct disadvantages verSuS ASICs of
`higher unit circuit cost, lower performance and lower gate
`density. The lower performance and lower gate density of
`FPGAs follows from the interconnect complexity required
`to Support programmable function blocks and the on chip
`programmable routing interconnections for programming of
`the function blocks.
`0039. The development of SoCs, ASICs and FPGAs
`circuits has become increasing capital intensive in terms of
`facility Support and large numbers of highly trained perSon
`nel. The IC integration progression can only guarantee that
`this trend will continue, making the development of these
`circuits the exclusive domain of a few large established
`companies with the result of lessening product diversity,
`competition and the well established economic Vitality that
`flows from the innovation of small enterprise. The result of
`the current trends of the IC integration proceSS is the loSS of
`greater diversity due to the growing capital barrier to market
`entry, this cannot be in the long term public best interest.
`0040 All planar circuits are made from a custom mask
`Set, where a mask Set consists of typically 16 to 32 lithog
`raphy masks. A Single change to one circuit device or the its
`wiring connections in a circuit design of 10s of millions of
`circuit devices will result in the remaking of Several or all
`masks for a planar IC. This in turn results in a requirement
`for timing simulation analysis of the circuit to determine
`anew it operating characteristics and if a failure co