Ulllted States Patent
`[19]
`[11] Patent Number:
`5,915,231
`
`Beffa
`[45 J Date of Patent:
`Jun. 22, 1999
`
`U3005915231A
`
`[54] METHOD IN AN INTEGRATED CIRCUIT
`(IC) MANUFACTURING PROCESS FOR
`IDENTIFYING AND REDIRECTING IC’S
`_
`misN%$28¥%§2%D DURING THEIR
`‘
`Inveuorzt Raymond J- Ma, Boise, Id
`,
`,
`_
`[73] ASSIgneei Micro" TBChm'Ogy, Inc-9 R0156, Td-
`
`[751
`
`5,355,320 10/1994 Erjavic et al.
`.......................... 304/488
`5,420,796
`5/1995 Weling et a1.
`..
`.. 364/468
`
`2451138451 1:233: 2:399 etlal- ~
`-- 322/52:
`,
`,
`e et a . ..........
`/
`o
`
`..
`364/468.28
`5,537,325
`7/1996 lwakiri et al.
`
`5,568,408 10/1996 Maeda .............
`364/580
`2932833 132332 $23???.....
`iii/iSS/ifi
`
`........................... 364/552
`5,801,965
`9/1998 Takagi et al.
`5,844,803
`12/1998 Bcffa .................................. 364/468.28
`5,856,923
`1/1999 Jones et al.
`........................ 364/468.28
`
`[21] Appl‘ No“ 08/806’442
`
`FOREIGN PATENT DOCUMENTS
`
`Feb. 26, 1997
`[22]
`Filed:
`
`. G06F 19/00; G06G 7/6466
`[51]
`Int. Cl.6
`
`[52] 08.0. ....................... 702/118; 364/468.28; 702/82;
`702/117; 438/14
`[58] Field of Search .................................. 702/81, 82, 83,
`702/84, 117, 118, 120, 182; 364/46801,
`468.17, 468.22, 468.24, 468.28; 438/5,
`10, 14’ 16, 17
`
`[56]
`
`References Cited
`US. PATENT DOCUMENTS
`
`4,958,373
`4,967,381
`5,103,166
`5,105,362
`5,217,834
`5,219,765
`592269118
`592569578
`5,271,796
`5,289,113
`5,294,812
`5,301,143
`
`9/1990 Usami et a1.
`............................... 382/8
`101/1990 Lane et al.
`.. 364/551 .01
`4/1992 Jeon et a1.
`324/158 R
`
`/1992 Kotani .......
`364/468
`
`.. 430/30
`6/1993 Higaki
`
`6/1993 Yoshida eta.
`437/8
`
`”993 Baker et a1.
`~~
`395/161
`
`"""" 437/8
`10/1993 C9rley .et al'
`12/1993 lVIIyashita ct al.
`156/626
`2/1994 Meaney et al.
`324/731
`
`...... 257/65
`3/1994 Hashimoto et a1.
`................................ 365/96
`/1994 Ohri et a1.
`
`5074909
`
`3/1993
`
`Japan .
`.
`.
`.
`313712115332”er7171;322:3311“ & Rom
`"
`’
`’
`[57]
`ABSTRACT
`
`.
`.
`.
`.
`An Inventive method of manufacturing IC deVIces from
`semiconductor wafers Includes prov1d1ng the wafers and
`fabricating IC’s on the wafers. At probe, a unique fuse ID is
`
`stored in each IC, and an electronic wafer map is electroni-
`cally stored for each wafer indicating the locations of good
`and bad IC’s on the wafer and the fuse ID’s of the IC’s on
`
`the wafer' EaCh 1C is the“ separated from its wafer F0 form
`an IC die, and the IC dice are assembled Into IC deVIces. At
`the opens/shorts test at the end of assembly, the fuse ID of
`each IC device is automatically retrieved so the wafer map
`of the IC device may be accessed and evaluated to identify
`any IC devices containing bad IC’s that have accidentally
`been assembled into IC devices. These “bad” IC devices are
`discarded, and the remaining IC devices continue on to
`back-end testin
`
`g.
`
`23 Claims, 2 Drawing Sheets
`
`FABRICATION
`
`SEMI-
`CONDUCTOR
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PROBE AND
`PROGRAM
`
`SCRAP
`BIN
`
`
`
`
`
`
`
`FUSE ID'5
`
`
`
`SAMSUNG EXHIBIT 1005
`SAMSUNG EXHIBIT 1005
`Samsung v. Trenchant
`Samsung v. Trenchant
`Case IPR2021-00258
`Case |PR2021-00258
`
`

`

`US. Patent
`
`Jun. 22, 1999
`
`Sheet 1 0f2
`
`5,915,231
`
`10
`
`FABRICATION
`
`12
`
`SEMI-
`CONDUCTOR
`WAFERS
`
`
`
`16
`
`PROBE
`
`
`
`
`
`Fig. 1
`(PRIOR ART)
`
`

`

`US. Patent
`
`Jun. 22, 1999
`
`Sheet 2 0f2
`
`5,915,231
`
`20
`
`FABRICATION
`
`,
`
`24
`
`
`SEMI-
`
`cououcron
`
`WAFERS
`
`
`
`
`22
`
`30
`
`28
`
`
` PROBEAND
`
`PROGRAM
`
`AHH?MMPS
`FUSEHTS
`
`ANDFUSEM)
`DAIA
`
`
`
`32
`
`
`
`
`
`
`
`
`
`
`
`AMWRBDHEEDS
`
`SCRAP
`BM!
`
`36
`
`BACK
`
`$flP
`
`Fig. 2H3
`
`34
`
`

`

`5,915,231
`
`1
`METHOD IN AN INTEGRATED CIRCUIT
`(IC) MANUFACTURING PROCESS FOR
`IDENTIFYING AND REDIRECTING IC’S
`MIS-PROCESSED DURING THEIR
`MANUFACTURE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`The present application is related to: a application having
`Ser. No. 085 91,238, entitled “METHOD AND APARATUS
`[sic] FOR STORAGE OF TEST RESULTS WITHIN AN
`INTEGRATED CIRCUIT,” and filed Jan. 17, 1996 now
`abandoned; a co-pending application having Ser. No.
`08/664,109, entitled “A STRUCTURE AND A METHOD
`FOR STORING INFORMATION IN A SEMICONDUC—
`
`10
`
`15
`
`TOR DEVICE,” and filed Jun. 13, 1996; and an application
`filed Jan. 17, 1997 entitled “METHOD FOR SORTING
`INTEGRATED CIRCUIT DEVICES.”
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`to integrated
`The present invention relates in general
`circuit (IC) manufacturing, and more specifically to methods
`in IC manufacturing processes for identifying and redirect—
`ing IC’s mis-processed during their manufacture.
`2. State of the Art
`
`As shown in FIG. 1, a typical process 10 for manufac-
`turing very small electronic circuits referred to as “Inte-
`grated Circuits” (IC’s) begins with the IC’s being formed or
`“fabricated” on the surface of a wafer 12 of semiconductor
`material, such as silicon. Once fabricated, IC’s are electroni-
`cally probed to determine whether they are functional (i.e.,
`“good”) or nonfunctional (i.e., “bad”), and a computer then
`stores an electronic wafer map 14 of their wafer 12 identi-
`fying the locations of the good and bad IC’s on the wafer 12.
`After being probed, IC’s are sawed from their wafer 12
`into discrete IC dice or “chips” using high-speed precision
`dicing equipment. IC dice identified as good by their wafer
`map 14 are then each “picked” by automated equipment
`from their sawed wafer 12 and “placed” on an epoxy coated
`bonding site of a lead frame, while IC dice identified as bad
`are discarded into a scrap bin 16. The epoxy attaching the
`good IC dice to their lead frames is then allowed to cure, and
`the attached dice are wire bonded to their lead frames using
`high speed bonding equipment. At this point in the process
`10, the lead frames of [C dice are still connected to other
`lead frames.
`
`Once wire bonded, IC dice and their lead frames are
`formed into IC packages using a hot thermosetting plastic
`encapsulant injected into a mold. Leads of the lead frames
`project from the IC packages after encapsulation, and these
`leads are dipped in a cleansing chemical bath in a process
`referred to as “de-flash.” After de-flash, IC packages are
`cured to set their plastic encapsulant, and their projecting
`leads are then electroplated with a lead/tin finish.
`After lead finishing, connections between the lead frames
`of different IC packages are cut
`to “singulate” the IC
`packages into discrete IC devices. Discrete devices are then
`tested in a simple electronic test that checks for “opens” (i.e.,
`no connection) within the devices where connections should
`exist and “shorts” (i.e., a connection) where connections
`should not exist. Devices that fail the opens/shorts test are
`discarded into the scrap bin 16, and devices that pass
`proceed to extensive back-end test procedures where they
`are tested for functionality and operability before being
`shipped to customers.
`
`40
`
`45
`
`60
`
`65
`
`2
`On occasion, bad IC dice are accidentally picked from a
`sawed wafer 12 for subsequent assembly and back-end
`testing as described above. This can happen, for example,
`because a human, software, or electronic error causes the
`automated pick and place equipment described above to
`access the wrong wafer map 14 for a wafer 12. It can also
`happen because of a misalignment, referred to as a “regis-
`tration” error, between the automated pick and place equip-
`ment and a wafer 12. In either case, such accidents typically
`are not detected until the bad IC dice undergo at least some
`backend testing and, as a result, waste back-end testing
`resources. Therefore, there is a need in the art for a method
`of identifying and discarding accidentally assembled IC dice
`before the dice undergo back-end testing procedures.
`As described in US. Pat. No. ’s 5,301,143,5,294,812, and
`5,103,166, some methods have been devised to electroni-
`cally identify IC dice. Such methods take place “off” the
`manufacturing line, and involve the use of electrically
`retrievable identification (ID) codes, such as so-called “fuse
`ID’s,” programmed into individual IC dice to identify the
`dice. The programming of a fuse ID typically involves
`selectively blowing an arrangement of fuses or anti-fuses in
`an IC die so that when the fuses or anti-fuses are accessed,
`they output a selected ID code. Unfortunately, none of these
`methods addresses the problem of identifying and discarding
`accidentally assembled IC dice “on” a manufacturing line.
`SUMMARY
`
`The present invention provides a method that can identify
`and discard accidentally assembled integrated circuit (IC)
`dice “on” an IC manufacturing line before the dice undergo
`back-end testing procedures.
`In one embodiment, the method identifies and redirects
`IC’s that have been mis—processed, such as bad IC’s iden-
`tified at probe that have accidentally been assembled and
`packaged. The method includes storing data, such as an
`electronic wafer map, at probe, for example, in association
`with a unique identification (ID) code, such as a fuse ID, of
`each of the IC’s. The stored data indicates a process flow
`within the IC manufacturing process that each of the IC’s
`should undergo. For example, the stored data may indicate
`that an IC is bad and should be discarded, or that an IC is
`good and should be assembled and packaged.
`As described above, on occasion one or more IC’s do not
`undergo the process [low they should undergo. For example,
`some bad IC’s may proceed through assembly and packag-
`ing rather than being discarded. To check for IC’s that have
`not undergone the process flow they should undergo, the
`present method also includes reading the ID code of each of
`the IC’s at, for example, the opens/shorts test at the end of
`assembly. The data (e.g., the wafer map) stored in associa-
`tion with the ID code of each of the IC’s is then accessed and
`
`evaluated to identify any IC’s that have undergone a process
`flow within the IC manufacturing process that is different
`from the process flow their data indicates they should have
`undergone, such as bad IC’s that have proceeded through
`assembly and packaging. Any IC’s identified as having been
`mis-processed are then redirected within the IC manufac-
`turing process. Thus, for example, bad IC’s that have been
`assembled and packaged may be discarded so they do not
`proceed to back-end testing.
`In another embodiment of the present invention, a method
`of manufacturing IC devices, such as Dynamic Random
`Access Memory Devices (DRAM’s), from semiconductor
`wafers includes providing the semiconductor wafers and
`fabricating IC’s on the wafers. A substantially unique ID
`
`

`

`5,915,231
`
`3
`code, such as a fuse ID, is then stored in each of the IC’s,
`and data is stored in association with the ID code of each of
`the IC’s that indicates a manufacturing process flow that
`each of the IC’s should undergo. Each IC is then separated
`from its wafer to form an IC die, and the IC dice are
`assembled into IC devices, such as wire bond/lead frame
`devices, Chip On Board (COB) devices, or flip-chip devices.
`The ID code associated with each of the IC devices is then
`read, and the data stored in association with the ID code
`associated with each of the IC devices is accessed and
`evaluated to identify any IC devices that have undergone a
`manufacturing process flow that is different from the manu-
`facturing process flow their data indicates they should have
`undergone. These identified IC devices are then redirected
`(e.g., discarded), and the remaining IC devices continue on
`to back—end testing.
`A further embodiment of the present invention comprises
`a method of manufacturing Multi-Chip Modules (MCM’s)
`similar to the method of manufacturing IC devices described
`above.
`
`A stil further embodiment of the present invention com-
`prises another method of manufacturing IC devices from
`semiconductor wafers. The method includes providing the
`semiconductor wafers and fabricating IC’s on the wafers.
`Each IC is electronically probed to identify good and bad
`IC’s on the wafers and then programmed with a unique fuse
`ID. An electronic wafer map is stored for each wafer
`indicating the locations of good and bad IC’s on the wafer
`and associating each IC on the wafer with its fuse ID. Each
`IC is then sawed from its wafer to form a discrete IC die that
`
`is automatically picked and placed on an epoxy coated
`bonding site of a lead frame. The epoxy is allowed to cure,
`and the IC dice are then wire bonded to their respective lead
`frames. Next, the IC dice and their associated lead frames
`are injection molded to form IC packages. Projecting leads
`of the packages are then de-flashed, the packages are cured,
`and the leads are then electroplated. Then, each package is
`singulated to form a discrete IC device, and each device is
`tested for opens and shorts. The fuse ID associated with each
`IC device is then clcctrically retrieved so the wafer map
`stored in association with the fuse ID associated with each
`
`of the IC devices may be accessed and evaluated to identify
`any IC devices that include a bad IC and any IC devices that
`include a good IC. Any IC devices identified as including a
`bad IC are discarded, and any IC devices identified as
`including a good IC proceed to back—end test .
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a flow diagram illustrating a conventional
`integrated circuit (IC) manufacturing process; and
`FIG. 2 is a flow diagram illustrating an IC manufacturing
`process in which accidentally assembled IC dice are iden-
`tified and discarded in accordance with the present invention
`bcforc back-end tcsting.
`DETAILED DESCRIPTION OF THE
`ILLUSTRATED EMBODIMENT
`
`10
`
`15
`
`40
`
`45
`
`As shown in FIG. 2, an inventive method 20 for manu-
`facturing integrated circuits (IC’s) from a group of semi-
`conductor wafers 22 includes the step 24 of fabricating the
`IC’s on the wafers 22. It will be understood by those having
`skill in the field of this invention that the present invention
`is applicable to any IC devices, including Dynamic Random
`Access Memory (DRAM)
`IC’s, Static Random Access
`Memory (SRAM) IC’s, Synchronous DRAM (SDRAM)
`IC’s, processor IC’s, Single In-line Memory Modules
`
`60
`
`65
`
`4
`
`(SIMM’s), Dual In-line Memory Modules (DIMM’s), and
`other Multi-Chip Modules (MCM’s). It will also be under-
`stood that although the present invention will be described
`below in the context of a wire bond/lead frame assembly
`process, the present invention is applicable to any IC assem-
`bly process, including, for example, Chip On Board (COB),
`flip chip, and Tape-Automated Bonding (TAB) processes.
`After fabrication, the IC’s are electronically probed in a
`probe step 28 to evaluate a variety of their electronic
`characteristics, and data from the probe step 28 identifying
`bad and good IC’s are noted and stored as wafer maps 30,
`as described above. During the probe step 28, IC’s fabri-
`cated on the wafers 22 are programmed in the manner
`described above with a fuse identification (ID) unique to
`each IC. The fuse ID for each IC is then stored in association
`with the wafer maps 30 such that each die location on each
`wafer map 30 is associated with the unique fuse ID of a
`particular IC. The fuse ID may identify, for example, a wafer
`lot ID, the week the IC’s were fabricated, a wafer ID, a die
`location on the wafer, and a fabrication facility ID.
`It will be understood, of course, that the present invention
`includes within its scope IC’s having any ID code, including
`those having fiise ID’s. It will also be understood that the
`IC’s may be programmed with their fuse ID’s at steps in the
`manufacturing process 20 other than the probe step 28.
`Once programmed, the IC’s proceed through an assembly
`process 32 to an opens/shorts test 34 as described above. At
`the opens/shorts test 34, the fuse ID of each IC is automati-
`cally read and correlated with the wafer map 30 of its wafer
`22.
`If a bad IC has accidently proceeded through the
`assembly process 32, the fuse ID of the IC, in correlation
`with the wafer map 30 of the IC’s wafer 22, will identify the
`IC as a bad IC so it can be discarded to a scrap bin 36 instead
`of proceeding through back—end testing. The present inven—
`tion thus provides a method of identifying and discarding
`accidentally assembled IC’s before they undergo back-end
`testing.
`It should be understood that although the fiise ID’s of IC’s
`in the process 20 are typically read electronically, they may
`also be read optically if the fuse ID’s consist of “blown”
`laser fuses that are optically accessible. It should also be
`understood that the present invention includes within its
`scope any method in an IC manufacturing process for
`identifying and redirecting IC’s mis-processed during their
`manufacture using ID codes such as fuse ID’s.
`Although the present invention has been described with
`reference to a preferred embodiment, the invention is not
`limited to this embodiment. For example, while the various
`steps of the preferred embodiment have been described as
`occurring in a particular order, it will be understood that
`these steps need not necessarily occur in the described order
`to fall within the scope of the present invention. Thus, the
`invention is limited only by the appended claims, which
`include within their scope all equivalent methods that oper-
`ate according to the principles of the invention as described.
`What is claimed is:
`
`1. A method in an integrated circuit (IC) manufacturing
`process for redirecting one or more IC’s that have been
`mis-processed, the IC’s being of the type to have a substan-
`tially unique identification (ID) code, the method compris-
`ing:
`storing data in association with the ID code of each of the
`IC’s that indicates a process flow within the IC manu-
`facturing process that each of the IC’s should undergo;
`reading the ID code of each of the IC’s;
`accessing the data stored in association with the ID code
`of each of the IC’s;
`
`

`

`5,915,231
`
`10
`
`15
`
`5
`evaluating the data accessed for each of the IC’s to
`identify any IC’s that have undergone a process flow
`within the IC manufacturing process that is different
`from the process flow their data indicates they should
`have undergone; and
`redirecting any IC’s identified as having been mis-
`processed.
`2. The method of claim 1 wherein the step of storing data
`comprises storing the ID code of each of the IC’s in
`association with a die location on an electronically stored
`wafer map.
`3. The method of claim 1 wherein the step of storing data
`comprises storing data at probe.
`4. The method of claim 1 wherein the step of storing data
`comprises storing data in association with the ID code of
`each of the IC’s that indicates each of the IC’s is one of a
`good IC suitable for assembly and back-end testing and a
`bad IC suitable for being discarded.
`5. The method of claim 1 wherein the step of reading the
`ID code of each of the IC’s comprises electrically retrieving '
`a unique fuse ID programmed into each of the IC’s.
`6. The method of claim 1 wherein the step of reading the
`ID code of each of the IC’s comprises optically reading a
`unique ID code provided on each of the IC’s.
`7. The method of claim 6 wherein the step of optically ’
`reading a unique ID code provided on each of the IC’s
`comprises optically reading a unique laser fuse ID pro-
`grammed into each of the IC’s.
`8. The method of claim 1 wherein the step of reading the
`ID code of each of the IC’s comprises reading the ID code
`of each of the IC’s at an opens/shorts test
`in the IC
`manufacturing process.
`9. The method of claim 1 wherein the step of accessing the
`data stored in association with the ID code of each of the
`
`IC’s comprises accessing the data stored in association with
`the ID code of each of the IC’s at an opens/shorts test in the
`IC manufacturing process.
`10. The method of claim 1 wherein the step of evaluating
`the data comprises evaluating the data accessed for each of
`the IC’s to identify any bad IC’s that have accidentally
`undergone an assembly procedure within the IC manufac-
`turing process.
`11. The method of claim 1 wherein the step of evaluating
`the data comprises evaluating the data at an opens/shorts test
`in the IC manufacturing process.
`12. The method of claim 1 wherein the step of redirecting
`any IC’s identified as having been mis—processed comprises
`discarding any IC’s identified as having been mis-processed.
`13. The method of claim 1 wherein the step of redirecting
`occurs before a back—end test procedure within the IC
`manufacturing process.
`14. The method of claim 1 further comprising assembling
`the IC’s into packaged IC devices after the step of storing
`data and before the step of reading the ID code of each of the
`IC’s.
`
`15. A method of manufacturing integrated circuit (IC)
`devices from semiconductor wafers, the method comprising:
`providing a plurality of semiconductor wafers;
`fabricating a plurality of IC’s on each of the wafers;
`causing each of the IC’s on each of the wafers to store a
`substantially unique identification (ID) code;
`storing data in association with the ID code of each of the
`IC’s that indicates a manufacturing process flow that
`each of the IC’s should undergo;
`separating each of the IC’s on each of the wafers from its
`wafer to form one of a plurality of IC dice;
`
`40
`
`45
`
`60
`
`65
`
`6
`assembling each of the IC dice into an IC device;
`reading the ID code associated with each of the IC
`devices;
`accessing the data stored in association with the ID code
`associated with each of the IC devices;
`evaluating the data accessed for each of the IC devices to
`identify any IC devices that have undergone a manu-
`facturing process flow that is different from the manu-
`facturing process flow their data indicates they should
`have undergone;
`redirecting any IC devices identified as having undergone
`a manufacturing process flow that is different from the
`manufacturing process flow their data indicates they
`should have undergone; and
`back-end testing any non-redirected IC devices.
`16. The method of claim 15 wherein the step of fabricat-
`ing a plurality of IC’s on each of the wafers comprises
`fabricating IC’s selected from a group comprising Dynamic
`Random Access Memory (DRAM) IC’s, Static Random
`Access Memory (SRAM)
`IC’s, Synchronous DRAM
`(SDRAM) IC’s, and processor IC’s.
`17. The method of claim 15 wherein the step of causing
`each of the IC’s on each of the wafers to store a substantially
`unique ID code comprises programming each of the IC’s on
`each of the wafers to permanently store a unique fuse ID.
`18. The method of claim 17 wherein the step of program-
`ming each of the IC’s on each of the wafers to permanently
`store a unique fuse ID comprises programming at least one
`of fuses and anti-fuses in each of the IC’s on each of the
`wafers to permanently store a unique fuse ID.
`19. The method of claim 15 wherein the step of assem-
`bling each of the IC dice into an IC device comprises:
`picking each of the IC dice from its wafer;
`placing each of the IC dice onto an epoxy coated bonding
`site of one of a plurality of lead frames;
`curing the epoxy on the bonding site of each of the lead
`frames;
`wire bonding each of the IC dice to its associated lead
`frame;
`injection molding each of the IC dice and its associated
`lead frame to form one of a plurality of IC packages
`each having projecting leads;
`de-flashing the projecting leads of each of the IC pack-
`ages;
`curing each of the IC packages;
`electroplating the projecting leads of each of the IC
`packages;
`singulating each of the IC packages into one of a plurality
`of discrete IC devices; and
`testing each of the IC devices for opens and shorts.
`20. The method of claim 15 wherein the step of assem-
`bling each of the IC dice into an IC device comprises
`assembling each of the IC dice into an IC device selected
`from a group comprising a wire bond/lead frame IC device,
`a Chip-On-Board (COB) IC device, a flip-chip IC device,
`and a Tape-Automated Bonding (TAB) IC device.
`21. A method of manufacturing Multi-Chip Modules
`(MCM’s) from semiconductor wafers, the method compris—
`ing:
`providing a plurality of semiconductor wafers;
`fabricating a plurality of IC’s on each of the wafers;
`causing each of the IC’s on each of the wafers to store a
`substantially unique identification (ID) code;
`storing data in association with the ID code of each of the
`IC’s that indicates a manufacturing process flow that
`each of the IC’s should undergo;
`
`

`

`5,915,231
`
`7
`separating each of the IC’s on each of the wafers from its
`wafer to form one of a plurality of IC dice;
`assembling one or more of the IC dice into each of a
`plurality of MCM’s;
`reading the ID code of each of the IC dice in each of the
`MCM’s;
`accessing the data stored in association with the ID code
`of each of the IC dice in each of the MCM’s;
`evaluating the data accessed for each of the IC dice in
`each of the MCM’s to identify any MCM’s having IC
`dice that have undergone a manufacturing process flow
`that is different from the manufacturing process flow
`their data indicates they should have undergone;
`redirecting any MCM’s identified as having IC dice that
`have undergone a manufacturing process flow that is
`different from the manufacturing process flow their
`data indicates they should have undergone; and
`back-end testing any non-redirected MCM’s.
`22. The method of claim 21 wherein the MCM’s are '
`
`10
`
`15
`
`selected from a group comprising Single In-Line Memory
`Modules (SIMM’s) and Dual In-line Memory Modules
`(DIMM’s).
`23. A method of manufacturing integrated circuit (IC)
`devices from semiconductor wafers, the method comprising:
`providing a plurality of semiconductor wafers;
`fabricating a plurality of IC’s on each of the wafers;
`electronically probing each of the IC’s on each of the
`wafers to identify good and bad IC’s on each of the
`wafers; programming each of the IC’s on each of the
`wafers to store a unique fuse identification (ID);
`storing an electronic wafer map for each wafer that
`identifies the locations of good and bad IC’s on the
`wafer and associates each IC on the wafer With its fuse
`ID;
`
`8
`sawing each of the IC’s on each of the wafers from its
`wafer to form one of a plurality of discrete IC dice;
`automatically picking each of the IC dice from its wafer;
`placing each of the IC dice onto an epoxy coated bonding
`site of one of a plurality of lead frames;
`curing the epoxy on the bonding site of each of the lead
`frames;
`Wire bonding each of the IC dice to its associated lead
`frame;
`injection molding each of the IC dice and its associated
`lead frame to form one of a plurality of IC packages
`each having projecting lcads;
`de-fiashing the projecting leads of each of the IC pack-
`ages;
`
`curing each of the IC packages;
`electroplating the projecting leads of each of the IC
`packages;
`singulating each of the IC packages into one of a plurality
`of discrete IC devices;
`testing each of the IC devices for opens and shorts;
`electrically retrieving the fuse ID associated with each of
`the IC devices;
`accessing the wafer map stored in association With the
`fiise ID associated with each of the IC devices;
`evaluating the wafer map accessed for each of the IC
`devices to identify any IC devices that include a bad IC
`and any IC devices that include a good IC;
`discarding any IC devices identified as including a bad IC;
`and
`
`back-end testing any IC devices identified as including a
`good IC.
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`APPLICATION NO.
`
`: 5,915,231
`: 08/806442
`
`DATED
`INVENTOR(S)
`
`: June 22, 1999
`: Raymond J. Beffa
`
`Page 1 of 2
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`On the title page:
`In item (56) References Cited, LINE 8,
`In item (56) References Cited, LINE 13,
`In item (56) References Cited, LINE 17,
`In item (56) References Cited, LINE 19,
`In item (56) References Cited, LINE 20,
`In item (56) References Cited, LINE 21,
`In item (56) References Cited, LINE 22,
`In item (56) References Cited, LINE 23,
`In item (56) References Cited, LINE 24,
`In item (56) References Cited,
`
`before “10/ 1993” insert --*--
`before “10/ 1994” inse
`--*--
`before “7/1996” insert --*--
`before “10/ 1996” insert --*--
`before “3/1998” insert --*--
`before “9/1998” insert --*--
`before “12/1998” insert --*--
`before “1/1999” insert --*--
`insert --* cited by examiner--
`insert the following US. Patent
`Documents:
`
`--5,440,493
`--5,442,561
`--5,450,326
`--5,483,l75
`--5,495,417
`
`8/1995 Doida--;
`8/1995 Yoshizawa et al.--;
`9/1995 Black--;
`1/1996 Ahmad et al.--; and
`2/1996 Fuduka et al.--.
`
`
`
`
`
`
`
`
`
`change “No. ’s” to --No.’s--
`change “stil” to --still--
`change “test” to --testing--
`change “process” to --method--
`change “process” to --method--
`
`delete “the step of”
`delete “the step of”
`delete “the step of”
`delete “the step of”
`delete “the step of”
`delete “the step of”
`
`
`
`In the specification:
`COLL
`COLL
`COLL
`COLL
`COLL
`
`In the claims:
`
`CLAIM 10, COLL
`CLAIM 11, COLL
`CLAIM 12, COLL
`CLAIM 13, COLL
`CLAIM 14, COLL
`CLAIM 19, COLL
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`APPLICATION NO.
`
`: 5,915,231
`: 08/806442
`
`DATED
`INVENTOR(S)
`
`: June 22, 1999
`: Raymond J. Beffa
`
`Page 2 of 2
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`In the claims (cont’d):
`CLAIM 19, COLUMN 6,
`
`LINE 31,
`
`before “IC” (second occurrence” change
`“an” to --the--
`
`
`
`Signed and Sealed this
`
`Twenty-seventh Day of November, 2007
`
`m W311.”
`
`JON W. DUDAS
`Director ofthe United States Patent and Trademark Oflice
`
`