(12) United States Patent
`Farnworth et al.
`
`USOO684.1883B1
`US 6,841,883 B1
`Jan. 11, 2005
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) MULTI-DICE CHIPSCALE
`SEMCONDUCTOR COMPONENTS AND
`WAFER LEVEL METHODS OF
`FABRICATION
`
`(75) Inventors: Warren M. Farnworth, Nampa, ID
`(US); Alan G. Wood, Boise, ID (US);
`William M. Hiatt, Eagle, ID (US);
`James M. Wark, Boise, ID (US);
`David R. Hembree, Boise, ID (US);
`Kyle K. Kirby, Boise, ID (US); Pete
`A. Benson, Boise, ID (US)
`(73) Assignee: Micron Technology, Inc., Boise, ID
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 37 days.
`
`(*) Notice:
`
`(21) Appl. No.: 10/403,937
`(22) Filed:
`Mar. 31, 2003
`(51) Int. Cl." ................................................ H01L 29/40
`(52) U.S. Cl. ........................................ 257/777; 257/774
`(58) Field of Search ................................. 257/777,774,
`257/618, 686
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,899.921 A 2/1990 Bendat et al.
`5,138.434 A 8/1992 Wood et al.
`5,299,092 A 3/1994 Yaguchi et al.
`5,437,915 A 8/1995 Nishimura et al.
`5,495,667 A 3/1996 Farnworth et al.
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`JP
`JP
`
`11/1992
`4-32O362
`11/1992
`4-32O365
`3/1993
`5-67726
`405082720 A 4/1993
`10-79362
`3/1998
`2000-311.85
`1/2000
`
`
`
`OTHER PUBLICATIONS
`Dexter Electronic Material, Hysol(R) FP4450 Material Prop
`erties, Spec sheet, pp. 1-2, Aug. 20, 1999.
`Dexter Electronic Material, Hysol(R) FP4451. Material Prop
`erties, Spec sheet, pp. 1-2, Aug. 20, 1999.
`Wafer Size CSP Packaging by VPES, Japan Rec Co., Ltd.,
`advertising material, pp. 1-4, 1998.
`Parylene Coating, advertising for Specialty Coating Sys
`tems, pp. 1-2, date unknown.
`Advanced Coating Parylene Conformal Coating Specialists,
`advertising material, pp. 1-7, 1998.
`David Francis & Linda Jardine, “Thin, Wafer-Level pack
`age is made Without Damaging Die”, Chip Scale Review,
`May/Jun. 2002, p. 70.
`Jeffrey C. Demmin, “More Thinning at ICAPS'', Advanced
`Packaging, Mar. 13, 2002.
`U.S. Appl. No. 09/259,143, filed Feb. 26, 1999.
`U.S. Appl. No. 09/640,801, filed Aug. 17, 2000.
`U.S. Appl. No. 09/652,340, filed Aug. 31, 2000.
`U.S. Appl. No. 10/094,161, filed Mar. 6, 2002.
`U.S. Appl. No. 60/425,567, filed Nov. 11, 2002.
`Primary Examiner Roy Potter
`(74) Attorney, Agent, or Firm-Stephen A. Gratton
`(57)
`ABSTRACT
`A Semiconductor component includes a base die and a
`Secondary die Stacked on and bonded to the base die. The
`base die includes conductive Vias which form an internal
`Signal transmission System for the component, and allow the
`circuit side of the secondary die to be bonded to the back
`Side of the base die. The component also includes an array
`of terminal contacts on the circuit Side of the base die in
`electrical communication with the conductive Vias. The
`component can also include an encapsulant on the back Side
`of the base die, which Substantially encapsulates the Sec
`ondary die, and a polymer layer on the circuit Side of the
`base die which functions as a protective layer, a rigidifying
`member and a stencil for forming the terminal contacts. A
`method for fabricating the component includes the Step of
`bonding Singulated Secondary dice to base dice on a base
`wafer, or bonding a Secondary wafer to the base wafer, or
`bonding Singulated Secondary dice to Singulated base dice.
`
`71 Claims, 27 Drawing Sheets
`
`18
`
`NNNNN
`SNNNN NNN
`AAAA
`Ya Y/
`
`
`
`- Kf4c - Ki?k
`
`2
`7 W2
`SYYYSSNN.YYYYY SNSNYS
`
`
`
`26H2
`
`1 OH
`&
`1.
`EYA 12H1
`Z?a Z?a Z:
`22%. 5%-25
`L. A. LA 1"
`2 277
`22-222222
`14OH
`134 14 AH
`138H
`
`SAMSUNG EXHIBIT 1004
`Samsung v. Trenchant
`Case IPR2021-00258
`
`

`

`US 6,841,883 B1
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`5,543,658 A 8/1996 Hosokawa et al.
`.. A 3. E. t st al.
`2Y-- a-2
`arnwor
`5,888.883 A 3/1999 Sasaki et al.
`5,897,337 A
`4/1999 Kata et al.
`6,060,373 A 5/2000 Saitoh
`6,080,602 A 6/2000 Tani et al.
`6,087.845 A 7/2000 Wood et al.
`6,097,087 A 8/2000 Farnworth et al.
`6,107,109 A 8/2000 Akram et al.
`6,114,240 A 9/2000 Akram et al.
`6,118,179 A 9/2000 Farnworth et al.
`6,130,111 A 10/2000 Ikuina et al.
`6,153,448 A 11/2000 Takahashi et al.
`6,169,329 B1
`1/2001 Farnworth et al.
`6,177.295 B1
`1/2001. De Samber et al.
`6,221,751 B1
`4/2001 Chen et al.
`6,233,185 B1
`5/2001. Beffa et al.
`6,235,554 B1
`5/2001 Akram et al.
`6.252.299 B1
`6/2001 Masuda et al.
`6,271,056 B1
`8/2001 Farnworth et al.
`6,281,131 B1
`8/2001 Gilton et al.
`6,294.837 B1
`9/2001 Akram et al.
`6,303.981 B1 10/2001 Moden
`6,303,997 B1 10/2001 Lee
`6,310,390 B1 10/2001 Moden
`6,313,531 B1 11/2001 Geusic et al.
`
`6,314,013 B1 11/2001 Ahn
`6,326.242 B1 12/2001 Brooks et al.
`6,326,698 B1 12/2001 Akram
`6,330,158 B1 12/2001 Akram
`6,338,980 B1
`1/2002 Satoh
`:
`6,340,845 B1
`1/2002 Oda ........................... 257/777
`6,359,456 B1
`3/2002 Hembree et al.
`6,362.529 B1 * 3/2002 Sumikawa et al. ......... 257/777
`6,368.896 B2
`4/2002 Farnworth et al.
`6,368,930 B1
`4/2002 Enquist
`6,372,624 B1
`4/2002 Farnworth et al.
`6,384,487 B1
`5/2002 Smith
`6,400,172 B1
`6/2002 Akram et al.
`6,440,772 B1
`8/2002 Smith
`6,441483 B1
`8/2002 Ak
`2 - - -a-
`al
`6,451,624 B1
`9/2002 Farnworth et al.
`6,465,877 B1 10/2002 Farnworth et al.
`6,472,735 B2 10/2002 Isaak .......................... 257/686
`6,482.576 B1 11/2002 Farnworth et al.
`6,482,674 B1 11/2002 Kinsman
`6,501,165 B1 12/2002 Farnworth et al.
`6,506,625 B1
`1/2003 Moden
`6,507,114 B2
`1/2003 Hui et al.
`6,577,013 B1 * 6/2003 Glenn et al. ................ 257/777
`6,582,992 B2
`6/2003 Poo et al.
`6,614,104 B2
`9/2003 Farnworth et al.
`
`* cited by examiner
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 1 of 27
`
`US 6,841,883 B1
`
`
`
`14
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`18
`
`18 5s
`
`
`
`
`
`
`
`A-N
`
`ZZ2
`
`1/2
`
`N QKNK
`A.
`AZ
`W W
`NSX2N2S
`S5&íSNS
`a Na2 2 Ws 2AZ.
`N.S 25E & Esk-Q
`Neil / v N
`86 24 86
`
`46
`
`FIGURE 1C
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 2 of 27
`
`US 6,841,883 B1
`
`
`
`FIGURE F
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 3 of 27
`
`US 6,841,883 B1
`
`SC 1
`
`3
`
`O Nr)
`
`2A-2E
`FIGURE 2
`
`2A-2E
`
`SC2
`
`5
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`JQ- 3V
`
`FIGURE 3
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 4 of 27
`
`US 6,841,883 B1
`
`38
`
`S. NYSNN-NSNSSSNNasay
`7-
`N
`M
`
`
`
`32
`
`3O
`
`46 1 4
`
`1 4
`46 36 46
`FIGURE 2A
`
`46
`
`J.8
`
`V
`J2
`
`42
`
`48
`
`48
`
`48
`
`48 42
`
`
`
`
`
`38-1
`
`ZZ A.
`
`42 Z
`
`Z2
`
`SKNNRKSNs S&S
`
`Z
`
`Z
`
`
`
`46 1 4
`
`46 36 46
`FIGURE 2B
`
`1 4
`
`
`
`46
`
`3O
`
`46 1 4
`
`1 4
`46 36 46
`FIGURE 2C
`
`46
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 5 of 27
`
`US 6,841,883 B1
`
`
`
`
`
`FIGURE 2D
`
`FIGURE 2E
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 6 of 27
`
`US 6,841,883 B1
`
`28
`
`28
`
`7O 28
`
`62
`
`66
`
`
`
`
`
`
`
`
`
`S23S23NS22.ÉNS
`KNNSNKNNSNKNNSN
`
`
`
`
`
`
`
`NY
`
`56 121
`
`64
`
`56
`
`56
`
`
`
`
`
`28
`
`70 28
`
`
`
`
`
`SYS aNNYNS anaaS Sasan
`
`RNNKNNNSNKNNNNNKNNNNNN
`
`56 12
`
`64
`
`56
`FIGURE 3B
`
`56
`
`6O
`
`58
`
`58 28 68
`
`
`
`
`
`
`
`
`
`68 62
`72
`NPC N A / NYRC1RN-270
`RNKNNSNKNNSNKNNSNNSNN
`
`NNENSENSES
`
`-Naa a
`
`SS Ar SN sha SANaas
`
`
`
`
`
`2O
`
`66
`
`56 12,
`
`64.
`
`56
`FIGURE 3C
`
`56
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 7 of 27
`
`US 6,841,883 B1
`
`28
`7
`2
`
`28
`
`74
`
`62
`
`a Ya Ya YY YYY is £SZ, SaaS
`s
`V
`as a
`RNSKSNNNN&SNNYSNKNNSN
`
`an
`
`NN
`
`Se
`
`SCCSKS
`S2N2N SSS&
`- - -
`
`56 68
`
`56 68
`
`56 68 54
`
`FIGURE 3D
`
`64
`
`
`
`2O
`
`
`
`66
`
`12
`
`
`
`62
`
`
`
`SNSSNNPCNNYNERNNNNNNNXNNN
`52
`SS552SSS
`Nk22 a
`strala
`
`12
`
`66
`
`S2A/2S
`
`70 74 68 28 5s
`
`72
`28 5s
`28 5s
`FIGURE 3E
`
`74
`
`54
`
`6O
`l
`
`76
`
`56
`
`78
`
`56
`
`68
`
`78 64
`6
`8
`
`56
`78
`
`TS
`
`- NL-l-NL / AL-J
`NNNNNNNNSNNNNNSNNNNSCNSN
`&SSS2sa Ysaaa/SS SSS52.YaYa Ya
`12-1 SNKS&S&N 66
`SESNXNESN
`
`
`
`
`
`
`
`701 7, 68 28
`
`5
`8
`
`
`
`8
`
`74
`
`FIGURE 3F
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 8 of 27
`
`US 6,841,883 B1
`
`54
`
`
`
`
`
`
`
`
`
`12
`
`54
`
`12
`
`
`
`NSSSSSSSN
`SZŽEXN/XSWXNS
`
`
`
`
`
`
`
`
`
`
`
`
`
`58 28
`
`58 28
`
`
`
`
`74
`
`FIGURE 3G
`
`8O 56 78
`
`56 78
`
`56 78 8O
`
`
`
`NNNNNNNNN 2& NYNNNSYNNSNSNYSNS
`
`SZXN/XTS/XNS
`
`58
`
`28
`
`58 28
`
`74
`
`66
`
`66
`
`FIGURE 3H
`
`76
`
`78
`
`56 78
`
`82
`
`54
`
`
`
`12
`
`
`
`
`
`a SSSNSN Na Na2 SNYSS is that
`
`NSNSANSAS
`- N
`\,
`\l-
`NNNNNNNNN ENSENSX&
`N&NS&SŠ N 7 KZ ,
`S). NXNE),
`
`
`
`66
`
`
`
`58 28
`
`FIGURE 3I
`
`74
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 9 of 27
`
`US 6,841,883 B1
`
`76
`
`8O 56 78
`
`56 78
`
`82
`
`54
`
`
`
`
`
`12
`
`
`
`NSASA NYX Y.
`NNNA
`S&S&S&S
`S; NEXNXN
`
`NNNNNESNNNNE-SNNNNEN
`
`SN
`
`58 28 N58 28
`
`FIGURE 3J
`
`74
`
`
`
`
`
`
`
`12
`
`3S
`54 NXSWSNWSC
`NM.
`NMI
`NWI
`&SSSSSSSS:S
`SNXNE
`XTS/XSNS
`
`Syranasantra an
`
`S.
`
`S.
`
`58 28
`
`FIGURE 3K
`
`
`
`74.
`
`
`
`3S
`
`SN
`
`
`
`12
`
`
`
`54 SN NSXAN NZN N NW SAS
`WIMM
`SYNNNNNNN NNN’sNNNS
`SNSGS52&GS2NSS5%SS
`SZXN/X/XSNS
`
`7O
`
`68 28
`
`58
`
`28
`
`
`
`2
`5
`8 28
`
`74
`
`FIGURE 3L
`
`66
`
`66
`
`66
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 10 Of 27
`
`US 6,841,883 B1
`
`82
`
`54
`
`
`
`
`
`SNNNNNSNSNNN/SINNNNNNESNYNNSNSNS/SNNNS
`
`66
`
`
`
`
`
`III 98
`II 90
`I 88
`8O
`26
`sal/86 56 S-86 56 yes
`SS S (6S
`2.4%24 Sé
`%
`S) SéSSSéSSK63N
`NESXi NZSSS
`
`
`
`
`
`58 28
`FIGURE 3M
`
`
`
`
`
`74
`
`
`
`
`
`
`
`
`
`
`
`
`
`A.
`46
`s k
`S 99
`Al ZzZ222 2 it. C
`KS S /
`NMI
`NW
`NAC
`SNNNNNNN/SSNNNNNNNNNYN
`s
`as
`52
`&SSS7%
`SSSSS a ra
`12 SNS&KNSKNSK22N. 66
`SNS V SNSS
`RNKNS
`N
`-SZXS/XN/XSS
`
`
`
`
`
`58 28
`58 28
`FIGURE 3N
`
`2O
`
`74
`
`14
`
`I 4824
`
`14
`
`
`
`
`
`
`
`96
`92
`
`46
`24 Six - || Pi,
`EX-Z
`88
`A.
`2W.
`so K
`AZ 22ave 2%zz As
`&SENSENSX&
`is, NY,XYYXSYS.N.
`12 SN3NSKNSKN 66
`SZXNW2XSWXNS
`
`
`
`
`
`
`
`
`
`26
`26
`28 5828
`FIGURE 3O
`
`2O
`
`74
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 11 of 27
`
`US 6,841,883 B1
`
`I
`
`II
`III
`24 58 2646 48
`
`
`
`
`
`
`
`
`
`a NY SN SNYNY/NYNYSY
`SNY
`
`NWCW Wr
`N 3 SešŠ
`XNESN
`SYNN N/ \ V
`S2 /) SW).
`26
`58
`sa? 28
`FIGURE 3P
`
`
`
`
`
`
`
`2O
`
`74
`
`54
`
`66
`
`
`
`94
`56, 86
`
`8O
`12
`66
`
`7O
`16
`
`
`
`56/24 86 56 24 86 14 56 24 86 56 24 86 14
`
`YA,
`
`SSX
`
`GSY
`
`AXS
`
`4. NS aNYNCSSNS MSSSSS/ANSONY
`
`
`
`
`
`
`
`
`
`
`
`N
`NYSSY
`N N
`NFFSS)
`NZ ANZ AI
`W27
`Wir
`Nizzyzer
`ESY2XSYXNXSY2KSYXN
`NYX. ZS 2NXYZZY
`Ni
`Ni
`(Na Ni
`N KKC. 4NNNK. SSN S&N
`NSSESSENSE&SE XNNNN 54
`XYYYYY/N,
`
`6
`58
`80 , 58 26 58
`2
`74
`FIGURE 3Q
`16
`* /56 24 86 56 24 86
`NAAAAA NAAEAAA N
`S2SSXNSES32XSYN
`NYNXX2% K2Y
`X&Y. &2
`-
`ŠišŠEN
`NNNN2NNNNE2 NNNNNNNNYSNNSNYSNNNNNY
`52SSSGS52
`S52
`Z
`SEXASX/SX/SSXSS
`
`TS
`
`94
`56
`
`
`
`
`
`
`
`
`
`2O
`
`as NSYas
`
`
`
`8O
`
`12
`
`58
`26
`26 58
`FIGURE 3R
`
`Z / W 7 V/
`
`74
`
`2O
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 12 of 27
`
`US 6,841,883 B1
`
`
`
`
`
`
`
`26
`
`58 26°58
`
`V
`
`/
`
`26.58 26.58 ao
`
`V
`
`V
`
`SS Sa
`
`SNSS
`
`SSKSSR2S2S3s SS
`NA &\N(A3%xN
`Naf2, SNY,Z), SN
`N
`N
`NNN / /
`/ / / N
`7 (
`zy N.
`
`
`
`
`
`
`
`
`
`26
`
`
`
`1 OO
`56
`26
`58
`26
`
`
`
`2O
`
`
`
`
`
`NAZANAZAKN'
`
`
`
`
`
`
`
`
`
`7, N.
`16
`
`2%NN263RNZXN2(
`&Š&géSS
`As 2 & V7 A W. 2 & W
`N
`/ (
`7 / .
`A 86 24 94 16 86 24
`FIGURE 3T
`
`
`
`N
`N /
`
`
`
`
`
`
`
`26
`
`
`
`26 2.
`
`26
`
`
`
`
`
`RR 2 2x
`
`2 2
`
`R 2 2X
`
`2 27
`
`
`
`
`
`
`
`
`
`$ 2.6%)
`2N, (2)
`NSSNSS
`ŠEŠEŠEŠ,
`LA. A. A. A. at
`NYZ6,3263&NW66X263XN
`NNN 7 (
`/ / / N
`77
`7
`
`
`
`
`
`
`
`54
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 13 of 27
`
`US 6,841,883 B1
`
`1 O
`1 O
`68 15s
`1s 28
`58 / 1 O2
`sa; 28 ss
`58
`1 O2 7o 72
`18272Y /18
`18/io229
`18
`NKNKKSKNK
`26 42 26 42
`26 472: 26 42
`Y12/F
`YMAX \\
`V N
`N22N22NN22N22NS
`SNS S) SSSSS2 naa yS2 SSSMENYSE
`Q&N KSNNN SSNNKNNNSSK2NNSNS
`R.A.A.A.R.A.A.N.
`Nyal ANN, Ely N.
`777,777. ZZZYZZZZZZZZZY2K722 ZZYZZZZZZYZZYZZ2X22 54
`86 244 86 2
`86 244 86\24.942
`24
`4 94
`4.
`56
`56
`56
`1d4 56 16
`FIGURE 3V
`
`K.
`
`22
`
`a
`
`22
`
`T
`
`YN a
`
`
`
`222
`
`2.22%ZN WZ22
`
`222
`
`Y
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 14 of 27
`
`US 6,841,883 B1
`
`2 \%
`% 7O %
`2 2
`2
`28
`56 N SSNSYS
`26
`NNNYSNSAKNNNNNNNNKSNNNNNa
`36-ki, Aze
`N:52, S
`9422 N5A 74- C
`LZIZIN
`
`18P
`
`18P
`
`58
`
`NYZ
`
`2x
`
`277 ACS -
`
`2SG2k
`
`aas
`
`48
`
`46
`46 86 24 86
`FIGURE 4A
`
`58 -10P
`28
`
`68 66 12
`
`26
`22
`48
`16
`
`14
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(2,Z &
`W7 Z3x. 43x7
`N5%. S.
`N
`At A.N.
`13, WZ 3, \
`N N
`
`NNNNNNNKAKNNNNNNNNK2SNNNNNX
`
`A42
`
`2/12
`
`YV
`
`
`
`FIGURE 4B
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 15 of 27
`
`US 6,841,883 B1
`
`
`
`58 - OC
`
`SS s
`W
`W
`W73% (27. Q
`
`A77
`
`2
`
`
`
`
`
`
`
`
`
`
`
`66
`
`-100
`
`
`
`N
`
`A.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`S.22%
`AAAAAAAAAA 777AAAAAAAAAAAAAYA
`SKSSNS
`
`
`
`Zez.
`N
`S
`
`- N
`FIGURE 4D
`Ap
`18
`
`46
`
`1 OE
`
`N 66E
`
`
`
`
`
`26E
`
`56E
`
`12E
`
`26E
`
`14S-1
`
`NNNYNKES&NNNNNNS2&ANN
`ey \
`| t2
`Niazia N
`\72 2.43 a
`N
`All Ali
`Z27,722. 2% as
`Wif Kf
`
`
`
`
`
`
`
`
`
`
`
`NYA
`
`2
`
`1.
`
`MVM
`
`2
`
`
`
`FIGURE4E
`
`as
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 16 of 27
`
`US 6,841,883 B1
`
`18
`
`SNSSK2KSSSNSNK2KNNSNS
`2
`2
`
`
`
`
`
`
`
`e 23. 2.
`- A4Az
`2.
`NYNNNNNY2KNNNNYNNYNY
`136F FIGURE 4F 142F
`
`C
`
`
`
`34F
`
`
`
`
`
`N
`SSSS2SSSK23S
`2
`W
`
`
`
`WS, WSW-94G
`
`
`
`A.
`
`
`
`FIGURE 4G
`
`14C
`
`18
`
`SNkiffsN SyñNS
`A-A as
`Z/2ZZX2, X
`2
`Kff (4 A
`2
`Z27 t2ZZX222
`*
`14 AA FIGURE 4H 138H
`
`
`
`
`
`
`
`7
`
`
`
`
`
`
`
`M77777
`2S232
`NY. NNNNNN, NY SNNN NAS NNN
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 17 Of 27
`
`US 6,841,883 B1
`
`
`
`
`
`
`
`A1
`
`A2
`
`A3O
`
`PR-PARE SECONDARY WAPR 3O
`SINGULATE SECONDARY DICE 14 FROM SECONDARY
`WAFER 30
`
`PREPARE BASE WAFER 54
`
`BOND SECONDARY DICE 14 TO BASE DICE 12 ON BASE
`WAFER 54
`
`SINGULATE COMPONENTS 1 O FROM BASE WAFER 54
`
`FIGURE 5A
`
`
`
`FORM MASK LAYER 42 ON SECONDARY WAFER 3O WITH
`OPENINGS 44. THEREN ALIGNED WITH DE CONTACTS 46
`- (FIG. 2A)
`
`PROBE TEST SECONDARY DICE 14 ON SECONDARY
`WAFER 3O TO DENTIFY GOOD DICE - (FIG. 2A)
`
`FORM UBM LAYERS 48 - (FIG. 2B)
`
`FORM BUMPED CONTACTS 24 ON UBM LAYERS 48
`
`A4
`
`SINGULATE SECONDARY DCE 14 FROM SECONDARY
`WAFER SO - (FIG. 2D)
`
`FIGURE SB
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 18 of 27
`
`US 6,841,883 B1
`
`FORM RDL CONDUCTORS 28 ON BASE WAFER 54
`
`FORM UBM LAYERS 58 ON RDL CONDUCTORS 28
`
`B3
`
`B4
`
`B5
`
`B6
`
`B7
`
`B8
`
`B9
`
`B1 O
`
`B 11
`
`B12
`
`B13
`
`B1 4
`
`FORM POLYMER LAYER 20 (OPTIONAL) - (FIG. 3C)
`
`APPLY PROTECTIVE TAPE 74 - (FIG. 3D)
`
`PARTIALLY FORM VIAS 78 - (FIG. 3E)
`
`THIN BASE WAFER 54 - (FIG. 3F)
`
`ETCH TO COMPLETE AND CLEAN VIAS 78 - (FIG. 3G)
`
`FORM INSULATING LAYERS 80 - (FIG. 3H)
`
`FORM RESIST LAYER 82 - (FIG. 31)
`
`LASER MACHINE TO OPEN NSULATED WIAS 78
`- (FIG. 3J)
`
`FORM CONDUCTIVE MATERAL IN VIAS 78 TO FORM
`CONDUCTIVE VIAS 26 - (FIG. 3K)
`
`FORM BUMPED CONTACTS 86 ON CONDUCTIVE VIAS 26
`- (FIG. 5K)
`
`PROBE TEST BASE DICE 12 ON BASE WAFER 54
`- (FIG. 3L)
`
`STRIP RESIST 82 AND FORM SOLDER TIPS 88
`- (FIG. 3M)
`FIGURE 5C
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 19 of 27
`
`US 6,841,883 B1
`
`C1
`O
`
`C1b
`
`C2
`
`CJS
`
`C4
`
`C5
`
`C6
`
`C7
`
`C8
`
`APPLY UNDERFILL 94 TO BASE WAFER 54 - (FIG. 3N)
`
`STACK GOOD SECONDARY DICE 14 ON BASE DICE 12 -
`(FIG. 3O)
`
`BOND BUMPED CONTACTS 24 ON SECONDARY DICE 14
`TO BUMPED CONTACTS 86 ON BASE DICE 12 (CURE
`UNDERFLL 94) - (FIG. 3P
`
`FORM ENCAPSULANT 16 - (FIG. 3Q)
`
`THIN SECONDARY DICE 14 - (FIG. 3R)
`
`REMOVE PROTECTIVE TAPE 74 - (FIG. 3S)
`
`DEPOSIT CONDUCTIVE MATERAL 1 OO - (FIG. 3T)
`
`REFLOW CONDUCTIVE MATERIAL 1 OO TO FORM TERMINAL
`CONTACTS 18 - (FIG. 3U)
`
`SINGULATE COMPONENTS 1 O FROM BASE WAFER 54
`- (F.G. 3V)
`FIGURE5D
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 20 of 27
`
`US 6,841,883 B1
`
`MINISCUS BUMP/FLIP CHIP BONDER (M8)
`
`PROVIDE SECONDARY WAFER
`3O
`
`PROVIDE BASE WAFER 54
`WITH CONDUCTIVE VIAS 26
`
`FORM UBM LAYERS 48
`
`FORM UBM LAYERS 87
`
`FORM BUMPED CONTACTS 24
`AS MENSCUS BUMPS
`
`FORM BUMPED CONTACTS 86
`AS MENISCUS BUMPS
`
`SINGULATE/SAW
`SECONDARY DICE
`14
`
`
`
`SINGULATE/SAW
`BASE DICE 12
`
`PICK DICE 12, 14
`INTO TRAYS/FILM
`FRAME TAPE
`
`
`
`APPLY UNDERFLL
`LAYER 94 TO
`BASE DICE 12
`
`PLACE
`SECONDARY DICE
`14 N FLIP CHIP
`BONDER
`
`ALGN 8 BOND
`BASE DCE 12 TO
`SECONOARY DICE
`14
`
`PLACE BASE DCE
`12 IN FLP CHIP
`BONDER (M8)
`
`
`
`
`
`
`
`
`
`
`
`
`FORM TERMINAL CONTACTS 18
`USNG BALL BUMPER
`(PAC TECH PREFORMS)
`
`FIGURE 6A
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 21 of 27
`
`US 6,841,883 B1
`
`BALL BUMPER (PAC TECH 80um)AFLIP CHIP BONDER (M8)
`
`PROVIDE SECONDARY WAFER
`3O
`
`PROVIDE BASE WAFER WITH
`CONDUCTIVE VIAS 26
`
`FORM UBM LAYERS 48
`
`FORM UBM LAYERS 87
`
`FORM BUMPED CONTACTS 24
`USING BAL BUMPER
`(PAC TECH 80um)
`
`SINGULATE/SAW BASE DICE
`12
`
`SINGULATE/SAW SECONDARY
`DICE 14
`
`APPLY UNDERFLL LAYER 94
`TO BASE DICE 14
`
`PLACE
`SECONDARY DICE
`1 4 IN FLP CHP
`BONDER (M8)
`
`ALIGN & BOND
`BASE DICE 12 TO
`SECONDARY DICE
`14
`
`PLACE BASE DICE
`14 IN FLP CHIP
`BONDER (M8)
`
`
`
`
`
`FORM TERMINAL CONTACTS 18
`USING BALL BUMPER
`(PAC TECH PREFORMS)
`
`FIGURE 6B
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 22 of 27
`
`US 6,841,883 B1
`
`BALL BUMPER (PACTECH 80un) ABALL BUMPER
`(PAC TECH LAPLACE)
`
`PROVIDE SECONDARY WAFER
`3O
`
`PROVIDE BASE WAFER 54.
`WITH CONDUCTIVE VIAS 26
`
`FORM UBM LAYERS 48
`
`FORM UBM AYERS 87.
`
`FORM BUMPED CONTACTS 24
`USING BALL BUMPER
`(PAC TECH 80um)
`
`PLACE BASE WAFER 54. IN
`BALL BUMPER
`(PAC TECH LAPLACE)
`
`SINGULATE/SAW SECONDARY
`DICE 14
`
`APPLY UNDERFL LAYER 94
`TO BASE WAFER 54
`
`
`
`
`
`
`
`
`
`
`
`
`
`ALIGN SINGULATED
`SECONDARY DICE 14 TO
`BASE DICE 12 ON BASE
`WAFER 54 USING BALL
`BUMPER
`(PAC TECH LAPLACE)
`
`FORM ENCAPSULANT 16
`
`FORM TERMINAL CONTACTS 18
`USING BALL BUMPER
`(PAC TECH PREFORMS)
`
`SNGULATE COMPONENTS 1 O
`FROM BASE WAFER 54
`
`FIGURE 6C
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 23 of 27
`
`US 6,841,883 B1
`
`BALL BUMPER (PAC TECH 80un)/FLIP CHIP BONDER (DATACON)
`
`PROVIDE SECONDARY WAFER
`3O
`
`PROVIDE BASE WAFER 54
`WITH CONDUCTIVE VIAS 26
`
`FORM UBM LAYERS 48
`
`FORM UBM LAYERS 87
`
`FORM BUMPED CONTACTS 24
`USING BALL BUMPER
`(PAC TECH 80um)
`
`PLACE BASE WAFER 54 IN
`FLIP CHP BONDER
`(DATACON)
`
`SINGULATE/SAW SECONDARY
`DCE 14
`
`FORM UNDERFLL LAYER 94
`ON BASE WAFER 54
`
`
`
`
`
`
`
`
`
`
`
`ALIGN SINGULATED
`SECONDARY DICE 14 TO
`BASE DICE 12 ON WAFER 30
`USING FLIP CHP BONDER
`(DATACON)
`
`FORM ENCAPSULANTS 16
`
`FORM TERMINAL CONTACTS 18
`BY STENCLING OR USING
`BALL BUMPER
`(PAC TECH PREFORMS)
`
`SINGULATE COMPONENTS 10
`FROM BASE WAFER 54
`
`FIGURE 6D
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 24 of 27
`
`US 6,841,883 B1
`
`WAFER BONDER (EVG)
`
`PROVIDE SECONDARY WAFER
`3O
`
`PROVIDE BASE WAFER 54
`WITH CONDUCTIVE VIAS 26
`
`FORM UBM LAYERS 48
`
`FORM UBM AYERS 87
`
`FORM BUMPED CONTACTS 24
`USING BALL BUMPER
`(PAC TECH 80um)
`
`PLACE BASE WAFER 54. IN
`WAFER BONDER (EVG)
`
`FORM UNDERFLL LAYER 94
`ON BASE WAFER 54
`
`ALIGN SECONDARY WAFER 30
`TO BASE WAFER 54 USING
`WAFER BONDER (EVG)
`
`FORM TERMINAL CONTACTS 18
`BY STENCLING OR USING
`BALL BUMPER
`(PAC TECH PREFORMS)
`
`
`
`SINGULATE COMPONENTS 1 O
`FROM BASE WAFER 54
`
`FIGURE 6E
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 25 of 27
`
`US 6,841,883 B1
`
`3 DE STACK - MINISCUS BUMPS/FLIP CHIP BONDER (M8)
`
`
`
`
`
`PROVIDE BASE
`WAFER 54-#1
`
`PROVIDE BASE
`WAFER 54-#2
`
`FORM UBM
`LAYERS 87
`
`FORM UBM
`LAYERS 87
`
`FORM BUMPED
`CONTACTS 86 AS
`MNISCUS BUMPS
`
`
`
`SINGULATE/SAW
`BASE DICE 12-#1
`
`
`
`
`
`
`
`SINGULATE/SAW
`BASE DICE 12-#2
`
`FORM UNDERFLL
`LAYER 94 ON
`BASE DICE 12-#2
`
`PLACE BASE DICE
`12-#1 ON FLIP
`CHP BONDER
`(M8)
`
`PLACE BASE DICE
`12-#2 ON FLIP
`CHP BONDER
`(M8)
`
`ALIGN & BOND
`BASE DICE 12-#1
`TO BASE DICE
`12-#2
`
`PROVIDE
`SECONDARY
`WAFER 3O
`
`FORM UBM
`LAYERS 48
`
`FORM BUMPED
`CONTACTS 24 AS
`MINISCUS BUMPS
`
`SINGULATE/SAW
`SECONDARY DICE
`14
`
`PLACE
`SINGULATED
`SECONDARY DICE
`14 ON FLIP CHP
`BONDER (M8)
`
`
`
`ALIGN & BOND
`SECONDARY DICE
`14 TO BASE DICE
`
`
`
`
`
`
`
`
`
`
`
`FORM TERMINAL CONTACTS 18
`USING BALL BUMPER
`(PAC TECH PREFORMS)
`
`FIGURE 6F
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 26 of 27
`
`US 6,841,883 B1
`
`3 DIESTACK - BALL BUMPER OR MINISCUS BUMPS/FLIP
`CHIP BONDER (M8) OR (DATACON)
`
`
`
`
`
`
`
`
`
`PROVIDE BASE
`WAFER 54-#1
`
`FORM UBM
`LAYERS 87
`
`FORM BUMPED
`CONTACTS 86 BY
`WAVE SOLDERING
`
`PROVIDE BASE
`WAFER 54-#2
`
`FORM UBM
`LAYERS 87
`
`SINGULATE/SAW
`BASE DICE 12-#2
`
`
`
`
`
`
`
`
`
`
`
`
`
`SINGULATE/SAW
`BASE DICE 12-#1
`
`FORM UNDERFLL
`LAYER 94
`
`PLACE BASE DICE
`12-# 1 IN FLIP
`CHP BONDER
`
`PLACE BASE DICE
`12-#2 IN FLIP
`CHP BONDER
`
`
`
`
`
`PRE-SOLDER
`PLATED DISCRETE
`COMPONENTS
`
`ALIGN & BOND
`BASE DICE
`
`
`
`
`
`
`
`
`
`
`
`
`
`PROVIDE
`SECONDARY
`WAFER 3O
`
`FORM UBM
`LAYERS 48
`
`FORM BUMPED
`CONTACTS 24 BY
`WAVE SOLDERING
`
`SINGULATE/SAW
`SECONDARY DICE
`14
`
`PLACE
`SECONDARY DICE
`1 4 IN FLP CHIP
`BONDER
`
`ALIGN & BOND
`SECONDARY DICE
`14 TO BASE DCE
`12-#1 & #2
`
`FORM TERMINAL CONTACTS 18
`USING BALL BUMPER (PAC
`TECH PREFORMS
`FIGURE 6G
`
`

`

`U.S. Patent
`
`Jan. 11, 2005
`
`Sheet 27 Of 27
`
`US 6,841,883 B1
`
`1 O6
`
`1 O or 1 OP
`
`
`
`
`
`
`
`FIGURE 7A
`
`1 O8
`
`1 O Or 1OP-N-
`
`1 O6 N
`
`
`
`1 1 O
`
`18 Or 8P
`
`is
`
`114 FIGURE 7B N108
`
`

`

`US 6,841,883 B1
`
`1
`MULTI-DICE CHP SCALE
`SEMCONDUCTOR COMPONENTS AND
`WAFER LEVEL METHODS OF
`FABRICATION
`
`2
`In an illustrative embodiment, the base die includes a
`circuit Side, a backside, a Semiconductor Substrate with
`integrated circuits, and conductive Vias in the Semiconductor
`Substrate. The Secondary die includes a circuit Side, a back
`Side, a Semiconductor Substrate with integrated circuits, and
`bumped contacts on the circuit Side. The bumped contacts on
`the Secondary die are bonded to the base die in electrical
`communication with the conductive Vias. The conductive
`Vias and the bumped contacts form an internal Signal trans
`mission System for the component, and allow the circuit Side
`of the secondary die to be bonded to the back side of the base
`die.
`The component also includes an array of terminal contacts
`on the circuit Side of the base die in electrical communica
`tion with the conductive Vias. In addition, the component
`includes an underfill layer attaching the base die to the
`Secondary die and can include an encapsulant on the back
`Side of the base die for protecting the Secondary die. The
`component can also include a polymer layer on the circuit
`Side of the base die which functions as a protective layer, a
`rigidifying member and a stencil for forming the terminal
`COntactS.
`An alternate embodiment component includes multiple
`Secondary dice, Such as a first Secondary die and a Second
`Secondary die, Stacked and bonded to one another and to a
`base die. In this embodiment the first secondary die includes
`conductive Vias, and the Second Secondary die can be
`bonded to the conductive vias. Another alternate embodi
`ment component includes a base die which functions as an
`interconnect element with no integrated circuitry. Another
`alternate embodiment component includes multiple base
`dice Stacked and bonded to one another, and a cap plate
`bonded to one of the base dice. The cap plate includes
`conductors that electrically connect Selected contacts (e.g.,
`power contacts and ground contacts) on the base dice to one
`another. AS another alternative, the cap plate can include
`electronic components Such as capacitors in a desired circuit
`pattern.
`An illustrative wafer level method for fabricating the
`component includes the Step of providing a Secondary wafer
`containing the Secondary dice, and the Step of providing a
`base wafer containing the base dice. The Secondary wafer is
`initially processed to form the bumped contacts, and other
`elements as well, and the completed Secondary dice are
`Singulated from the Secondary wafer. Prior to Singulation the
`Secondary dice can be tested on the Secondary wafer using
`wafer level test procedures. The Secondary dice can also be
`tested and burned-in following Singulation and certified as
`known good dice (KGD).
`The base wafer is initially processed to form the polymer
`layer, the conductive Vias, the bumped contacts, and other
`elements as well. In addition, the base wafer can be ground,
`polished or etched to thin the base dice, and facilitate
`formation of the conductive vias. Further, the base dice on
`the base wafer can be tested using wafer level test proce
`dures.
`Following initial processing and testing of the base wafer,
`the Singulated Secondary dice are bonded to the base dice on
`the base wafer. The bonding Step can include formation of an
`underfill layer on the base wafer, and reflow or conductive
`adhesive bonding of the bumped contacts on the Secondary
`dice, to the bumped contacts on the base dice. The bonding
`Step can also be performed by bonding the Secondary wafer
`to the base wafer, or by bonding Singulated Secondary dice
`to Singulated base dice. Following the bonding Step, the
`Secondary dice on the base wafer can be thinned by grinding,
`
`FIELD OF THE INVENTION
`This invention relates generally to Semiconductor manu
`facture and packaging. More particularly, this invention
`relates to multi-dice Semiconductor components, to methods
`for fabricating the components, and to Systems incorporating
`the components.
`
`BACKGROUND OF THE INVENTION
`Semiconductor manufacturers have developed
`components, Such as packages and BGA devices, which
`contain multiple Semiconductor dice. For example, Systems
`in a package (SIP) include multiple dice having different
`configurations, Such as a memory, a processing, or an
`application Specific configuration. The multiple dice provide
`increased integration, Security and performance in a com
`ponent.
`One aspect of these multi-dice components is that they
`typically have a relatively large peripheral outline and
`thickness. For example, conventional Systems in a package
`have two or more dice spread out on a common Substrate.
`These components are typically larger than conventional
`plastic Semiconductor packages. It would be desirable to be
`able to fabricate Semiconductor components, Such as pack
`ages and BGA devices, with multiple dice, but also with a
`chip Scale outline and thickness.
`At the same time, components need a reliable and efficient
`internal Signal transmission System, and a high input/output
`capability. One aspect of conventional chip Scale
`components, Such as chip Scale packages (CSP), is that they
`are difficult to manufacture with the reliability required in
`the industry. For example, Some chip Scale components
`include relatively complicated Signal transmission Systems,
`Such as beam leads and wire conductors. These signal
`transmission Systems are difficult to manufacture, and are
`prone to failure, particularly at the high pin counts required
`for demanding electronics applications. It would be desir
`able for a multi-dice component to have a reliable Signal
`transmission System capable of Volume manufacture.
`The present invention is directed to a multi-dice compo
`nent having a chip Scale outline, an integrated internal Signal
`transmission System, and a high input-output capability. In
`addition, the present invention is directed to wafer level
`methods for fabricating multi-dice, chip Scale components.
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`SUMMARY OF THE INVENTION
`In accordance with the present invention, multi-dice Semi
`conductor components, wafer level methods for fabricating
`the components, and Systems incorporating the components
`are provided.
`The component includes a base die, and a Secondary die
`stacked on and bonded to the base die. The base die
`functions as an interconnect and Support element for pack
`aging the Secondary die, but can also include integrated
`circuits, Such that the component can be configured as a
`System in a package. The component has a chip Scale outline
`(footprint) substantially identical to that of the base die. In
`addition, both the base die and the Secondary die can be
`thinned, Such that even with Stacked dice, the component
`can have a chip Scale thickness (profile).
`
`55
`
`60
`
`65
`
`

`

`3
`polishing or etching, and the terminal contacts formed on the
`base dice. The completed components, each of which
`includes a base die and a Stacked Secondary die, are then
`Singulated from the base wafer.
`An alternate embodiment wafer level fabrication method
`includes the Steps of processing the base wafer and the
`Secondary wafer, bonding the base wafer to the Secondary
`wafer, and then Singulating the components from the bonded
`wafers. AS another alternative fabrication method, the base
`wafer can be processed and Singulated into the base dice,
`and the Singulated Secondary dice attached to the Singulated
`base dice.
`The component can be used to construct various electrical
`Systems. Such as module Systems, Systems in a package
`(SIPs), computer Systems, camcorder Systems, camera
`Systems, cellular telephone Systems, and medical device
`Systems.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1A is an enlarged schematic bottom view of a
`component constructed in accordance with the invention;
`FIG. 1B is a enlarged schematic side elevation view of the
`component,
`FIG. 1C is an enlarged Schematic croSS Sectional view of
`the component taken along section line 1C-1C of FIG. 1A;
`FIG. 1D is an enlarged Schematic croSS Sectional view of
`the component taken along section line 1D-1D of FIG. 1C:
`FIG. 1E is an enlarged Schematic croSS Sectional view of
`the component taken along section line 1E-1E of FIG. 1C:
`FIG. 1F is an enlarged Schematic cross Sectional view of
`the component taken along section line 1F 1F of FIG. 1C:
`FIG. 2 is a plan view of a secondary wafer used in the
`fabrication of the component;
`FIGS. 2A-2E are schematic cross sectional views taken
`along section line (2A-2E)-(2A-2E) of FIG. 2 illustrating
`Steps performed on dice on the Secondary wafer during
`fabrication of the component;
`FIG. 3 is a plan view of a base wafer used in the
`fabrication of the component;
`FIGS. 3A-3P are schematic cross sectional views taken
`along section line (3A-3P)-(3A-3P) of FIG. 3 illustrating
`Steps performed on a die on the base wafer during fabrica
`tion of the component with three different embodiments (I,
`II, III) illustrated in FIGS. 3M-3P;
`FIGS. 3O-3V are schematic cross sectional views taken
`along section line (3A-3P)-(3A-3P) of FIG. 3 illustrating
`Steps performed on dice on the base wafer during fabrication
`of the component using embodiment II in FIGS. 3M-3P;
`FIG. 4A is a Schematic croSS Sectional view equivalent to
`FIG. 1C of an alternate embodiment component having
`terminal contacts which comprise pins,
`FIG. 4B is a schematic cross sectional view equivalent to
`FIG. 1C of an alternate embodiment component having two
`Secondary dice Stacked and bonded to one another and to a
`base die;
`FIG. 4C is a Schematic croSS Sectional view equivalent to
`FIG. 1C of an alternate embodiment component having
`direct connect base die with no redistribution layer;
`FIG. 4D is a schematic cross sectional view equivalent to
`FIG. 1C of an alternate embodiment component having a
`center connect Secondary die;
`FIG. 4E is a Schematic croSS Sectional view equivalent to
`FIG. 1C of an alternate embodiment component having an
`interconnect base die and Stacked Secondary dice;
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 6,841,883 B1
`
`4
`FIG. 4F is a schematic cross sectional view equivalent to
`FIG. 1C of an alternate embodiment component having
`Stacked base dice and a cap plate;
`FIG. 4G is a Schematic croSS Sectional view equivalent to
`FIG. 1C of an alternate embodiment component having an
`underfill layer configured as an encapsulant;
`FIG. 4H is a schematic cross sectional view equivalent to
`FIG. 1C of an alternate embodiment component having
`Stacked base dice and a cap plate with electronic compo
`nents thereon;
`FIG. 5A is a flow diagram illustrating broad steps in the
`fabrication method;
`FIG. 5B is a flow diagram illustrating steps performed on
`the Secondary wafer in the fabrication method;
`FIG. 5C is a flow diagram illustrating steps performed on
`the base wafer in the fabrication method;
`FIG.5D is a flow diagram illustrating steps for mounting
`the Secondary dice to the base dice on the base wafer;
`FIGS. 6A-6G are flow diagrams illustrating steps of the
`fabrication method performed using different Semiconductor
`fabrication equipment;
`FIG. 7A is a schematic plan view of a module system
`incorporating components constructed in accordance with
`the invention;
`FIG. 7B is a schematic cross sectional view of the module
`system taken along section line 7B-7B of FIG. 7A,
`FIG. 8 is a schematic cross sectional view of a system in
`a package incorporating components constructed in accor
`dance with the invention;
`FIG. 9 is a schematic cross sectional view of a computer
`System incorporating components constructed in accordance
`with the invention;
`F