Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`v.
`TRENCHANT BLADE TECHNOLOGIES LLC.
`Patent Owner
`
`__________________
`Case IPR2021-00258
`U.S. Patent No. 7,494,846
`__________________
`
`DECLARATION OF VIVEK SUBRAMANIAN, PH.D.
`ON BEHALF OF PETITIONER
`
`
`CLAIMS 1-16
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`

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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`TABLE OF CONTENTS
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`Page
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`I. 
`
`Relevant Law ................................................................................................... 5 
`
`A. 
`
`B. 
`
`C. 
`
`Person of Ordinary Skill in the Art ....................................................... 5 
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`Claim Construction ............................................................................... 6 
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`Anticipation ........................................................................................... 7 
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`D.  Obviousness ........................................................................................... 7 
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`II. 
`
`Summary of Opinions .................................................................................... 10 
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`III.  Overview of the ’846 Patent .......................................................................... 10 
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`A. 
`
`B. 
`
`The ’846 Patent Specification ............................................................. 13 
`
`Summary of the Prosecution History of the ’846 Patent .................... 17 
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`IV.  Overview of the Primary Prior Art Reference ............................................... 20 
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`A.  Overview of Matsuo ............................................................................ 20 
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`V. 
`
`Level of Ordinary Skill in the Art ................................................................. 25 
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`VI.  Claim Construction ........................................................................................ 25 
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`VII.  Specific Grounds for Challenge .................................................................... 26 
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`A.  Ground I: Matsuo Anticipates Claims 1, 3, 8, 9 and 11. ..................... 26 
`
`1. 
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`2. 
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`3. 
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`4. 
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`Claim 1 ...................................................................................... 26 
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`Claim 3 ...................................................................................... 49 
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`Claim 8 ...................................................................................... 51 
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`Claim 9 ...................................................................................... 52 
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`5. 
`
`Claim 11 .................................................................................... 54 
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`B. 
`
`Ground II: Matsuo in combination with Farnworth renders
`obvious claims 4-7............................................................................... 54 
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`1. 
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`2. 
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`3. 
`
`Claim 7 ...................................................................................... 54 
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`Claims 4 and 5 ........................................................................... 57 
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`Claims 4 and 6 ........................................................................... 63 
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`C. 
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`Ground III: Matsuo in combination with Beffa renders obvious
`claim 10. .............................................................................................. 68 
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`1. 
`
`Claim 10 .................................................................................... 68 
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`D.  Ground IV: Matsuo in combination with Trezza renders obvious
`Claims 2, 12-14 and 16. ...................................................................... 70 
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`1. 
`
`2. 
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`3. 
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`4. 
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`5. 
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`Claim 2 ...................................................................................... 70 
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`Claim 12 .................................................................................... 80 
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`Claim 13 .................................................................................... 94 
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`Claim 14 .................................................................................... 96 
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`Claim 16 .................................................................................... 97 
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`Ground V: Matsuo in combination with Leedy renders obvious
`claim 8. .............................................................................................. 100 
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`1. 
`
`Claim 8 .................................................................................... 100 
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`Ground VI: Matsuo in combination with Suh renders obvious
`claims 4 and 5. ................................................................................... 103 
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`1. 
`
`Claims 4 and 5 ......................................................................... 103 
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`E. 
`
`F. 
`
`G.  Ground VII: Matsuo in combination with Trezza and Beffa
`renders obvious claim 15. .................................................................. 105 
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`1. 
`
`Claim 15 .................................................................................. 105 
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`VIII.  Availability for Cross-Examination ............................................................ 106 
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`IX.  Right to Supplement .................................................................................... 107 
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`X. 
`
`Jurat .............................................................................................................. 108 
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
`
`I, Vivek Subramanian, declare as follows:
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`
`
`1.
`
`2.
`
`My name is Vivek Subramanian.
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`I received a B.S. degree in Electrical Engineering from the Louisiana
`
`State University in 1994. I received M.S. and Ph.D. degrees in Electrical
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`Engineering from Stanford University in 1996 and 1998, respectively. Between
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`1998 and 2000, I was a postdoctoral visiting research engineer at the University of
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`California, Berkeley, where I specifically worked on a DARPA-funded project
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`where part of my activities involved chip stacking technology.
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`3.
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`Through most of my career, I have been active in semiconductor
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`technology development, including in chip stacking technology and through silicon
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`via technology. In 1998, I co-founded Matrix Semiconductor, Inc., a company
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`that developed high density memory technology. Between 2008 and 2011, I
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`served as the Chief Technical Advisor for QuSwami, Inc., a startup company that
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`developed an energy conversion device. In 2004, I co-founded Kovio, Inc., a
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`startup company in the printed electronics space. I served as a Scientific advisor
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`for Kovio between 2004 and 2013. In 2014, I co-founded Locix, Inc., a startup
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`company in the area of wireless networking and imaging systems. I have served as
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`Chief Technical Officer of Locix from 2014 through the present.
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`4.
`
`I have been an independent consultant in the semiconductor industry
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`since 2000, focusing, among other things, on memory technology.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`5.
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`Since 2000, I have been a faculty member in the Electrical
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`Engineering and Computer Sciences Department at the University of California,
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`Berkeley. I was an Assistant Professor from 2000 to 2005, an Associate Professor
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`from 2005 to 2011, and a Professor from 2011 to 2020. Between July 2018 and
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`2020, I was also a Chancellor’s Professor, which is an honor bestowed upon a
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`limited number of professors by the Chancellor of the University for distinguished
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`achievement in research, teaching, and service. From 2020, I transitioned to an
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`adjunct professorship while I graduate my remaining PhD students, since I have
`
`completed my move to EPFL in Switzerland, as discussed below.
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`6.
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`Since 2009, I also have been an Adjunct Professor at the Sunchon
`
`National University in Sunchon, Korea.
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`7.
`
`Since August 2018, I have been a Professor in the Department of
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`Microengineering at École polytehnique fédérale de Lausanne in Lausanne,
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`Switzerland.
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`8.
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`I have published more than 200 technical papers in journals and at
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`conferences.
`
`9.
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`I am a named inventor on over 60 United States patents, many of
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`which are in the field of semiconductor technology.
`
`10.
`
`I am familiar with the technology of the challenged patent—U.S.
`
`Patent No. 7,494,846 (the “’846 patent”)—and the knowledge and capabilities of a
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`person of ordinary skill in the art for that patent as of the time it was filed on
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`
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`March 9, 2007. I personally satisfied and exceeded the level of ordinary skill in
`
`the art (described below) for the ’846 patent as of the time it was filed.
`
`11.
`
`12.
`
`I am a member of the Institute of Electrical and Electronic Engineers.
`
`I have served as a committee member of numerous technical
`
`conferences, including International Electron Device Meeting, Device Research
`
`Conference, Large Area, Organic, and Printed Electronics Conference, and IEEE
`
`Electronic Components and Technology Conference.
`
`13.
`
`A copy of my curriculum vitae (including a list of all publications) is
`
`attached as Appendix A.
`
`14.
`
`I have reviewed the specification, claims, and file history of the “’846
`
`patent (Ex. 1001, Ex. 1012). I understand that the ’846 patent was filed on March
`
`9, 2007 as U.S. Patent Application No. 11/716,104.
`
`15.
`
`I have reviewed the following references in preparing this declaration,
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`all of which I understand to be prior art to the ’846 patent:
`
` U.S. Patent Publication No. 2003/0062612, titled “Multi-Dice Chip Scale
`
`Semiconductor Components and Wafer Level Methods of Fabrication”
`
`(“Matsuo” (Ex. 1003)), which published on April 3, 2003.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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` U.S. Patent No. 6,841,883, titled “Multi-Dice Chip Scale Semiconductor
`
`Components and Wafer Level Methods of Fabrication” (“Farnworth” (Ex.
`
`1004)), which issued on January 11, 2005.
`
` U.S. Patent No. 5,915,231, titled “Method in an Integrated Circuit (IC)
`
`Manufacturing Process for Identifying and Redirecting IC’s Mis-
`
`Processed During Their Manufacture” (“Beffa” (Ex. 1005)), which issued
`
`on June 22, 1999.
`
` U.S. Patent Publication No. 2006/0278992, titled “Post & Penetration
`
`Interconnection” (“Trezza” (Ex. 1006)), which was filed on January 10,
`
`2006, published on December 14, 2006, and claims priority to U.S.
`
`Provisional Application No. 60/690,759 filed on June 14, 2005.
`
` U.S. Patent Publication No. 2005/0023656, titled “Vertical System
`
`Integration” (“Leedy” (Ex. 1007)), which published on February 3, 2005.
`
` U.S. Patent Publication No. 2007/0218678, titled “Method of
`
`Manufacturing Wafer Level Stack Package” (“Suh” (Ex. 1008)), which
`
`was filed on December 29, 2006 and published on September 20, 2007.
`
`16.
`
`I have reviewed the above patent and patent publication, and all other
`
`exhibits cited in this declaration.
`
`17.
`
`I have been retained by the Petitioner Samsung Electronics Co., Ltd.
`
`(“Samsung”) as an expert in the field of semiconductor fabrication. I am working
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`as an independent consultant in this matter and am being compensated for my time
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`
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`at my normal hourly consulting rate of $625. My compensation does not depend
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`on and in no way affects the substance of my statements in this Declaration.
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`18.
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`I have no financial interest in the Petitioner. I similarly have no
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`financial interest in the ’846 patent and have had no contact with the named
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`inventors of the ’846 patent.
`
`I.
`
`Relevant Law
`
`19.
`
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my analysis and
`
`conclusions. My understanding of the law is as follows:
`
`A.
`
`Person of Ordinary Skill in the Art
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`20.
`
`I have been informed and understand that, in the context of an
`
`invalidity analysis, a person having ordinary skill in the art (“POSITA”) is a
`
`hypothetical person who looks to prior art at the time of the invention. I further
`
`understand that the factors that may be considered in determining the level of
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`ordinary skill include: (1) the problems encountered in the art; (2) the prior art
`
`solutions to the problems encountered in the art; (3) the rapidity of innovations; (4)
`
`the sophistication of the technology; and (5) the education level of active workers
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`in the field. I understand that these factors need not all be taken into account for
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`
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`the analysis and that one or more of these factors may control.
`
`B. Claim Construction
`
`21.
`
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`purposes of my analysis in this proceeding and with respect to the prior art, I have
`
`been informed that claims subject to inter partes reviews are currently reviewed
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`under “the Phillips standard.”
`
`22.
`
`I have been informed that under the Phillips standard, claim terms are
`
`given their plain and ordinary meaning as understood by a person of ordinary skill
`
`in the art at the time of the invention in light of the claim language and the patent
`
`specification.
`
`23.
`
`I have been informed that the claims encompass the embodiments
`
`described in the specification.
`
`24.
`
`I have been informed that a patentee can serve as his or her own
`
`lexicographer. As such, if the specification provides a claim term with a specific
`
`definition, I should interpret that claim term in light of the particular definition
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`provided by the patentee.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`C. Anticipation
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`
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`25.
`
`I have been informed and understand a patent claim is invalid as
`
`“anticipated” by the prior art if each and every limitation of that claim is found in a
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`single prior art reference. I further understand that two references cannot be
`
`combined for anticipation purposes unless one is incorporated by reference into the
`
`other by including a particularized identification in the anticipatory reference of the
`
`material incorporated and a clear indication in the anticipatory reference of where
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`that material is found in the second reference.
`
`26.
`
`I have been further informed and understand that the description in a
`
`prior art reference does not have to be in the same words as the claim, but all of the
`
`requirements of the claim must be there, either stated or necessarily implied (i.e.,
`
`inherent), so that a person of ordinary skill in the art, looking at that one reference,
`
`would be able to make and use the claimed invention based on the reference. I
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`further understand that a reference need not state a feature’s absence in order to
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`disclose a negative limitation.
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`D. Obviousness
`
`27.
`
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed. This means that, even if all of the requirements of a claim
`
`are not found in a single prior art reference, the claim is not patentable if the
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`differences between the subject matter in the prior art and the subject matter in the
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`
`
`claim would have been obvious to a person of ordinary skill in the art at the time
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`the application was filed.
`
`28.
`
`I have been informed and understand that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
`
` the level of ordinary skill in the art at the time the application was filed;
`
` the scope and content of the prior art; and
`
` what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`29.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
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`other factors:
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` whether the teachings of the prior art references disclose known concepts
`
`combined in familiar ways, which, when combined, would yield
`
`predictable results;
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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` whether a person of ordinary skill in the art could implement a predictable
`
`variation, and would see the benefit of doing so;
`
` whether the claimed elements represent one of a limited number of known
`
`design choices, and would have a reasonable expectation of success by
`
`those skilled in the art;
`
` whether a person of ordinary skill would have recognized a reason to
`
`combine known elements in the manner described in the claim;
`
` whether there is some teaching or suggestion in the prior art to make the
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`modification or combination of elements claimed in the patent; and
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` whether the claim applies a known technique that had been used to
`
`improve a similar device or method in a similar way.
`
`30.
`
`I understand that one of ordinary skill in the art has ordinary creativity
`
`and is not an automaton.
`
`31.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
`
`II.
`
`Summary of Opinions
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`
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`32.
`
`For the reasons explained below, I conclude that claims 1-16 of the
`
`’846 patent are disclosed in the prior art, and are anticipated and/or rendered
`
`obvious by the prior art.
`
`III. Overview of the ’846 Patent
`
`33.
`
`The ’846 patent is directed to “integrated circuits, and more
`
`particular[ly] to manufacturing and packaging techniques for forming stacked
`
`memory dies.” Ex. 1001, 1:6-8.
`
`34.
`
`Integrated circuits technology followed a trajectory called “Moore’s
`
`law” where the number of transistors within a given area were expected to double
`
`about every two years. This constant push to densely pack transistors in a given
`
`area led to rapid improvements in the semiconductor industry—and the ’846 patent
`
`recognizes as much. Ex. 1001, 1:12-19 (“Since the invention of integrated circuits,
`
`the semiconductor industry has experienced continuous rapid growth due to
`
`constant improvements in the integration density of various electronic components
`
`(i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this
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`improvement in integration density has come from repeated reductions in
`
`minimum feature size, which allow more components to be integrated into a given
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`chip area.”). As the ’846 patent notes, this was improvements effectively in a two-
`
`dimensional (2D) nature. Ex. 1001, 1:20-23 (“These integration improvements are
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`essentially two-dimensional (2D) in nature, in that the volume occupied by the
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`
`
`integrated components is essentially on the surface of the semiconductor wafer.”).
`
`35.
`
`The other way to increase the density of components was three-
`
`dimensional stacking of these integrated circuit “chips” or “dies.” As the ’846
`
`patent recognizes, this, too, was a well-known technique. Ex. 1001, 1:35-37
`
`(“three-dimensional integrated circuit (3DIC) and stacked dies are commonly
`
`used.”). I reproduce below Figure 1 of the ’846 Patent which is labeled as “Prior
`
`Art.” As shown below, two dies 10 and 12 are stacked together in a vertically
`
`aligned manner with vertically stacked and aligned with each other with
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`[t]hrough-silicon vias (TSV)1 running through them.
`
`
`1 Throughout this declaration, I have added colors to show where various features
`
`described in the text are shown in figures disclosed in the prior art and in various
`
`figures that I created for explanation. I have also emphasized certain text in bold
`
`and/or italics for clarity. All emphasis, color, and annotations are added unless
`
`otherwise stated.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`These [t]hrough-silicon vias (TSV) are typically metallic paths that
`
`36.
`
`traverse the entire thickness of the die and provide electrical connection within the
`
`electrical components in one die to electrical components in other die. To
`
`facilitate these inter-chip or inter-die connections, bond pads are often formed on
`
`either side of the die, as shown above as bond pads 6. The bond pads are
`
`vertically aligned with the corresponding bond pads on the opposing die and
`
`electrical connections are made. Ex. 1001, 1:37-45 (“TSVs 4 penetrate through
`
`semiconductor substrate 2, and are connected to the integrated circuits in the
`
`respective dies and bonding pads 6. Dies 10 and 12 are bonded through bonding
`
`pads 6.”). Figure 1 shows the result of these stacked dies that are shown to be
`
`vertically aligned with one another.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`37.
`
`Stacking memory dies bring about one additional challenge in that
`
`each memory die must have unique addresses in order to be able to distinguish one
`
`memory die from the other. Ex. 1001, 1:57-59. As such, rather than the usual
`
`preferred approach of using TSVs to connect identical memory dies that “have
`
`exactly the same design, … fabricated using a same set of masks,” Ex. 1001, 1:51-
`
`56, different “redistribution lines” and “interposers” were purportedly used to
`
`distinguish the dies within the stack. Ex. 1001, 1:59-65. The downside of this
`
`approach, according to the ’846 patent, was introduction of “extra costs for
`
`forming and attaching interposers.” Ex. 1001, 1:66-67.
`
`A. The ’846 Patent Specification
`
`38.
`
`The ’846 patent purports to allows the use of TSVs in stacking of
`
`identical memory dies by providing a programmable identification circuit in each
`
`identical memory die. According to the ’846 patent, the identification circuit can
`
`be used to store “unique addresses” of memory dies that are otherwise identical to
`
`one another Ex. 1001, 2:8-21, 4:67-5:2. As a consequence, redistribution lines
`
`and/or interposers need not be utilized, lowering cost. Ex. 1001, 3:29-33. But as I
`
`explain below, the purported solution described in the ’846 patent merely uses
`
`well-known techniques and structures that were patented by Toshiba at least about
`
`three years before the ’846 patent was filed.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`39.
`
`I reproduce below Figure 5 of the ’846 Patent. As shown, it shows
`
`four dies that are stacked on top of each other. Ex. 1001, 5:42 (“Referring to FIG.
`
`5, dies 1, 2, 3 and 4 are stacked…”). Although the integrated circuits are not
`
`shown in the dies, it is understood that the integrated circuits are present in each of
`
`the dies. Ex. 1001, 4:8-9. (“Each of dies 1, 2, 3 and 4 includes a substrate, on
`
`which integrated circuits (not shown) may be formed.”). Moreover, the ’846
`
`patent notes that the four dies should be considered to be identical to each other,
`
`albeit some differences can exist between the dies. Ex. 1001, 6:22-27 (“For
`
`example, die 4 may have a greater thickness than dies 1, 2 and 3. In this case, the
`
`only difference between die 4 and dies 1, 2 and 3 are the thickness of substrates
`
`(hence the lengths of TSVs), and programming states of the programmable
`
`elements. Accordingly, die 4 is still considered to be identical to dies 1, 2 and 3.”).
`
`40.
`
`The ’846 patent appears to have schematically illustrated two different
`
`parts of the stacked dies for its purposes. On the left, the ’846 patent highlights the
`
`identification (ID) circuits in each die, that are connected to its through-silicon
`
`vias (TSVs), which in turn are connected to its own bond pads. On the right, the
`
`’846 patent highlights the input/output (IO) paths that include the through-silicon
`
`via[s] (TSV[s]) (connected to circuitry such as address lines, data lines and the
`
`like), which in turn are connected to its own bond pads. As shown, I have colored
`
`the TSVs for ID circuits a different color than the TSVs for the I/O circuitry (not
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`shown), and I have colored the bond pads for the ID circuits a different color than
`
`
`
`the bond pads for the I/O circuitry. However, structurally speaking, they do not
`
`have meaningful differences between them.
`
`
`
`ID Circuits
`
`41.
`
`I first discuss the left portion of Figure 5 directed to the ID circuits in
`
`greater detail. As I mentioned above, the ’846 patent discusses providing into each
`
`die, ID circuit that include programmable elements. Ex. 1001, 4:22-24. These
`
`programmable elements can be fuses (F1 to F4 with squiggly lines) or any “other
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`non-volatile devices, such as flash memories” that can be used to store a unique
`
`
`
`identification data for each die. Ex. 1001, 4:25-32. Regardless of the specific
`
`programmable element being utilized, “[t]he programmable elements in the ID
`
`circuit of each die are programmed differently from the programmable elements in
`
`the ID circuits of other dies.” Ex. 1001, 4:55-57. The unique information stored
`
`in the programmable elements can “act[] as a unique address of the corresponding
`
`die.” Ex. 1001, 4:67-5:2. Ex. 1001, 4:37-41,
`
`42.
`
`Each of these programmable elements of the ID circuits are
`
`connected to TSVs. Ex. 1001, 4:37-5:15, Figure 5. Each of these TSVs also has
`
`“chip-select pads P1, P2, P3 and P4” on one side of the die and “chip-select pads
`
`P1_B, P2_B, P3_B and P4_B” “[o]n the opposite side of the die.” Ex. 1001, 4:37-
`
`44. The corresponding chip-select pads P1, P2, P3 and P4 and chip-select pads
`
`P1_B, P2_B, P3_B and P4_B on opposing dies are vertically aligned to each other
`
`and electrically connected, thereby electrically connecting all of the dies in the
`
`stack together. Ex. 1001, 4:37-5:15, Figure 5. The chip-select pads are used to
`
`provide a chip select signal that enables one of the dies in the stack. Ex. 1001,
`
`5:54-64.
`
`I/O Circuitry
`
`43.
`
`The TSVs and bond pads for I/O circuitry is shown on the right
`
`portion of Figure 5. Although not shown in Figure 5, each die has numerous
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`circuitry associated with the main memory circuitry, such as the address and data
`
`
`
`lines of memory. Ex. 1001, 4:11-15 (“In an exemplary embodiment, the integrated
`
`circuits include memory circuits. Accordingly, the plurality of I/O pads PIO1
`
`through PIOn may include a portion connected to the address lines (not shown),
`
`and a portion connected to the data lines.”). These memory circuitry are
`
`connected to TSVs and each of these TSVs have a “plurality of input/output (I/O)
`
`pads PIO1 through PIOn” on one side of the die and “I/O pin PIO1_B through
`
`PIOn_B, … on the opposite side of the die.” Ex. 1001, 4:9-21. Again, the I/O
`
`pads and the I/O pins are vertically aligned with each other and electrically
`
`connected, thereby electrically connecting all of the dies in the stack together. Ex.
`
`1001, 4:19-21.
`
`B.
`
`44.
`
`Summary of the Prosecution History of the ’846 Patent
`
`The application for the ’846 patent was filed on March 9, 2007, and
`
`issued on February 24, 2009, after receiving a first-action allowance. Ex. 1001,
`
`Cover; Ex. 1012 [File History], 39-44 (Notice of Allowance dated August 8,
`
`2008). The Examiner allowed the claims without issuing a rejection, but the
`
`Examiner provided the following reasons for allowance:
`
`Although Muranaka 2005/0263605 discloses a multi-chip module
`[0224] and addressing of the chips using laser blown fuses to
`program the chips [0218 and 0222] as an improvement to using
`
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`
`
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`[0225-0226] with
`the chips
`to program
`memory cells
`identification information for the addressing to have been known,
`the reference does not disclose or suggest the bonding as recited
`wherein each of the I/O pads in the first die is connected to an
`I/O path in the second die as recited in claim 1 or vertical
`alignment of I/O pads as recited in claim 12.
`Ex. 1012, 43.
`
`45.
`
`I make three observations to the Examiner’s Reasons for Allowance.
`
`First, the Examiner appears to note that ID circuits the ’846 patent specification
`
`characterizes as being the feature that allows the use of TSVs to stack identical
`
`memory circuits together were known in the art.
`
`46.
`
`Second, the Examiner appears to consider features that were
`
`admittedly well-known to be allowable. As I discussed above in paragraph 35 to
`
`36, connecting vertically aligned I/O pads and I/O paths on opposing dies were
`
`admittedly well-known. Admitted prior art Figure 1 shows shown a structure
`
`where the I/O pads on two opposing dies are vertically aligned and electrically
`
`connected to one another.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`
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`47.
`
`Third, the Examiner appears to have misread or misunderstood the
`
`claim term “I/O conductive path” recited in claim 1. Specifically, claim 1 recites
`
`that “the plurality of I/O conductive paths comprises through-silicon vias” and
`
`claim 2 recites that “each of the I/O conductive paths comprises a first and a
`
`second I/O pad on opposite sides of the respective first and second semiconductor
`
`dies.” In other words, the claim term “I/O conductive paths” encompasses both
`
`TSVs and pads. However, the Examiner’s Reasons for Allowance
`
`mischaracterizes the claim, noting that “I/O pads [plural, and not I/O paths] in the
`
`first die is connected to an I/O path [singular] in the second die as recited in claim
`
`1.” Ex. 1012, 43. At a minimum, Examiner made an error in reading the claims.
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`
`
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`48.
`
`The applicant did not comment on Examiner’s reasons for allowance.
`
`IV. Overview of the Primary Prior Art Reference
`A. Overview of Matsuo
`
`49. Matsuo was filed on September 27, 2002 by Kabushiki Kaisha
`
`Toshiba, and published on April 3, 2003. Ex. 1003, Cover. Matsuo is based on an
`
`earlier Japanese Patent Application No. 2001-375002, filed on September 29,
`
`2001. Ex. 1003, Cover.
`
`50. Matsuo teaches “stacked type semiconductor device has a plurality of
`
`[memory] chips stacked in a vertical direction.” Ex. 1003, [0005]. “The
`
`semiconductor integrated circuits C1 to C4 have substantially the same structure
`
`and conform to the same specification.” Ex. 1003, [0028].
`
`51.
`
`I reproduce below Matsuo’s Figure 1. As shown, four semiconductor
`
`chips C1 to C4 are stacked together over a base substrate BS. Ex. 1003, [0027]
`
`(“A base substrate BS has a plurality of semiconductor integrated circuit chips
`
`(LSI chips) C1 to C4 stacked together thereon.”). Matsuo explains that “[t]he
`
`semiconductor integrated circuits C1 to C4 have substantially the same structure
`
`and conform to the same specification.” Ex. 1003, [0028].
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`
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`52.
`
`Similar to the ’846 patent, the four memory chips C1, C2, C3, and
`
`C4 include “through plugs PG formed of conductive material and penetrating the
`
`chip.” Ex. 1003, [0029]. I have colored on the left portion of the figure some of
`
`the through plugs in light green and some of the through plugs in dark green.
`
`Although Figure 1 above does not explicitly show them, Matsuo teaches that “pads
`
`are formed on the through plugs.” Ex. 1003, [0042]. These pads are further
`
`provided with bumps, which I colored in orange and pink. Ex. 1003, [0029]
`
`(“The corresponding terminals of the chips [that comprise through plugs PG] are
`
`connected together by bumps BP.”), [0043], [0030]. Through plugs PG are
`
`vertically aligned and electrically connected together.
`
`ID Circuits
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`Declaration of Dr. Vivek Subramanian
`U.S. Patent No. 7,494,846
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`53.
`
`Like the ’846 patent, Matsuo teaches that each di