United States Patent (19)
`Takasugi et al.
`
`USOO5978303A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,978,303
`Nov. 2, 1999
`
`54 MEMORY DEVICE PROVIDING BURST
`READ ACCESS AND WRITEACCESS FROM
`A SINGLE ADDRESS INPUT
`
`75 Inventors: Atsushi Takasugi; Takeshi Gotoh, both
`of Tokyo, Japan
`
`73 Assignee: Oki Electric Industry Co., Ltd.,
`Tokyo, Japan
`
`21 Appl. No.: 09/096,585
`22 Filed:
`Jun. 12, 1998
`30
`Foreign Application Priority Data
`Jul. 10, 1997
`JP
`Japan .................................... 9-185532
`Jul. 22, 1997
`JP
`Japan .................................... 9-212474
`May 19, 1998
`JP
`Japan ......
`... 10-137171
`(51) Int. Cl." ....................................................... G11C 8700
`52 U.S. Cl. ................................. 365/230.03; 365/230.06
`58 Field of Search ......................... 365/230.03, 230.06,
`365/233,236
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`OTHER PUBLICATIONS
`
`MSM54V24632A 131,072 Wordx32–Bitx2-Bank Synchro
`nous Dynamic RAM, Oki Semiconductor, Aug. 1, 1997, pp.
`1-29.
`
`Primary Examiner Trong Phan
`Attorney, Agent, or Firm Jones Volentine, LLP
`57
`ABSTRACT
`According to a first aspect of the invention, a memory device
`has a main memory array and a Sub memory array. In a
`Single burst, data are read from a Series of columns in the
`main memory array, transferred from one column in the
`main memory array to one column in the Sub memory array,
`read from a Series of columns in the Sub memory array, and
`written into the above-mentioned one column in the main
`memory array. According to a Second aspect of the
`invention, a memory device has a memory array and Sepa
`rate external data input terminals and output terminals. In a
`Single burst, data are read from a Series of columns in the
`memory array, and written to one of the columns, preferably
`the last column in the Series. Input of the written data is
`preferably simultaneous with the output of the data read
`from the column to which the input data are written.
`
`5,604,697 2/1997 Takahashi et al. ...................... 365/230
`5,848,021 12/1998 Sugibayashi ....................... 365/230.06
`
`82 Claims, 90 Drawing Sheets
`
`
`
`10
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`U.S. Patent
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`Nov. 2, 1999
`
`Sheet 1 of 90
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`5,978,303
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`FIG.3
`
`
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`U.S. Patent
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`Nov.2, 1999
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`Sheet 2 of 90
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`5,978,303
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`U.S. Patent
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`Nov. 2, 1999
`
`Sheet 3 of 90
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`5,978,303
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`U.S. Patent
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`Nov.2, 1999
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`Sheet 4 of 90
`
`5,978,303
`
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`NANYA TECHNOLOGY EXHIBIT 1006
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 8 of 90
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`5,978,303
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`U.S. Patent
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`Nov. 2, 1999
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`Nov. 2, 1999
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`Nov.2, 1999
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`Sheet 37 of 90
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`U.S. Patent
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`Sheet 38 of 90
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`Nov. 2, 1999
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`Nov.2, 1999
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`U.S. Patent
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`5,978,303
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`Nov. 2, 1999
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`Nov.2, 1999
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`NANYA TECHNOLOGY EXHIBIT 1006
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`U.S. Patent
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`Nov.2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov.2, 1999
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`U.S. Patent
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`Nov.2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 51 of 90
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`5,978,303
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`U.S. Patent
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`Nov.2, 1999
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`Sheet 52 of 90
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov.2, 1999
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`Sheet 57 of 90
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
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`U.S. Patent
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`Nov.2, 1999
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`Sheet 58 of 90
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 61 of 90
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`5,978,303
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`Nov.2, 1999
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`Sheet 62 of 90
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
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`U.S. Patent
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`Nov.2, 1999
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`U.S. Patent
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`Nov.2, 1999
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`NANYA TECHNOLOGY EXHIBIT 1006
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`U.S. Patent
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`Nov.2, 1999
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`Sheet 65 of 90
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`5,978,303
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 66 of 90
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 67 of 90
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`5,978,303
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`U.S. Patent
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`Nov. 2, 1999
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 69 of 90
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`NANYA TECHNOLOGY EXHIBIT 1006
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 70 of 90
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`5,978,303
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`FIG.73
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
`
`Nov.2, 1999
`
`Sheet 71 of 90
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`5,978,303
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`FIG.74
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Nov. 2, 1999
`Sheet 72 0f 90
`FIG.76
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`5,978,303
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`
`
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`
`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Nov. 2, 1999
`
`Sheet 74 of 90
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`5,978,303
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`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
`
`Nov. 2, 1999
`
`Sheet 75 of 90
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`5,978,303
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`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Nov.2, 1999
`
`Sheet 77 of 90
`
`5,978,303
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`2
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`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`U.S. Patent
`
`Nov. 2, 1999
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`5,978,303
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`
`Sheet 78 of 90
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Nov. 2, 1999
`
`Sheet 79 0f 90
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`5,978,303
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`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`U.S. Patent
`
`Nov. 2, 1999
`Sheet 81 of 90
`FIG.85
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`5,978,303
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`
`
`
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`5,978,303
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`
`
`
`
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
`
`Nov. 2, 1999
`
`Sheet 84 of 90
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
`
`Nov.2, 1999
`
`Sheet 85 of 90
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Nov.2, 1999
`
`Sheet 86 of 90
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`U.S. Patent
`
`Nov. 2, 1999
`
`Sheet 87 of 90
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
`
`Nov.2, 1999
`
`Sheet 88 of 90
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`U.S. Patent
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`Nov. 2, 1999
`
`Sheet 89 of 90
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`5,978,303
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`FIG.94
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`U.S. Patent
`
`Sheet 90 of 90
`Nov. 2, 1999
`FIG.95
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`5,978,303
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`NANYA TECHNOLOGY EXHIBIT 1006
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`5,978,303
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`15
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`25
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`35
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`40
`
`1
`MEMORY DEVICE PROVIDING BURST
`READ ACCESS AND WRITEACCESS FROM
`A SINGLE ADDRESS INPUT
`BACKGROUND OF THE INVENTION
`The present invention relates to a memory device with
`features useful in, for example, the digital processing of
`moving pictures.
`This type of processing is becoming increasingly neces
`Sary: television Sets are making use of digital image
`processing techniques, personal computers and WorkStations
`are being used to display Video images, and moving pictures
`are being transferred between these different media, with
`attendant conversion between different formats.
`Much digital image processing is performed on rectan
`gular blocks of picture elements or pixels. Spatial and
`temporal filtering for noise rejection, effect processing, and
`format conversion are typical examples. Motion estimation
`for image compression is another example. When moving
`pictures are processed in real time, there is accordingly a
`need for very fast retrieval of blocks of pixels. For example,
`as each new pixel in a moving picture is received and Stored,
`it may be necessary to read a block of pixels in which the
`new pixel occurs, and corresponding blocks of pixels from
`Several preceding image frames or fields, all in the Space of
`time before the next pixel is received.
`Conventional dynamic random access memory (DRAM)
`is far too slow for this task, because every read or write
`access must be preceded by the time-consuming input of a
`new address.
`Conventional dual-ported dynamic random-access
`memory, also known as Video random-acceSS memory
`(VRAM), can provide high-speed serial read access to an
`entire row of pixels, e.g. to all of the pixels in a horizontal
`Scanning line on a Screen, but this feature is not useful for
`access to rectangular blocks of pixels.
`Synchronous dynamic random-access memory (SDRAM)
`and Synchronous graphics random-access memory
`(SGRAM) permit burst access to Smaller groups of pixels,
`but require Separate address input for read acceSS and write
`access, which is inconvenient when the arrival of each new
`pixel requires both types of access. SDRAM and SGRAM
`also fail to Support Some of the burst lengths most often
`required in digital filtering.
`Moreover, none of these memories can be easily cascaded
`to provide access to pixel blocks in Several frames or fields.
`The inadequacies of existing types of random-acceSS
`memory have often forced System designers to use first-in
`first-out (FIFO) memory for storing fields and frames, and
`provide an application-specific integrated circuit (ASIC)
`with line memories for use in accessing rectangular blockS
`of pixels. An ASIC with twenty-one line memories, each a
`Static random-access memory (SRAM) storing one thousand
`twenty-four eight-bit words, has been used in digital tele
`vision receivers, for example. SRAM memory cells are
`large, however, So the line memories take up much space in
`the ASIC, limiting the amount of actual image-processing
`circuitry that can be accommodated. The SRAM line memo
`ries also consume much current, because they are operated
`as shift registers, and their presence increases the cost of the
`ASIC.
`Further details will be given below.
`SUMMARY OF THE INVENTION
`It is accordingly an object of the present invention to
`provide a memory device combining the functions of a field
`or frame memory and a group of line memories.
`
`45
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`50
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`55
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`60
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`65
`
`2
`Another object of the invention is to provide a memory
`device in which input of a single row-column address can
`produce burst read acceSS combined with Single write
`CCCSS.
`Another object is to provide a memory device in which
`input of a Single row address can produce burst read access
`combined with Single write access, using a column address
`input previously.
`Still another object is to provide a memory device suitable
`for cascading.
`Yet another object is to provide a memory device that can
`Store pixel data for multiple fields or frames of a moving
`picture, and output multiple pixel data from each of the
`fields or frames in a single combined burst.
`According to a first aspect of the invention, a memory
`device has a main memory array and a Sub memory array,
`both arrays sharing the same word lines, row decoder, and
`internal data bus. The Sub memory array has fewer columns
`than the main memory array. The data bus is coupled to a
`data input unit and a data output unit, which have external
`data input and output terminals.
`A column address generator generates a Series of column
`addresses from a Single starting column address, designated
`by an external column address signal. A main column
`decoder decodes the column addresses to Select a Series of
`columns in the main memory array. A Sub column decoder
`decodes low-order bits of the column addresses to Select a
`Series of columns in the Sub memory array.
`A control Signal generator generates internal control Sig
`nals that cause data Stored in the main memory array to be
`output through the internal data bus, cause data Stored in the
`main memory array to be transferred through the internal
`data bus to the Sub memory array, cause data Stored in the
`Sub memory array to be output through the internal data bus,
`and cause input data to be transferred to the main memory
`array through the internal data bus. Preferably these opera
`tions are performed in a single burst, in which data are
`output from multiple columns in the main memory array and
`multiple columns in the Sub memory array, are transferred
`from one column in the main memory array to one column
`in the Sub memory array, and are input to the Same one
`column in the main memory.
`The data input terminals and data output terminals may be
`Separate, permitting the data input unit to receive input data
`during the output of data from the data