`
`
`
`By Authority of the
`UnderSecretary of Commercefor Intellectual Property
`and Director of the United States Patent and Trademark Office
`
`
`
`
`
`AlONECER‘ey
`
`Certifying Officer
`
`
`
`
`NANYA CHNOLOC YCYEXHIB T1002, :
`
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`
`
`L®ALLTOWHOMTHESE; PRESENTS) SHALE, COME:
`UNITED STATES DEPARTMENT OF COMMERCE
`
`United States Patent and Trademark Office
`
`March 11, 2020
`
`THIS IS TO CERTIFY THAT ANNEXEDIS A TRUE COPY FROM THE
`
`RECORDS OF THIS OFFICE OF THE FILE WRAPPER AND CONTENTS
`
`OF:
`
`APPLICATION NUMBER: 09/504,344
`FILING DATE: February 14, 2000
`PATENT NUMBER: 6,651,134
`ISSUE DATE: November 18, 2003
`
`
`
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`cb99073.
`
`0325.00309 |
`
`\
`Field of the Invention
`
`The present invention relates to memory devices generally
`
`5
`
`and, more particularly,
`
`to a memory device that transfers a fixed
`
`number of words of data with each access.
`
`Background of the Invention
`
`A synchronous Static Random Access Memory
`
`(SRAM)
`
`can
`
`locations using a Single
`
` provide data from multiple address
` can be started and stopped in response to a control Signal.
`
`
`
`ia
`
`address. Accessing multiple locations in response to a Single
`
`address is called a burst mode access.
`
`A memory device that
`
`provides a burst mode can reduce activity on the address and
`
`control buses.
`
`The burst mode of a conventional synchronous SRAM
`
`A conventional Dynamic Random Access Memory
`
`(DRAM)
`
`preserves data during periodic absences of power by implementing a
`
`memory cell as a capacitor and an access transistor.
`
`Since the
`
`charge on the capacitor will slowly leak away,
`
`the cells need to be
`
`20
`
`“refreshed”
`
`once
`
`every few milliseconds.
`
`Depending on
`
`the
`
`frequency of accesses, a conventional DRAM can need an interrupt to
`
`1
`
`OL
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`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`0325.00309
`CD99073
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`perform data refreshes. Using a DRAM in a burst application is
`
`difficult because of
`
`the need to refresh.
`
`Completely hiding
`
`refresh cycles
`
`(e.g.,
`
`refreshing data without
`
`the need for
`
`interrupts)
`
`in a DRAM cannot happen with conventional memory
`
`devices due to architecture choices that have been made. Data word
`
`bursts can be interrupted while in progress since conventional
`
`architectures
`
`support
`
`both burst
`
`and Single
`
`access modes.
`
`Conventional DRAM access takes about 10ns to get data, but nearly
`
`20ns
`
`to complete writeback and equalization.
`
`The addition of
`
`another 20ns for a refresh results in a total access of 40ns.
`
`Since the data burst transfers of conventional memories
`
`can be interrupted and single accesses made,
`
`the amount of time
`
`that the data, address and control busses are not in use can vary.
`
`The variability of bus availability complicates the design of
`
`systems with shared data, address and control busses.
`
`It would be desirable to have a memory device that has a
`
`
`
`Fixed burst length.NNtttot
`
`Summary of the Invention
`
`20
`
`The present
`
`invention concerns an integrated circuit
`
`comprising a memory and a logic circuit.
`
`The memory may comprise
`
`2
`
`al
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`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`0325.00309
`CD99073
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`a plurality of storage elements each configured to read and write
`
`data in response to an internal address signal.
`
`The logic circuit
`
`the
`may be configured to generate a predetermined number of
`internal address signals in response to (i)
`an external address
`
`signal,
`
`(ii) a clock signal and (iii) one or more control signals.
`
`The generation of
`
`the predetermined number of
`
`internal address
`
`
`
`
`
`
`
`signals may be non-interruptible.
`eee
`The objects,
`
`features and advantages of
`
`the present
`
`invention include providing a fixed burst memory that may (i) give
`
`network customers who
`
`typically burst
`
`large data lengths the
`
`ability to set a fixed burst
`
`length that suits particular needs;
`
`(1i) have non-interruptible bursts;
`
`(iii) free up the address bus
`
`and
`
`control
`
`bus
`
`for
`
`a
`
`number
`
`of
`
`cycles;
`
`(iv)
`
`provide
`
`programmability for setting the burst
`
`length by using DC levels
`
`[Vss or Vee] on external pins;
`
`(v) hide required DRAM refreshes
`
`inside a known fixed burst
`
`length of data words; and/or
`
`(vi)
`
`operate at higher frequencies without needing interrupts to perform
`
`refreshes of data.
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`Brief Description of the Drawings
`
`These and other objects, features and advantages of the
`
`present
`
`invention will be apparent
`
`from the following detailed
`
`description and the appended claims and drawings in which:
`
`5
`
`FIG.
`
`1
`
`is a block diagram illustrating a preferred
`
`embodiment of the present
`
`invention;
`
`FIG. 2 is a detailed block diagram illustrating a circuit
`
`
`he a”©lilt.Hil
`
`a
`
`
`
`1s
`
`102 of FIG. 1;
`
`FIG.
`
`3
`
`is a detailed block diagram of a circuit 102'
`
`illustrating an alternative embodiment of the circuit 102 of FIC.
`
`1 ;
`
`FIG.
`
`4
`
`is a flow diagram illustrating an example burst
`
`address sequence;
`
`FIGS.
`SA and
`5B are diagrams
`illustrating example
`operations of a 4 word (FIG.
`5A)
`and an 8 word (FIG.
`5B)
`fixed
`
`burst access in accordance with the present
`
`invention; and
`
`FIG.
`
`6
`
`is a diagram illustrating an example operation
`
`where a burst length may be long enough to include a writeback and
`
`a refresh cycle.
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`CD99073
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`Detailed Description of the Preferred Embodiments
`
`Referring to FIG. 1, a block diagram of a circuit 100 is
`
`shown in accordance with a preferred embodiment of
`
`the present
`
`invention.
`
`The circuit 100 may be implemented,
`
`in one example, as
`
`5
`
`a
`
`fixed burst memory.
`
`The circuit
`
`100 may be configured to
`
`iba
`
`
`
`
`transfer a fixed number of words of data with each access (e.g.,
`
`read or write).
`
`A number of words transferred as a group is called
`
`a burst.
`
`The circuit 100 generally comprises a circuit 102 anda
`
`memory array (or circuit) 104. The circuit 102 may be implemented,
`
`in one example, as a burst address counter/register.
`
`The memory
`
`array 104 may be implemented,
`
`in one example, as a static random
`
`access memory (SRAM),
`
`a dynamic random access memory (DRAM), or
`
`other appropriate memory
`
`to meet
`
`the design criteria of
`
`a
`
`particular implementation.
`
`The circuit 102 may have an input 106 that may receive a
`
`signal
`
`(e.g., ADDR_EXT),
`
`an input 108 that may receive a signal
`
`(e.g., LOAD), an input 110 that may receive a signal
`
`(e.g., CLK),
`
`an input 112 that may receive a signal
`
`(e.g., ADV), and an input
`
`114 that may receive a signal
`
`(e.g., BURST).
`
`The circuit 102 may
`
`20
`
`have an output 116 that may present a signal (e.g., ADDR_INT)
`
`to an
`
`input 118 of the memory 104.
`
`The memory 104 may have an input 120
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

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`0325.00309
`CD39073
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`that may receive a signal
`
`(e.g., R/Wb),
`
`an input 122 that may
`
`receive a signal (e.g., DATA_IN) and an output 122 that may present
`
`a signal (e.g., DATA_OUT).
`
`The various Signals are generally “on”
`
`(e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0).
`
`5
`
`However,
`
`the particular polarities of the on (e.g., asserted) and
`
`off
`
`(e.g., de-asserted)
`
`states of
`
`the Signals may be adjusted
`
`(e.g.,
`
`reversed)
`
`accordingly to meet
`
`the design criteria of
`
`a
`
`particular implementation.
`
`The signal ADDR_EXT may be,
`
`in one example, an external
`
` address signal. The signal ADDR_EXT may be n-bits wide, where n is
`fiaWadi.
`
`
`
`
`an integer.
`
`The signal CLK may be a clock Signal. The signal R/Wb
`
`may be a control signal that may be in a first state Or a second
`
`state. When the signal R/Wb is in the first state,
`
`the circuit 100
`
`will generally read data
`
`from the memory circuit
`
`104
`
`for
`
`15
`
`presentation as the signal DATA_OUT. When the signal R/Wb is in
`
`the second state,
`
`the circuit
`
`100 will generally store data
`
`received as the signal DATA_IN.
`
`The signal LOAD may be,
`
`in one example, an address load
`
`control signal.
`
`The circuit 100 may be configured to load an
`
`20
`
`initial address, presented by the signal ADDR_EXT,
`
`in response to
`
`the signal LOAD.
`
`The initial address may determine the initial
`
`6
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`0325.00309
`CD99073
`
`location where data transfers to and from the memory 104 will
`
`generally begin.
`
`The signal ADV may be,
`
`in one example, used as a control
`
`signal.
`
`The circuit 100 may be configured to transfer a fixed
`
`number of words
`
`to or
`
`from the memory 104
`
`in response to the
`
`Signals ADV, CLK and R/Wb. When the Signal ADV is asserted,
`
`the
`
`circuit
`
`100 will generally begin transferring a predetermined
`
`number of words.
`
`The transfer is generally non-interruptible.
`io
`
`In
`
`one example,
`
`the signal ADV may initiate the generation of a number
`
`of addresses for presentation as the signal ADDR_INT.
`
`The signals ADV and LOAD may be,
`
`in one example, a Single
`
`signal (e.g., ADV/LDb). The signal ADV/LDb may be a control signal
`
`that may be in a first state or a second state. When the signal
`
`ADV/LDb is in the first state,
`
`the circuit 102 will generally load
`
`an address presented by the signal ADDR_EXT as an initial address.
`
`When the signal ADV/LDb is in the second state,
`
`the circuit 102 may
`
`be configured to generate the signal ADDR_INT as a fixed number of
`
`addresses in response to the signal CLK.
`
`The signal ADDR_INT may
`
`be,
`
`in one
`
`example,
`
`an internal address signal.
`
`The
`
`signal
`
`
`
`
`20
`
`ADDR_INT may be n-bits wide.
`
`Once the circuit 102 has started
`
`generating the fixed number of addresses,
`
`the circuit 102 will
`
`7 \
`
`\
`
`)i
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`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`y|
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`0325.00309
`CD99073
`
`generated (e.g.,
`
`a non-interruptible burst).
`
`The signal BURST may be,
`
`in one example, a configuration
`
`signal
`
`for programming the fixed number of addresses that
`
`the
`
`circuit
`
`102 may generate in response to the Signals CLK and
`
`ADV/LDb. The signal BURST may be generated,
`
`in one example, by (i)
`
`using bond options,
`
`(ii) voltage levels applied to external pins,
`
`or (iii) other appropriate signal generation means.
`
`When the memory 104 is implemented as a DRAM,
`
`the circuit
`
`100 may be configured to hide required DRAM refreshes
`
`(e.g.,
`
`refreshes may occur without affecting external environment)
`
`inside’
`
`a known fixed burst length of data words.
`
`The fixed burst length
`
`may allow the circuit 100 to operate at higher Erequencies than a
`
`conventional DRAM without needing interrupts to perform refreshes
`
`of data.
`
`In one example,
`
`the fixed burst
`
`length may be four or
`
`eight words.
`
`However,
`
`the burst
`
`length may be set
`
`to whatever
`
`length is necessary to meet
`
`the design criteria of a particular
`
`application.
`
`For example,
`
`the burst length may be programmed,
`
`in
`
`one example,
`
`to allow both writeback and refresh to occur within a
`
`
`
`20
`
`single access.
`
`The fixed burst length may be set,
`
`in one example,
`
`——
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`0325.00309
`CD99073
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`longer or shorter depending upon a frequency or technology to be
`
`used.
`
`The circuit 100 may be configured to provide a fixed
`
`burst
`
`length that may suit the requirements of network customers
`
`who typically burst large data lengths. By providing a fixed burst
`
`length,
`
`the circuit 100 may allow shared usage of data, address and
`
`A fixed length non-interruptible burst generally
`control busses.
`frees up the address bus and control bus for a known number of
`
`cycles.
`
`The address and control busses may be shared by a number
`
`of memory devices. The circuit 100 may provide a more reliable and
`
`/or accurate burst than is possible with multiple chips.
`
`Referring
`
`to
`
`FIG,
`
`2,
`
`a
`
`detailed
`
`block
`
`diagram
`
`illustrating implementation of
`
`the circuit 102
`
`is shown.
`
`The
`
`circuit 102 may comprise an address counter register 126 and a
`
`burst counter 128.
`
`The address counter register 126 generally
`
`receives the signals ADDR_EXT, LOAD, and CLK.
`
`The address counter
`
`register 126 may be configured to present the signal ADDR_INT. The
`
`signal ADV and the signal BURST may be presented to a burst counter
`
`128.
`
`The signal CLK may be presented at an input 130 of the burst
`
`
`
`15
`
`20
`
`counter 128. The burst counter 128 may have an output 132 that may
`
`present a signal
`
`(e.g., BURSTCLK) at an input 134 of the circuit
`
`want
`
`9
`
`severnna
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

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`0325.00309
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`
`126.
`
`An initial address may be loaded into the address counter
`
`register 126 by presenting the initial address
`
`in the signal
`
`ADDR_EXT and asserting the signal LOAD.
`
`The circuit 126 may be
`
`configured to increment
`
`an address
`
`in response to the signal
`
`the burst counter 128
`BURST_CLK. When the signal ADV is asserted,
`will generally present
`the signal BURST_CLK in response to the
`
`signal CLK.
`
`The signal BURST_CLK generally contains a number of
`
`pulses that has been programmed by the Signal BURST.
`
`Referring
`
`to
`
`FIG. $3,
`
`a
`
`detailed block
`
`diagram
`
`illustrating an alternative embodiment of the circuit 102 is shown.
`
`The circuit 102’ may comprise a latch 134, a multiplexer 136 anda
`
`counter 138.
`
`The signals ADDR_EXT, LOAD and CLK may be presented
`
`to the latch 134.
`
`The latch 134 may have an output 140 that may
`
`present a portion (e.g., mbits, where mis an integer smaller than
`
`n) of the signal ADDR_EXT as a portion of the signal ADDR_INT, an
`
`output 142 that may present a second portion (e.g., k bits, where
`
`k is an integer smaller than n) of the Signal ADDR_EXT to a first
`
`input of the multiplexer 136, and an output 144 that may present
`
`the second portion of the signal ADDR_EXT to an input 146 of the
`
`
`
`
`20
`
`counter 138.
`
`10
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
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`

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`0325.00309
`CD99073
`
`The signals ADV, CLK and BURST may be presented to inputs
`
`of the counter 138.
`
`The counter 138 may be configured to generate
`
`a number of addresses in response to the Signals CLK, BURST and
`ADV.
`The number of addresses generated by the counter 138 may be
`
`programmed by the signal BURST.
`
`
`
`iis
`
`
`
`The signal BURST may be presented to a control
`
`input of
`
`the multiplexer 136.
`
`The multiplexer 136 may select between a
`
`number of signals from the latch 134 and a number of Signals from
`
`the counter 138 to be presented as a second portion of the signal
`
`ADDR_INT in response to the signal BURST.
`
`Referring to FIG.
`
`4,
`
`a
`
`flow diagram illustrating an
`
`example burst address sequence is shown. When the signal ADV is
`
`asserted,
`
`the circuit 100 will generally generate a number of
`
`address signals, for example, N where N is an integer. The address
`
`Signals may be generated,
`
`in one example, on a rising edge of the
`
`Signal CLK.
`
`The address signals will generally continue to be
`
`generated until the Nth address signal is generated.
`
`Referring
`
`to
`
`FIGS.
`
`5A
`
`and
`
`5B,
`
`timing
`
`diagrams
`
`illustrating example operations for a four word (FIG.
`
`SA) and an
`
`20
`
`eight word (FIG.
`
`5B)
`
`fixed burst memory in accordance with the
`
`present
`
`invention are shown.
`
`The
`
`timing diagrams generally
`
`11
`
`ny\
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`“Subclass.
`
`:aye
`
`“APPLICATION NO,
`09/504344
`
`APPLIGANTS
`
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH,LL’
`
`
`
`'NANYA TECHNOLOGY EXHI
`
`
`
`aE
`
`e.KF
`
`
`
`
`
`
`
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`file:///c:/APPS/preexam/correspondence/! .htm
`
`AACAA
`Bib Data Sheet >
`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`Patent and TrademarkOffice
`Address: COMMISSIONER OF PATENTS AND TRADEMARKS
`‘Washington, D.C. 20231
`
`
`FILING DATE
`
`ATTORNEY
`
`
`| SERIAL NUMBER | GROUP ARTUNIT|HocKET NO.02/14/2000 CLASS
`
`
`
`368
`09/504,344
`2824
`0325.000309
`
`PRUEDIT ee
`
`IAPPLICANTS
`Cathal G. Phelan, Mountain View, CA;
`
`| 7 CONTINUING DATA KREKIKIIIKEKEEKERREREREERR nN on é
`
`Gre FOREIGN APPLICATIONS RREKEREREREKKEREEERE fr? é
`
`y
`IF REQUIRED, FOREIGN FILING LICENSE-GRANTED,,
`5nn
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`| STATE OR
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`ewance
`2
`
`\Verified and
`
`ADDRESS—
`
`021363
`
`
`
`-
`
`079 ¢ a
`a yes no
`Foreign Priorityclaimed
`
`85USC119(a-)conditions AO) yesnoOmetsf eae]
`Acknowledged ‘ExaminersSignatfteTHE_—
`Pe(aienenybwveguith-buicehrgchherdpAtieust
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`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`lo.All Fees
`{a 1.16 Fees( Filing )
`UW 1.17 Fees ( Processing Ext. of
`FILING FEE |FEES:Authority has been given in Paper
`
`RECEIVED to charge/credit DEPOSIT ACCOUNT__|time)No.
`
`690
`INo.
`for following:
`a 1.18 Fees(Issue )
`|
`[a Other
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` 19 credit
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`|R
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`NANYA TECHNOLOGY EXHIBIT 1002
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`

`PATENT APPLICATION SERIAL NO.
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`ecfe4/2000 SCARRICH GO000016 09504344
`
`FEriol
`
`630.00 OF
`
`PTO-1556
`(5/87)
`“U.S. GPO: 1999-459-082/19144
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`O2-\S~-909
`
`
`
`00/Pt/20Wt OLd
`"s'no690Lr
`
`CHRISTOPHER P. MAIORANA,P.C.
`ES
`o
`24025 Greater Mack, Suite 200
`Ai =>
`St. Clair Shores, Michigan 48080
`a Bo
`os =~
`Utility Patent Application Transmittal
`ae=o
`(Only for new non-provisional applications Under 37 CFR 1.53(b))
`ASSISTANT COMMISSIONER FOR PATENTS
`Case Docket No.0325.000302 =
`Washington, D. C. 20231
`Date: February 14, 2000
`
`TH Eq
`na ==
`
`Sir:
`
`Transmitted herewith for filing is a patent applicationof:
`
`Inventor(s):
`
`Cathal G. Phelan
`
`For:
`
`FIXED BURST MEMORIES
`
`Enclosedare:
`
`lL
`
`2.
`
`xX
`
`X
`
`Specification (13 pages); Claims (4 pages); Abstract (1 page)
`
`_5_ sheets of formal drawings.
`
`c. ___
`
`400 Incorporation By Reference (usable if Item 3b is checked)
`The entire disclosure of the prior application, from which a copy of the oath or
`declaration is supplied under Item 3b, is considered as being part ofthe disclosure
`of the accompanying application and is hereby incorporated by reference therein.
`
`5. If a Continuing Application, check appropriate box and supply the requisite
`information below andin a preliminary amendment:
`
`Continuation
`of prior application no.:
`
`Divisional
`
`Continuation-in-part (CIP)
`
`6
`
`XK
`
`An assignment to CYPRESS SEMICONDUCTOR CORP.along with PTO form
`1595,
`
`7 A PTO Form 1449 with a copy ofthe references not previously cited.
`
`8
`
`9.
`
`xX
`
`Return Receipt Postcard
`
`Other:
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
`
`
`
`
`
`3. Total Pages_2X Oath or Declaration
`
`a. _X Newly executed (original or copy)
`b. __.
`Copy from a prior application (37 CFR 1.63(d))
`(for continuation/divisional with Item 5 completed)
`Copy of Revocation of Previous Power
`
`
`
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`Thefiling fee has been calculated as shown below:
`
`
`Page 2 of 2
`
`
`
`
`BaioFee|=~|=| se.00|a
`
`
`> =o
`
`ToalCaims|17|0. |x sisoo]s ow| “Seeze
`
`
`2p 4
`Indep. Claims F336lo x
`$78.00
`$ 0.00
`in=a
`o| =
`Mult. Dep. Claims PT $260.00
`$ 0.00
`5 =
`
`
`
`°° =
`
`
`
`
`
`SUB-TOTAL ..............005.
`690.00
`
`SMALL ENTITY STATUS(divide SUB-TOTAL by two) ...... $
`__
`x Assignment Recordal Fee ($40.00) ..............0000000 000 $ 40.00
`TOTAL 2... ee eee cee eee $730.00
`
`x
`
`
`A checkin the amount of $730.00 to coverthe filing fee is enclosed.
`
`x
`
`The Commissioner is hereby authorized to charge any fees under 37 CFR 1.16 and 1.17
`which may be required by this paper or associated with this filing to Deposit Account No.
`50-0541. A duplicate copy ofthis sheet is enclosed.
`
`
`Correspondence Address:
`
`IAT
`021 363
`PATENT TRADEMARK: OFFICE:
`
`
`Customer Numberor Bar Code Label:
`
`CERTIFICATE OF EXPRESS MAILING
`
`Therebycertify that this paper (along with any paperreferred to as being attached or enclosed) is being deposited with the
`United States Postal Service via Express Mail Label No. EL417953316USin an envelope addressed to: BOX PATENT
`APPLICATION,Assistant Commissioner for Patents, Washington, D.C. 20231, on Feb
`14, 2000.
`
`
`fuadsdah,
`
`
`ia”
`
`\
`
` By Christopher P. Maiorana
`
`Reg. No. 44,829
`CHRISTOPHER P. MAIORANA,P.C.
`24025 Greater Mack, Suite 200
`St. Clair Shores, Michigan 48080
`(810) 498-0670
`
`Date: February 14, 2000
`
`Attorney Docket No.: 0325.00309
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
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`

`

`
`
`
`
`0325.00309
`CD99073
`
`illustrate externally measurable signals for four and eight word
`
`fixed burst read/write architectures.
`
`In general, an operation
`
`(e.g.,
`
`read or write) of the circuit 100 begins with loading an
`
`initial address
`
`(e.g., portions 150,
`
`154,
`
`and 158 of FIG.
`
`5A;
`
`portions 150’, 154’,
`
`and 158’ of FIG. 5B).
`
`Starting with the
`
`initial address, a fixed number of words are generally transferred
`
`(e.g.,
`
`line DQ of FIGS.
`
`5A and 5B). During the transfer of the
`
`fixed number of words,
`
`the address and control buses (e.g., ADDR,
`
`CE, R/W, etc.) are generally available to other devices
`
`(e.g.,
`
`portions 152, 156, and 160 of FIG.
`
`5A; portions 152’, 156’, and
`
`160’ of FIG. 5B).
`
`In one example,
`
`the control and address bus
`
`activity may be one-fourth (FIG.
`
`5A) or one-eighth (FIG.
`
`5B)
`
`the
`
`data bus activity (e.g., compare line ADDR with line DO of FIGS. 5A
`
`and 5B).
`
`The
`
`reduced bus activity may be an effect of
`
`the
`
`architecture.
`
`The data bus may be,
`
`in one example, active nearly
`
`100% of the time (e.g.,
`
`line DQ of FIGS. 5A and 5B)
`
`In one example,
`
`there may be no inefficiencies switching from read to write to read
`
`etcetera (e.g., see labels under line DO of FIGS. 5A and 5B).
`
`Referring to FIG.
`
`6,
`
`a timing diagram illustrating a
`
`
`
`15
`
`20
`
`fixed burst
`
`length long enough to hide a writeback and a refresh
`
`cycle
`
`is.
`
`shown.
`
`Internally the action being performed may
`
`12
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`NANYA TECHNOLOGYEXHIBIT 1002
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`0325.00309
`CD99073
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`completely hide DRAM refresh activity inside nominal external
`
`activities. A portion 162 illustrates that refresh activity (e.g.,
`
`writeback,
`
`read for refresh,
`
`and writeback for refresh) may be
`
`completed within the time of
`
`the burst
`
`transfer. When a fixed
`
`burst long enough to completely hide refresh activity is provided,
`
`there may be no penalty for using DRAM instead of SRAM for the
`
`memory 104.
`
`While
`
`the invention has been particularly shown and
`
`described with reference to the preferred embodiments thereof, it
`
`will be understood by those skilled in the art that various changes
`
`in form and details may be made without departing from the spirit
`
`and scope of the invention.
`
`
`
`13
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`NANYA TECHNOLOGYEXHIBIT 1002
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`

`
`
`
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`0325.00309
`
`CD99073
`
`CLAIMS
`
`OS
`
`1.
`
`An integrated cirquit comprising:
`
`a memory comprising a pjurality of storage elements each
`
`configured to read and write data in response to an internal
`
`address signal; and
`
`5
`
`a logic circuit configuyed to generate a predetermined
`
`number of said internal address
`
`Bignals
`
`in response to (i)
`
`an
`
`external address signal,
`
`(ii) a cldck signal and (iii) one or more
`
`control signals, wherein said genleration of said predetermined
`
`
`
` number of internal address signals jis non-interruptible.
`
`
`
`
`
`2.
`
`The integrated circuilt according to claim1, wherein
`
`said predetermine number of internal| address signals is determined
`
`by a fixed burst
`
`length.
`
`
`
`
`
`3,
`
`The integrated circuit| according to claim1, wherein
`
`said predetermined number of interna]
`
`address signals is 4.
`
`4,
`
`The integrated circuit
`
`ecording to claim1, wherein
`
`said predetermined number of internal \jaddress signals is 8.
`
`
`14
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
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`

`
`
` i
`iufaci,
`
`
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`0325.00309
`
`CD99073
`
`\
`
`5.
`
`The integrated cixpute according to claim 2, wherein
`
`said fixed burst length is programmable.
`
`6.
`
`The integrated circuit according to claim 5, wherein
`
`said fixed burst length is
`
`programmed by bond options.
`
`7.
`
`The integrated cifrcuit according to claim 5, wherein
`
`said fixed burst
`
`length is
`
`programmed by voltage levels on
`
`external pins.
`
`8.
`
`The integrated circuit according to claimi1, wherein
`
`said memory comprises a static Jrandom access memory.
`
`9.
`
`The integrated circuit according to claim 1, wherein
`
`said memory comprises a dynamic] random access memory.
`
`10.
`
`The integrated cifrcuit according to claim 9, wherein
`
`said predetermined number of internal address signals is chosen to
`
`provide time for writeback and
`
`refresh cycles.
`
`15
`
`NANYA TECHNOLOGYEXHIBIT 1002
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`0325.00309
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`CD99073
`
`11.
`
`The integrated circuit according to claim 1, wherein
`
`said predetermined number of internal address signals is chosen to
`|
`meet predetermined criteria for sharing address and control busses.
`
`An integrated circuit
`
`
`
`12.
`
`comprising:
`
`means
`
`for reading and wfiting data in response to an
`
`internal address signal; and
`
`
`
`means
`
`for generating aj predetermined number of said
`
`internal address signals in respgnse to (i)
`
`an external address
`
`signal,
`
`(ii) a clock signal and (iii) one or more control signals,
`
`wherein said generation of said
`
`redetermined number of internal
`
`address signals is non-interruptilble.
`
`
`
`
`13.
`
`A method of providing a
`
`fixed burst
`
`length data
`
`transfer comprising the steps of
`
`
`
`reading from and writing data to a memory in response to
`
`an internal address signal; and
`
`generating a predetexumined number of
`
`said internal
`
`
`
`
`
`address signals in response to (i
`
`a clock signal and (iii) a controll
`
`an external address signal,
`
`(ii)
`
`signal, wherein said generation
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
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`0325.00309
`CD99073
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`of saidpredetermined number of internal]/ address signals is non-interruptible.
`
`14.
`
`The method according to claim 13, further comprising
`
`the step of programming said predetermined number.
`
`15.
`
`The method according to claim 14, wherein said
`
`programming step is performed using bond options.
`
`16.
`
`The method accoyding to claim 14, wherein said
`
`programming step is performed uging voltage levels.
`
`17.
`
`The method according to claim13, further comprising
`
`the step of selecting said predetermined number to provide time for
`
`
`
`
`
`
`
`
`
`writeback and refresh cycles.
`
`
`
`17
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`0325.00309
`CD99073
`
`ABSTRACT OF THE DISCLOSURE
`
`An integrated circuit comprising a memory and a logic
`
`circuit.
`
`The memory may comprise a plurality of storage elements
`
`each configured to read and write data in response to an internal
`
`5
`
`address signal.
`
`The logic circuit may be configured to generate a
`
`predetermined number of the internal address signals in response to
`
`(i) an external address signal,
`
`(ii) a clock signal and (iii) one
`
`&
`
`or more control signals.
`
`1He
`
` number of internal address signals may be non-interruptible.
`
` fodisde.Gal
`
`
`
`The generation of
`
`the predetermined
`
`18
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`ee)
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`NANYA TECHNOLOGYEXHIBIT 1002
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`NANYA TECHNOLOGY EXHIBIT 1002
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`' 02711/00
`
`FRI 11:22 FAX 810 498 0673
`
`
`Docket No. 0325.00309
`
`CHRISTOPHER MAIORANA PC
`
`
`@oos
`
`DECLARATION, POWER OF ATTORNEY AND PETITION
`I, the undersigned inventor, hereby declare that:
`
`Myresidence, postoffice address and citizenship are givennext to my name;
`J believe that I am thefirst, original and solc inventorofthe subjectmatterclaimedin the application
`for patent entitled "HIDDEN DRAM REFRESHIN FIXED BURST MEMORIES", which:
`X__
`is submitted herewith;
`
`
`
`;
`and amended on
`as Application Serial No.
`wasfiled on
`I have reviewed and understand the contents of the above-identified application for patent
`(hereinafter, "this application”), including the claims:
`lacknowledgethe duty underTitle 37, Code ofFederal Regulations, Section 1.56, to discloseto the
`United States Patent and Trademark Office information known to be materialto thepatentability of
`this application.
`I also acknowledge that information is material to patentability whenit is not
`cwnulative to information already providedto the United States Patent and Trademark Office and
`whenit either
`
`compels, byitselforin combinationwith otherinformation, aconclusionthat a claim
`is unpatentable under the preponderanceof evidence standard, giving each term in
`the claim its broadest reasonable construction consistent with the application, and
`before any consideration is given to evidence which may be submitted to establish
`a contrary conclusion ofpatentability, or
`
`refutes oris inconsistent with a position taken in either(i) asserting an argument of
`patentability,or(ii) opposing an argumentofunpatentability relied on by the United
`States Patent and Trademark Office;
`Thereby claim the priority benefit under Title 35, Section 119(e), ofthe following United States
`provisional patent applications:
`
`Application No.
`
`Filing Date
`
`Thereby claim thepriority benefit underTitle 35, Section 120, ofthe following United States patent
`applications:
`.
`
`
`Serial No.
`
`Filing Date
`
`Status
`
`
`
`
`
`le
`
`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGYCORP. V. MONTEREY RESEARCH, LLC
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`NANYA TECHNOLOGY EXHIBIT 1002
`NANYA TECHNOLOGY CORP. V. MONTEREY RESEARCH, LLC
`
`

`

`‘ 02711/00
`
`FRI 11:22 FAX 810 498 0673
`
`
`
`CHRISTOPHER MAIORANA PC
`
`
`
`fioog
`
`Docket No. 0325.00309
`
`Page 2 of 2
`
`Thereby claim the prionty benefit under Title 35, Section 365(c), ofthe following PCT International
`patent applications designating the United States:
`
`Application No.
`
`Filing Date
`
`Where the subject matter of the claimsof this application is not disclosed in the United States or
`PCT priority patent applications identified above, I acknowledge the duty to disclose information
`knownto be material to the patentability ofthis application that becameavailable between the filing
`dates of this application and of the priority United States or PCT patent applications.
`
`I hereby appoint as myattorneys with full powerof substitution to prosecute this application and
`conduct all business in the United States Patent and Trademark Office associated with this
`application: Customer No. 021363.
`
`Ne
`021363
`PATENT.TRADEMARK OFFICE +
`
`I declare that all statements made herein ofmy ownknowledge are true and thatall statements made
`on information and belief are believed to be true; and further that these statements were made with
`the knowledge that willful false statements and the like so made are punishable by fine or
`imprisonment, or both, under Section 1001 of Title 18 of the United States Code and that such
`willful false statements mayjeopardize the validity of this applicaiion or any patent issuing thereon.
`
`Cathal G, Phelan
`
`Post Office Address:
`
`Haty,
`
`
`finfaite
`
`
`
`394 MountainViewAve.
`men.
`alla <xaa
`
`Mountain View, CA 9404]
`——ALS 7
`Signature of Inventor
`Citizen of:__
`Ireland
`7 / _
`Residence: 394 Mountain View Ave.
`< / wey
`Mountain View, CA 94041
`
`Date
`
`NANYA TECHNOLOGYEXHIBIT 1002
`NANYA TECHNOL