Trials@uspto.gov
`571-272-7822
`
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`Paper No. 7
`Date: June 14, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`NANYA TECHNOLOGY CORPORATION,
`NANYA TECHNOLOGY CORPORATION U.S.A., and
`NANYA TECHNOLOGY CORPORATION DELAWARE,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2021-00167
`Patent 6,651,134 B1
`
`
`
`
`
`
`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`MELVIN, Administrative Patent Judge.
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`571-272-7822
`
`
`Paper No. 7
`Date: June 14, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`NANYA TECHNOLOGY CORPORATION,
`NANYA TECHNOLOGY CORPORATION U.S.A., and
`NANYA TECHNOLOGY CORPORATION DELAWARE,
`Petitioner,
`v.
`MONTEREY RESEARCH, LLC,
`Patent Owner.
`
`IPR2021-00167
`Patent 6,651,134 B1
`
`
`
`
`
`
`
`
`
`Before KRISTEN L. DROESCH, JOHN F. HORVATH, and
`JASON W. MELVIN, Administrative Patent Judges.
`MELVIN, Administrative Patent Judge.
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`IPR2021-00167
`Patent 6,651,134 B1
`
`
`INTRODUCTION
`I.
`Nanya Technology Corporation, Nanya Technology Corporation,
`U.S.A., and Nanya Technology Corporation Delaware (collectively
`“Petitioner” or “Nanya”) filed a Petition (Paper 1, “Pet.”) requesting
`institution of inter partes review of claims 1–21 (all claims, “the challenged
`claims”) of U.S. Patent No. 6,651,134 B1 (Ex. 1001, “the ’134 patent”).
`Pet. 5. Monterey Research, LLC, (“Patent Owner”) filed a Preliminary
`Response. Paper 6 (“Prelim. Resp.”). Pursuant to 35 U.S.C. § 314 and
`37 C.F.R. § 42.4(a), we have authority to determine whether to institute
`review.
`An inter partes review may not be instituted unless “the information
`presented in the petition . . . and any response . . . shows that there is a
`reasonable likelihood that the petitioner would prevail with respect to at
`least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a). For the
`reasons set forth below, we conclude that Petitioner has not shown a
`reasonable likelihood it will prevail in establishing the unpatentability of at
`least one challenged claim, and we therefore do not institute inter partes
`review.
`
`A. REAL PARTIES IN INTEREST
`Petitioner identifies the captioned parties as real parties in interest.
`Pet. 2. Patent Owner identifies itself and IPValue Management as real
`parties in interest. Paper 4, 1.
`
`B. RELATED MATTERS
`As required by regulation, the parties identify matters related to the
`’134 patent. Pet. 2–3; Paper 4, 1–2. Of note is IPR2020-00985, in which
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`Advanced Micro Devices, Inc., challenges all claims of the ’134 patent, and
`IPR2020-01492, in which Qualcomm Incorporated challenges all claims
`other than claim 8. We instituted review in IPR2020-00985 on December 2,
`2020. IPR2020-00985, Paper 13. We instituted review in IPR2020-01492 on
`March 8, 2021. IPR2020-01492, Paper 9.
`Additionally, the district-court case involving Nanya is identified as
`Monterey Research, LLC v. Nanya Technology Corp. et al., No.
`1:19-cv-02090 (D. Del. 2019). Paper 4, 1, Pet. 2.
`
`C. THE ’134 PATENT
` The ’134 patent is titled Memory Device with Fixed Length Non
`Interruptible Burst. Ex. 1001, code (54). The patent discloses that “the data
`burst transfers of conventional memories can be interrupted and single
`accesses made,” and proposes a memory device “that has a fixed burst
`length.” Id. at 1:37–45.
`Figure 1 is reproduced below:
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`Ex. 1001, Fig. 1. Figure 1 depicts circuit 100 configured as a fixed burst
`memory, in which circuit 102 accepts external signals including external
`address signal ADDR_EXT, and “generate[s] the signal ADDR_INT as a
`fixed number of addresses in response to the signal CLK.” Id. at 3:21–22.
`The ’134 patent states that “[o]nce the circuit 102 has started generating the
`fixed number of addresses, the circuit 102 will generally not stop until the
`fixed number of addresses has been generated (e.g., a non-interruptible
`burst).” Id. at 3:25–28.
`The ’134 patent depicts two embodiments for circuit 102, in Figures 2
`and 3. Figure 2 is reproduced below:
`
`
`
`Id. Fig. 2. Figure 2 shows burst counter 128 receiving signal CLK (a clock
`signal), signal ADV, and signal BURST, and providing signal
`BURST_CLK. “When the signal ADV is asserted, the burst counter 128 will
`generally present the signal BURST_CLK in response to the signal CLK.
`The signal BURST_CLK generally contains a number of pulses that has
`been programmed by the signal BURST.” Id. at 4:10–14. Figure 3 and the
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`associated description disclose an alternative circuit, in which “counter 138
`may be configured to generate a number of addresses in response to the
`signals CLK, BURST[,] and ADV” and where “[t]he number of addresses
`generated by the counter 138 may be programmed by the signal BURST.”
`Id. at 4:29–34. The ’134 patent describes more generally that, “[w]hen the
`signal ADV is asserted, the circuit 100 will generally generate a number of
`address signals” and that “[t]he address signals will generally continue to be
`generated until the Nth address signal is generated.” Id. at 4:42–48.
`
`D. CHALLENGED CLAIMS
`Challenged claim 1 is reproduced below:
`1. A circuit comprising:
`a memory comprising a plurality of storage elements each
`configured to read and write data in response to an
`internal address signal; and
`a logic circuit configured to generate a predetermined
`number of said internal address signals in response to
`(i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals, wherein said generation
`of said predetermined number of internal address signals
`is non-interruptible.
`Ex. 1001, 5:22–32. Independent claim 16 recites limitations similar to those
`of claim 1, expressed as means-plus-function elements. Id. at 6:20–30.
`Independent claim 17 recites limitations similar to those of claim 1,
`expressed as a “method of providing a fixed burst length data transfer.” Id.
`at 6:31–39. Claims 2–7 and 9–15 depend, directly or indirectly, from
`claim 1. Id. at 5:33–6:19. Claims 18–21 depend, directly or indirectly, from
`claim 17. Id. at 6:40–48.
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`E. PRIOR ART AND ASSERTED GROUNDS
`Petitioner asserts the following grounds of unpatentability:
`Claim(s) Challenged
`35 U.S.C. § References/Basis
`1–3, 5, 8–10, 12–14, 16–18, 21 102
`Zagar1
`
`2–7, 19, 20
`
`11, 15
`1–5, 11–13, 15–18
`
`6, 7, 14, 19, 20
`8–10, 21
`
`1–3, 8, 12, 13, 16, 17
`
`4, 11, 15
`5, 9, 10, 14, 18, 21
`
`6, 7, 19, 20
`
`103
`
`103
`102
`
`103
`103
`
`102
`
`103
`103
`
`103
`
`Zagar, Fujioka2
`
`Zagar, Lysinger3
`Takasugi4
`
`Takasugi, Fujioka
`Takasugi, Zagar
`
`Wada5
`
`Wada, Takasugi
`Wada, Zagar
`
`Wada, Zagar, Fujioka
`
`Pet. 6–7. Petitioner also relies on the Declaration of Erik Chmelar, Ph.D.
`Ex. 1003.
`
`II. ANALYSIS
`A. LEVEL OF ORDINARY SKILL IN THE ART
`Petitioner proposes that a person of ordinary skill “would have been a
`technical person with a Bachelor’s degree in electrical engineering,
`
`
`1 US 5,666,323, issued Sept. 9, 1997 (Ex. 1005).
`2 US 6,185,149, issued from US 09/340,147, filed June 28, 1999 (Ex. 1008).
`3 US 5,784,331, issued July 21, 1998 (Ex. 1009).
`4 US 5,978,303, issued Nov. 2, 1999 (Ex. 1006).
`5 US 6,115,280, issued from US 08/833,178, filed Apr. 4, 1997 (Ex. 1007).
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`computer engineering, applied physics, or a related field, and approximately
`two years of experience working in the design, development, and/or testing
`of memory circuits, related hardware design.” Pet. 14 (citing Ex. 1003 ¶ 27).
`Patent Owner does not dispute this definition of a person of ordinary skill.
`See generally Prelim. Resp. For purposes of this Decision, we adopt
`Petitioner’s proposed level of ordinary skill as it appears to be consistent
`with the level of skill reflected by the Specification and in the asserted prior
`art references.
`
`B. CLAIM CONSTRUCTION
`For an inter partes review petition filed after November 13, 2018, we
`construe claim terms “using the same claim construction standard that would
`be used to construe the claim in a civil action under 35 U.S.C. 282(b).”
`37 C.F.R. § 42.100(b) (2020). Petitioner submits that “all terms should be
`given their plain and ordinary meaning” without elaboration. Pet. 15. Patent
`Owner submit that only “non-interruptible” and two means-plus-function
`terms require construction. Prelim. Resp. 14.
`As to “non-interruptible,” Patent Owner submits that the parties
`agreed to the construction adopted by the ITC in ITC-337-TA-792 (“the
`’792 Investigation”)—“cannot be stopped or terminated once initiated until
`the fixed number of internal addresses has been generated.”
`Prelim. Resp. 14–15. We proceed with that construction, as it is consistent
`with the plain and ordinary meaning of the claim term.
`We conclude that no other claim term requires express construction
`for purposes of this decision. See Nidec Motor Corp. v. Zhongshan Broad
`Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017).
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`C. GROUNDS BASED ON ZAGAR
`Zagar discloses an integrated circuit memory device. Ex. 1005,
`code (57). It describes that “[a] dual bank architecture is used to provide
`continuous sequential access to the array.” Id. at 1:38–41. Zagar depicts
`operation of a memory bank in Figure 1, reproduced below:
`
`
`
`Id., Fig. 1. Figure 1 depicts synchronous NAND dynamic memory device
`with clock signal input node 10 for receiving a clock signal, node 20 for
`receiving external address signals, node 30 for receiving data signals, and
`node 40 for receiving control signals. Id. at 2:14–20. Figure 1 further depicts
`row address latch 50, which generates a row address at node 90, provided to
`word line generator 110, which receives clock signal and control signals, and
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`activates a series of word lines 120, 122, 124, and 126, which in turn
`sequentially actuate access devices 130, 132, 134, and 136 to sequentially
`access data stored on storage elements 140, 142, 144, and 146. Id. at 2:20–
`27. Zagar discloses that, “[a]t the end of a memory cycle . . . a command is
`sent to close the open row.” Id. at 2:46–47.
`Zagar’s Figure 2 is reproduced below:
`
`
`
`Figure 2 depicts an embodiment with two banks of memory devices 170
`and 172 operating in a similar fashion to the device of Figure 1. Id. at 3:4–
`12. Figure 2 depicts the same external inputs as Figure 1. Id. at 3:8–12.
`Zagar discloses that “[a] command to perform a burst read of bank two will
`terminate the burst read of bank one.” Ex. 1005, 3:18–20.
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`Petitioner asserts that the claimed “internal address signals” read on
`Zagar’s word lines 120, 122, 124, and 126. Pet. 18–20. Addressing whether
`Zagar’s internal-address generation is non-interruptible, Petitioner asserts
`that “[b]ecause the memory device of FIG. 1 comprises only a single bank,
`there cannot be a command to perform a burst read out of a second (non-
`existent) bank which would terminate a burst read out of the single bank.”
`Pet. 21. Patent Owner, on the other hand, contends that “Zagar may
`terminate a single-bank memory burst in the same way it terminates a dual-
`bank memory burst: interrupting a first burst with a read command to begin
`a second burst.” Prelim. Resp. 33 (citing Ex. 1005, 3:18–20).
`We determine that Patent Owner has the more persuasive view of
`Zagar. When introducing the dual-bank embodiment, Zagar notes that
`“[e]lements of like function between FIG. 1 and FIG. 2 have corresponding
`element numbers.” Ex. 1005, 3:8–9. Zagar does not describe a difference
`between the “control” signals or logic of a single-bank embodiment and
`those of the dual-bank embodiment. See id. at 2:18–19, 3:4–26. Thus,
`Zagar’s disclosure indicates that the two embodiments function the same
`regarding their control capabilities. If the dual-bank embodiment may
`terminate a burst read operation, that capability arises from the control
`circuitry. By noting that the two embodiments share features unless
`indicated, Zagar supports the view that the single-bank embodiment may
`also terminate a burst read operation via the same control circuitry.
`Zagar further explains that the two-bank embodiment allows a “row in
`one bank to be opened or closed while data is being accessed in the other
`bank.” Id. at 3:12–15. The single-bank embodiment describes that “[a]t the
`end of a memory cycle, . . . a command is sent to close the open row.” Id.
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`at 2:46–47. Patent Owner argues that the ability to close a row further
`supports that Zagar’s burst operation could be interrupted, by issuing a
`command to close the row. Prelim. Resp. 33–34. We read Zagar’s
`row-closing operation as further support that Zagar does not disclose
`non-interruptible address generation, because Zagar does not disclose any
`way of preventing a command to close a row from interrupting a burst cycle.
`Thus, Zagar does not disclose the claimed “non-interruptible” generation of
`internal address signals.
`All independent claims of the ’134 patent require that generating
`internal address signals “is non-interruptible.” Ex. 1001, 5:30–32, 6:28–30,
`6:38–39. Accordingly, Petitioner’s contentions for anticipation by Zagar do
`not support institution. Further, in the obviousness grounds that include
`Zagar, Petitioner addresses only the dependent claims and relies on Zagar as
`disclosing non-interruptible address generation. Pet. 30–40. Thus,
`Petitioner’s contentions for those obviousness grounds also fail to support
`institution.
`
`D. GROUNDS BASED ON TAKASUGI
`Takasugi discloses a memory device providing burst read and write
`access from a single address input. Ex. 1006, codes (54), (57). Takasugi’s
`objectives include “provid[ing] a memory device in which input of a single
`row-column address can produce burst read access combined with single
`write access.” Id. at 2:1–4. Takasugi describes a number embodiments,
`which share common features. See id. at 16:21–22 (“The operation of the
`first four embodiments is summarized in FIG. 16 . . . .”), 16:62–63 (“[T]he
`fifth embodiment has the same elements as the first embodiment, indicated
`with the same reference numerals . . . .”), 20:15–18 (“[T]he ninth
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`embodiment is a memory device with two banks, referred to as bank A and
`bank B. Each of the two banks A and B is similar in configuration to the
`fifth embodiment.”). Takasugi’s Figure 17 is reproduced below:
`
`
`
`Id., Fig. 17. Figure 17 depicts the fifth embodiment and shows elements
`common with the first embodiment, along with “three additional elements
`disposed in the Y address generator 12”—“an access counter (AC) 50, an
`address register (ADR) 52, and an address register output switch 54.” Id. at
`16:62–67. Petitioner relies on those elements and aspects common with the
`first embodiment. See Pet. 40–46. Takasugi discloses that the “access
`counter 50 receives the clock signal CLK and a stopping control signal PST,
`and outputs an address input control signal PAI to the address register output
`switch 54.” Ex. 1006, 16:67–17:3. “The address register 52 receives and
`
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`stores the externally input Y address YAD” and the “address register output
`switch 54 couples the address register 52 to the down-counter 30.” Id. at
`17:3–6. “Control signal PST initializes the access counter 50 to a value that
`controls the burst length.” Id. at 17:7–8. “The access counter 50 only needs
`to output control signal PAI, so the access counter 50 can be configured as a
`ring counter or shift register.” Id. at 17:12–14.
`Takasugi discloses that, in the fifth embodiment, the memory device
`uses a “control signal ADX/ to generate an X or Y address signal internally,
`without input on the address bus ADD” and further notes that, “[w]hen RAS/
`and ADX/ are both low, the X address generator 29 generates a new X
`address by incrementing the previous X address” and “[w]hen CAS/ and
`ADX/ are both low, the Y address held in the address register 52 is
`transferred through the address register output switch 54 into the
`down-counter 30.” Id. at 17:26–30 (referring to Figure 18). Takasugi states
`that the “ninth embodiment can also operate in the mode described in the
`fifth embodiment, in which new X addresses are generated automatically in
`response to CS/, RAS/, and ADX/.” Ex. 1006, 23:40–44. Petitioner relies on
`that statement to assert that Takasugi discloses generating a predetermined
`number of internal addresses. Pet. 42–43.
`As to whether such generation is non-interruptible as claimed,
`Petitioner points to Takasugi’s access counter 50. Pet. 43–44 (citing
`Ex. 1006, 17:7–14. Petitioner reasons that access counter 50 is non-
`interruptible because Takasugi states that the access counter 50 “can be
`configured as a ring counter or shift register” and skilled artisans would
`understand “that a ring counter and a shift register is each a state machine
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`that cycles through its states uninterrupted and without the need for
`additional inputs.” Pet. 44.
`Patent Owner contends that Takasugi fails to disclose that access
`counter 50 “controls the generation of internal address signals,” particularly
`in a non-interruptible way. Prelim. Resp. 41. In Patent Owner’s view,
`Takasugi discloses multiple ways of stopping a burst: (1) a control signal
`that Takasugi refers to as a “stopping control signal PST” (Ex. 1006, 16:67–
`17:3) and (2) external signals such as ADX/, which Takasugi discloses as an
`“address transfer control signal” that must be low for the X address
`generator 29 to generate a new X address (Ex. 1006, 17:23–30). Prelim.
`Resp. 41–42.
`We conclude Petitioner’s contentions suffer from a fundamental flaw.
`To assert that address generation is non-interruptible, Petitioner relies on
`Takasugi’s “access counter 50.” Pet. 43–44; Ex. 1006, 16:62–17:14. That
`access counter is part of Takasugi’s “Y address generator 12.” Ex. 1006,
`16:64–65. But to assert that Takasugi generates a predetermined number of
`internal addresses, Petitioner relies on a statement that “new X addresses are
`generated automatically in response to CS/, RAS/, and ADX/.” Pet. 43
`(quoting Ex. 1006, 23:40–44). Petitioner does not explain why Takasugi’s
`disclosures regarding using access counter 50 to generate Y addresses would
`apply to generating X addresses. Moreover, Takasugi depicts “X address
`generator 29” as a separate element from “Y address generator 12.”
`Ex. 1006, Fig. 17. We conclude that the Petition does not adequately explain
`how Takasugi’s teachings disclose a single logic circuit configured to
`generate a predetermined number of internal addresses in a non-interruptible
`fashion.
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`As noted above, all independent claims of the ’134 patent require that
`generating internal address signals “is non-interruptible.” Ex. 1001, 5:30–32,
`6:28–30, 6:38–39. Accordingly, Petitioner’s contentions for anticipation by
`Takasugi (Pet. 40–51) do not support institution. Further, in the obviousness
`grounds that include Takasugi, Petitioner addresses only the dependent
`claims and relies on Takasugi as disclosing non-interruptible address
`generation. Pet. 51–55. Thus, Petitioner’s contentions for those obviousness
`grounds also fail to support institution.
`
`E. GROUNDS BASED ON WADA
`Wada’s first conventional SRAM embodiment is depicted in Figure
`12, reproduced below:
`
`
`
`Ex. 1007, Fig. 12. Figure 12 depicts burst counter unit 80 that starts with
`external address signal EXT.ADD and increments the address to create
`internal address signal INT.ADD, which is provided to decoder 2 to select
`word line 11 in memory cell array 1 for reading or writing data. Id. at 1:22–
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`2:33, 3:5–32. Wada discloses that “every time the clock signal CLK is at a
`leading edge and the advance signal ADV is High,” the internal address “is
`incremented by the burst counter.” Id. at 3:5–9. Wada notes that speed
`improvement in the conventional embodiment described above is limited by
`the “operative delays resulting from the parts of the memory cell array” such
`as “delay times in operations of the word lines.” Id. at 5:26–42.
`Wada discloses a second conventional SRAM embodiment, depicted
`in Figure 15, reproduced below:
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`Id. Fig. 15. Figure 15 depicts memory cell array 1 where the word line 11
`selected for reading or writing is determined by memory address input signal
`MADD, which is sent to the decoder as internal address signal INT.ADD.
`Id. at 3:33–62. Figure 15 depicts output register 5, which retains data
`received from memory cell array 1 through sense amplifier 41. Id. at 3:42–
`4:13. Rather than using a burst counter to increment the address identifying a
`memory word line as in the first conventional embodiment, the second
`conventional embodiment uses burst counter 8 to accept external chunk
`address signal EXT.CHA and increment it, producing internal chunk address
`signal INT.CHA, which allows multiplexer 7 to select from one of four
`blocks, 50 through 53 in output register 5 to provide to data input/output
`pin 9. Id. at 4:6–40.
`Wada describes that the second conventional embodiment avoids the
`operative delays involved in its first conventional embodiment. Id.
`at 5:43–45. Wada notes that the second conventional embodiment has the
`disadvantage of one clock-cycle delay between two burst outputs relating to
`two memory addresses. Id. at 5:50–53. That delay arises because data must
`be retained in the output register until output, preventing new data from
`being captured from the memory cell array. Id. at 5:11–24. Thus, Wada
`proposes an improved approach using burst mode that does not suffer from
`the operative delays of the conventional embodiment described above or the
`additional conventional embodiment with “data output interruptions”
`between bursts associated with different addresses. Id. at 5:66–6:7. Wada
`describes six enumerated embodiments that purport to address deficiencies
`of the prior art. Id. at 12:28–14:52 (First Embodiment), 14:53–16:50
`(Second Embodiment), 16:51–18:48 (Third Embodiment), 18:49–19:34
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`(Fourth Embodiment), 19:35–20:60 (Fifth Embodiment), 20:61–38 (Sixth
`Embodiment).
`Wada’s Second Embodiment is depicted in Figure 3, reproduced
`below:
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`
`
`Id. Fig. 3. Figure 3 depicts a system sharing most components with
`Figure 15 (the second conventional embodiment) described above, but using
`multiple output registers 5A through 5K in place of single output register 5,
`and using additional multiplexers 60a through 63a to select among the
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`multiple output registers. See id. at 14:63–15:2 (describing differences
`between the First Embodiment and Second Embodiment), 12:36–13:13
`(describing differences between the second conventional embodiment and
`the First Embodiment). As with Wada’s second conventional embodiment,
`its Second Embodiment uses burst counter unit 8 to convert external chunk
`address signal EXT.CHA into internal chunk address signal INT.CHA,
`which controls which block of the selected output register is transferred to
`output pin 9. Id. at 15:66–16:3.
`Because the Second Embodiment uses multiple output registers, it can
`“execute data burst output in uninterrupted fashion.” Id. at 16:12–15.
`Wada’s statement in that regard refers to avoiding the one clock-cycle delay
`associated with the single output register used in the second conventional
`embodiment. See id. at 5:50–53 (describing that “a data-free period (an
`interruption in the flow of data output) is bound to occur between two burst
`outputs”), 14:28–33 (describing that using two output registers as in the First
`Embodiment “permit[s] uninterrupted burst output of data), 16:12–15
`(describing that the Second Embodiment “provides one advantage identical
`to that of the first embodiment, i.e., the ability to execute data burst output in
`uninterrupted fashion”).
`Petitioner contends that both the first conventional embodiment and
`the Second Embodiment anticipate claim 1. Pet. 62–67. As to the claimed
`“logic circuit configured to generate a predetermined number of said internal
`address signals,” Petitioner identifies burst counter unit 80 in Wada’s first
`conventional embodiment (Pet. 63–64) and burst counter unit 8 in Wada’s
`Second Embodiment (Pet. 64–65). As described above, Wada teaches that
`those two circuits are “identical in structure” other than being provided with
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`IPR2021-00167
`Patent 6,651,134 B1
`
`different external address signals. See Ex. 1007, 4:18–21 (describing
`differences between the burst counter unit 80 and burst counter unit 8),
`12:36–39 (describing differences between the second conventional
`embodiment and the First Embodiment, not including any difference in burst
`counter unit 8), 14:63–15:5 (same, as between the First Embodiment and
`Second Embodiment), Figs. 1, 2 (showing the First Embodiment and Second
`Embodiment contain the same burst counter unit 8). Thus, Wada’s two
`embodiments identified by Petitioner for the claimed logic circuit offer no
`functional difference for our analysis of non-interruptibility.
`Patent Owner argues that the identified circuits do not satisfy the
`limitation “wherein said generation of said predetermined number of internal
`address signals is non-interruptible.” Prelim. Resp. 48–49. In particular,
`Patent Owner asserts that Petitioner has not identified a teaching that
`prevents interrupting a burst of address signals. Patent Owner reasons that,
`in Wada, “when the advance signal ADV is not High, the burst counters 80
`and 8 will not increment addresses, terminating the burst procedure.” Id.
`at 49; accord id. at 48 (citing Ex. 1007, 2:55–3:15).
`We agree with Patent Owner. Wada discloses that the burst counter
`increments with a leading edge of the clock signal only “when the advance
`signal ADV is brought High.” Ex. 1007, 2:56–59; accord id. at 3:5–9
`(stating the internal address signal is incremented “every time the clock
`signal CLK is at a leading edge and the advance signal ADV is High”).
`Wada discloses that the advance signal is controlled by an external device.
`Id. at 1:65–66 (“An input pin 93 receives an advance signal ADV that is
`externally furnished.”). Thus, incrementing Wada’s internal address depends
`on an external device maintaining the advance signal. Accordingly, we do
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`IPR2021-00167
`Patent 6,651,134 B1
`
`not agree with Petitioner that Wada discloses no method of terminating a
`burst before it has completed.
`As to the Second Embodiment, Petitioner points to Wada’s statement
`that the operations “are carried out continuously,” which “allows the data
`corresponding to the address Am to be output uninterrupted in burst mode.”
`Pet. 67 (citing Ex. 1005 at 16:5–10) (emphasis omitted). Patent Owner
`contends that, in Wada, “uninterrupted” means without delay between
`successive bursts, not without interruption within a burst. Prelim. Resp. 47–
`48. We agree with Patent Owner’s view. As described above, Wada’s
`disclosure of a second conventional embodiment specifically points out a
`one clock-cycle delay, which Wada addresses as one of the primary
`improvements to its disclosed embodiments. See supra at 17. When Wada
`discusses avoiding a “data-free period (an interruption in the flow of data
`output),” it connects that goal with the gap “between two burst outputs, one
`relating to the current memory address An, the other associated with the next
`memory address Am.” Ex. 1007, 5:50–53. Thus, Wada’s goal of memory
`“working in burst mode . . . without causing data output interruptions” (id. at
`6:3–7) or statements that its embodiments “permit uninterrupted burst output
`of data” (e.g., id. at 14:32–33, 16:12–15) do not speak to possible
`interruptions within a particular burst, as would be relevant to the claim
`language.
`Because Wada discloses systems in which the internal address
`increments for burst operation only when an external signal (ADV) is
`maintained in a particular state, it does not disclose the claimed “generation
`of . . . internal address signals is non-interruptible.” To be sure, Wada’s
`circuit could be used in a manner such that a burst is not interrupted, by
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`IPR2021-00167
`Patent 6,651,134 B1
`
`maintaining the ADV signal high until a desired number of clock cycles
`have passed. But simply using the circuit in that manner does not mean the
`burst was non-interruptible as claimed. 6 Our construction of the challenged
`claims requires that a non-interruptible burst “cannot be stopped or
`terminated once initiated until the fixed number of internal addresses has
`been generated.” See supra at Error! Bookmark not defined.. Such a
`limitation is not satisfied by a circuit in which burst operation depends on
`external control. The ’134 patent makes precisely that distinction over the
`prior art. Ex. 1001, 1:32–34 (“Data word bursts can be interrupted while in
`progress since conventional architectures support both burst and single
`access modes.”).
`Accordingly, we conclude Petitioner has not shown a reasonable
`likelihood it would prevail with respect to anticipation of claim 1 by Wada.
`Because all the independent claims require the same non-interruptible
`functionality, we reach the same conclusion for all claims. Further, in the
`obviousness grounds that include Wada, Petitioner addresses only the
`dependent claims and relies on Wada as disclosing non-interruptible address
`generation. Pet. 74–78. Thus, Petitioner’s contentions for those obviousness
`grounds also fail to support institution.
`
`
`
`6 As one possible analogy, a claim requiring “a vehicle that may not exceed
`20 mph” would not read on a car that happens to be driven at 15 mph,
`absent some mechanism in the structure of the car that prevents it from
`exceeding 20 mph. Wada’s circuit achieves uninterrupted bursts only when
`external control signals maintain ADV high while internal addresses are
`generated. That is different from a non-interruptible circuit.
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`IPR2021-00167
`Patent 6,651,134 B1
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`III. CONCLUSION
`For the reasons discussed above, we conclude Petitioner has not
`shown a reasonable likelihood of prevailing with respect to at least one
`claim. Accordingly, we do not institute review.
`
`IV. ORDER
`
`Accordingly, it is
`ORDERED that, pursuant to 35 U.S.C. § 314(a), no inter partes
`review of the ’134 patent is instituted in this proceeding.
`
`
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`Trials@uspto.gov
`571-272-7822
`
`PETITIONER:
`Peter Wied
`Vincent Yip
`pwied@nixonpeabody.com
`vyip@nixonpeabody.com
`
`
`
`PATENT OWNER:
`
`Theodoros Konstantakopoulos
`Ryan G. Thorne
`Yung-Hoon Ha
`Christian M. Dorman
`DESMARAIS LLP
`tkonstantakopoulos@desmaraisllp.com
`rthorne@desmaraisllp.com
`yha@desmaraisllp.com
`cdorman@desmaraisllp.com
`
`
`
`
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