Case IPR2021-00167
`U.S. Patent No. 6,651,134
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________________________________________
`
`
`
`NANYA TECHNOLOGY CORPORATION,
`NANYA TECHNOLOGY CORPORATION, U.S.A.,
`and NANYA TECHNOLOGY CORPORATION DELAWARE,
`Petitioner
`
`v.
`
`MONTEREY RESEARCH, LLC,
`Patent Owner
`__________________
`
`Case IPR2021-00167
`
`U.S. Patent No. 6,651,134
`__________________
`
`
`
`PATENT OWNER PRELIMINARY RESPONSE
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

`

`Case IPR2021-00167
`U.S. Patent No. 6,651,134
`
`TABLE OF CONTENTS
`
`I.
`II.
`
`Page
`Introduction ...................................................................................................... 1
`Background ...................................................................................................... 3
`A. Overview Of The ’134 Patent. .............................................................. 3
`III. Claim Construction ........................................................................................ 14
`A. All Challenged Claims: “Non-Interruptible.” ..................................... 14
`B.
`Claim 16: “means for reading data . . . / means for generating a
`predetermined number of said internal address signals in
`response to (i) an external address signal, (ii) a clock signal and
`(iii) one or more control signals”. ....................................................... 15
`IV. Summary Of Prior Art References ................................................................ 18
`A.
`Zagar .................................................................................................... 19
`1.
`Zagar Is Directed To Providing Continuous Sequential
`Access To A Memory Array. .................................................... 19
`Takasugi .............................................................................................. 22
`1.
`Takasugi Is Directed To Preventing Interruptions In
`Between Bursts. ........................................................................ 22
`C. Wada .................................................................................................... 25
`1. Wada Is Directed To Preventing Interruptions In
`Between Bursts. ........................................................................ 25
`Zagar, Takasugi, and Wada Are Substantially The Same As,
`And Cumulative To, Cowles. .............................................................. 26
`V. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 1.................................................................... 32
`A.
`Zagar Does Not Disclose “wherein said generation of said
`predetermined number of internal address signals is non-
`interruptible”. ...................................................................................... 32
`
`B.
`
`D.
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`B.
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`B.
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`Case IPR2021-00167
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`U.S. Patent No. 6,651,134
`1.
`Zagar Is Directed To Providing Continuous Data Access
`Between Bursts, Not Non-Interruptible Bursts. ........................ 32
`2.
`Zagar Discloses Terminating Bursts. ........................................ 33
`Zagar Does Not Teach The Means-Plus-Function Limitations
`Of Claim 16. ........................................................................................ 34
`VI. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 2.................................................................... 36
`A. Nanya’s Proposed Combination Of Zagar And Fujioka Does
`Not Meet Every Limitation Of Any Challenged Claim. ..................... 36
`VII. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 3.................................................................... 36
`A. Nanya’s Proposed Combination Of Zagar And Lysinger Does
`Not Meet Every Limitation Of Any Challenged Claim. ..................... 36
`VIII. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 4.................................................................... 37
`A.
`Takasugi Does Not Disclose “a memory comprising a plurality
`of storage elements each configured to read and write data in
`response to an internal address signal.” ............................................. 37
`Takasugi Does Not Disclose “a logic circuit configured to
`generate a predetermined number of said internal address
`signals in response to (i) an external address signal, (ii) a clock
`signal and (iii) one or more control signals”. ..................................... 39
`Takasugi Does Not Disclose “wherein said generation of said
`predetermined number of internal address signals is non-
`interruptible”. ...................................................................................... 41
`1.
`Takasugi Discloses Terminating Bursts ................................... 41
`2.
`Takasugi Is Directed To Preventing Interruptions
`Between Bursts. ........................................................................ 43
`Takasugi Does Not Teach The Means-Plus-Function
`Limitations Of Claim 16. .................................................................... 44
`
`C.
`
`D.
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`Case IPR2021-00167
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`U.S. Patent No. 6,651,134
`IX. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 5.................................................................... 45
`A. Nanya’s Proposed Combination Of Takasugi And Fujiokia
`Does Not Meet Every Limitation Of Any Challenged Claim. ............ 45
`X. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 6.................................................................... 45
`A. Nanya’s Proposed Combination Of Takasugi And Zagar Does
`Not Meet Every Limitation Of Any Challenged Claim. ..................... 45
`XI. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 7.................................................................... 46
`A. Wada Does Not Disclose “wherein said generation of said
`predetermined number of internal address signals is non-
`interruptible”. ...................................................................................... 46
`1.
`The Board Has Already Found That Wada Does Not
`Anticipate The Challenged Claims. .......................................... 46
`2. Wada Is Directed To Preventing Interruptions In
`Between Bursts, Not Making A Burst Non-Interruptible. ........ 47
`The Burst Procedure In Wada’s Conventional And
`Second Embodiments May Be Terminated By Failing To
`Maintain The External Advance Signal. ................................... 48
`B. Wada Does Not Teach The Means-Plus-Function Limitations
`Of Claim 16. ........................................................................................ 49
`XII. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 8.................................................................... 50
`A. Nanya’s Proposed Combination Of Wada And Takasugi Does
`Not Meet Every Limitation Of Any Challenged Claim. ..................... 50
`XIII. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 9.................................................................... 51
`A. Nanya’s Proposed Combination Of Wada And Zagar Does Not
`Meet Every Limitation Of Any Challenged Claim. ............................ 51
`
`3.
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`Page
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`2.
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`3.
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`U.S. Patent No. 6,651,134
`XIV. Nanya Did Not Establish A Reasonable Likelihood Of Prevailing
`Against Any Claim In Ground 10.................................................................. 51
`A. Nanya’s Proposed Combination Of Wada, Zagar, and Fujioka
`Does Not Meet Every Limitation Of Any Challenged Claim. ............ 51
`XV. The Board Should Exercise Its Discretion To Deny Institution Of
`Nanya’s Petition. ............................................................................................ 52
`A.
`The General Plastic Factors Favor Denial Of Institution. .................. 53
`1.
`Factor 1: whether the same petitioner previously filed a
`petition directed to the same claims of the same patent. .......... 55
`Factor 2: whether at the time of filing of the first petition
`the petitioner knew of the prior art asserted in the second
`petition or should have known of it. .......................................... 57
`Factor 3: whether at the time of filing of the second
`petition the petitioner already received the patent
`owner’s preliminary response to the first petition or
`received the Board’s decision on whether to institute
`review in the first petition. ........................................................ 58
`Factors 4 and 5: the length of time that elapsed between
`the time the petitioner learned of the prior art asserted in
`the second petition and the filing of the second petition;
`and whether the petitioner provides adequate
`explanation for the time elapsed between the filings of
`multiple petitions directed to the same claims of the same
`patent. ........................................................................................ 59
`Factors 6 and 7: the finite resources of the Board; and
`the requirement under 35 U.S.C. § 316(a)(11) to issue a
`final determination not later than 1 year after the date on
`which the Director notices institution of review. ...................... 60
`The Advanced Bionics Factors Favor Denial Of Institution. .............. 61
`1.
`Factor (a), (b), (c), and (d): Similarities and material
`differences in asserted art and prior art involved during
`examination; cumulative nature of art, extent art
`
`B.
`
`4.
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`5.
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`U.S. Patent No. 6,651,134
`evaluated, and overlap in arguments and manner of
`reliance. ..................................................................................... 63
`2.
`Factor (e): Establishing Examiner error. ................................. 64
`3.
`Factor (f): Additional evidence and facts. ................................ 65
`XVI. Conclusion ..................................................................................................... 65
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`Case IPR2021-00167
`U.S. Patent No. 6,651,134
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`Advanced Bionics, LLC v. MED-EL Elektromedixinische Gerate BmhH
`IPR2019-01469, Paper 6 (PTAB Feb. 13, 2020) (precedential) ...................62
`Becton, Dickinson & Co. v. B. Braun Melsungen AG,
`Case IPR2017-01586, Paper 8 (PTAB Dec. 15, 2017) (designated
`informative) ............................................................................................ 52, 62
`General Plastic Co., Ltd. v. Canon Kabushiki Kaisha,
`Case IPR2016-01357, Paper 19 (PTAB Sept. 6, 2017) (precedential) . passim
`NHK Spring Co., Ltd. v. Intri-Plex Techs., Inc.,
`IPR2018-00752, slip op. (Paper 8) (PTAB Sept. 12, 2018)
`(precedential) .................................................................................................65
`Pers. Web Techs., LLC v. Apple, Inc.,
`848 F.3d 987 (Fed. Cir. 2017) .......................................................................19
`Valve Corp. v. Elec. Scripting Prods., Inc.,
`Case IPR2019-00062, -00063, -00084, Paper 11 (PTAB Apr. 2, 2019)
`(precedential) .............................................................................. 52, 55, 57, 59
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795, 803 (Fed. Cir. 1999) ...............................................................14
`Statutes
`35 U.S.C. § 314(a) ........................................................................................ 2, 52, 61
`35 U.S.C. § 325(b) ...................................................................................................52
`35 U.S.C. § 325(d) ........................................................................................ 2, 62, 65
`35 U.S.C. 112(f) .......................................................................................................15
`Regulations
`37 C.F.R. § 42.104(b)(4) ....................................................................... 19, 35, 44, 50
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`Case IPR2021-00167
`Page(s)
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`U.S. Patent No. 6,651,134
`83 Fed. Reg. 39,989 (Aug. 13, 2018).......................................................................60
`Other Authorities
`Patent Trial and Appeal Board Consolidated Trial Practice Guide (Nov.
`2019) ..............................................................................................................60
`
`
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`All emphases are added unless otherwise indicated.
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`This paper includes color illustrations and should be viewed in color.
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`Case IPR2021-00167
`U.S. Patent No. 6,651,134
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`PATENT OWNER’S EXHIBIT LIST
`
`Exhibit No.
`2001
`
`2002
`2003
`
`2004
`
`2005
`
`2006
`
`2007
`
`2008
`
`2009
`
`2010
`
`DESCRIPTION
`Nanya Defendants’ Initial Proposed Claim Constructions in Monterey
`Research, LLC v. Nanya Tech. Corp., et al, C.A. No. 19-2090-NIQA
`(D. Del. Mar. 1, 2021).
`U.S. Pat. No. 5,729,504 to Cowles (“Cowles”).
`Monterey’s Complaint in Monterey Research, LLC v. Nanya Tech.
`Corp., et al, C.A. No. 19-2090 (NIQA), Dkt. No. 1 (D. Del. Nov. 11,
`2019).
`Monterey’s First Amended Complaint in Monterey Research, LLC v.
`Advanced Micro Devices, Inc., C.A. No. 19-cv-2149-NIQA-LAS,
`Dkt. No. 1 (D. Del. Feb. 5, 2020).
`Monterey’s First Amended Complaint in Monterey Research, LLC v.
`Qualcomm Inc. et al, C.A. No. 19-2083-NIQA-LAS, Dkt. No. 16 (D.
`Del. Feb. 14, 2020).
`Scheduling Order in Monterey Research, LLC v. Qualcomm Inc., et
`al, C.A. No. 19-2083-NIQA-LAS, Dkt. No. 44 (D. Del. Oct. 1, 2020);
`Monterey Research v. Nanya Tech. Corp. et al, C.A. No. 19-2090-
`NIQA-LAS, Dkt. No. 38 (D. Del. Oct. 1, 2020); Monterey Research,
`LLC v. Advanced Micro Devices Inc., C.A. No. 19-2149-NIQA-LAS,
`Dkt. No. 60 (D. Del. Oct. 1, 2020); Monterey Research, LLC v.
`STMicroelectronics N.V., et al, C.A. No. 20-0089-NIQA-LAS, Dkt.
`No. 52 (D. Del. Oct. 1, 2020); and Monterey Research, LLC v.
`Marvell Tech. Grp. Ltd. et al, C.A. No. 20-0158-NIQA-LAS, Dkt.
`No. 42 (D. Del. Oct. 1, 2020).
`Nanya’s Initial Invalidity Contentions in Monterey Research, LLC v.
`Nanya Tech. Corp., et al, C.A. No. 19-2090-NIQA (D. Del. Jan. 11,
`2021).
`Qualcomm’s Initial Invalidity Contentions in Monterey Research,
`LLC v. Qualcomm Inc. et al, C.A. No. 19-2083-NIQA-LAS (D. Del.
`Jan. 11, 2021).
`Qualcomm’s Preliminary Proposed Claim Constructions in Monterey
`Research, LLC v. Qualcomm Inc. et al, C.A. No. 19-2083-NIQA-LAS
`(D. Del. Mar. 1, 2021).
`Nanya’s Opening Brief In Support Of Motion For Stay Pending Inter
`Partes Review in Monterey Research, LLC v. Nanya Tech. Corp., et
`al, C.A. No. 19-2090-NIQA, Dkt. No. 60 (D. Del. Feb. 12, 2021).
`
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`Case IPR2021-00167
`U.S. Patent No. 6,651,134
`Exhibit No.
`2011
`
`DESCRIPTION
`Qualcomm’s Opening Brief In Support Of Their Motion To Stay
`Pending Inter Partes Review in Monterey Research, LLC v.
`Qualcomm Inc. et al, C.A. No. 19-2083-NIQA-LAS, Dkt. No. 71 (D.
`Del. Feb. 18, 2021).
`Order 29 Construing Claims, Inv. No. 337-TA-792, U.S.I.T.C.
`(February 9, 2012).
`
`2012
`
`All citations to specific pages of exhibits follow the pagination added to those
`exhibits per 37 C.F.R. § 42.63(d)(2)(i).
`
`
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`Case IPR2021-00167
`U.S. Patent No. 6,651,134
`Introduction
`I.
`
`The Board should deny Nanya Technology Corporation, Nanya Technology
`
`Corporation, U.S.A., and Nanya Technology Corporation Delaware’s ( “Nanya” or
`
`“Petitioner”) Petition against Claims 1-21 (“the Challenged Claims”) of U.S. Patent
`
`No. 6,651,134 (Ex-1001, the “’134 Patent”). Nanya’s Petition is the third raised
`
`against the ’134 Patent in the span of six months, directed to the same claims and
`
`using the same prior art references. In fact, four of Nanya’s Grounds are based on
`
`the same prior art reference—Wada—that the Board has already found does not
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`present a reasonable likelihood of anticipating independent Claims 1, 16, and 17 of
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`the ’134 Patent.
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`The ’134 Patent claims novel and non-obvious designs and procedures for
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`improving the efficiency and speed of memory devices conducting “burst”
`
`operations to access multiple memory locations using a single address. Nanya’s
`
`Petition does not establish a reasonable likelihood that the Challenged Claims are
`
`anticipated or obvious and that they should be cancelled. The Board should deny
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`Nanya’s Petition for three reasons.
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`First, none of Nanya’s primary references—Zagar, Takasugi, and Wada—
`
`disclose all limitations of the challenged claims. Particularly, none of Zagar,
`
`Takasugi, and Wada discloses “wherein said generation of said predetermined
`
`number of internal address signals is non-interruptible.” Indeed, the Board has
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`U.S. Patent No. 6,651,134
`already found that Wada does not disclose the “non-interruptible limitation. And
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`none of Nanya’s alleged obviousness references—Fujioka (Ex-1006) and Lysinger
`
`(Ex-1009)—teach that limitation.
`
`Second, the Board should exercise its discretion to deny institution under 35
`
`U.S.C. § 314(a) because Nanya’s Petition is the third petition filed against the ’134
`
`Patent. Nanya’s quintessential “follow-on” Petition was filed six months after
`
`Advanced Micro Devices, Inc. (“AMD”), and three months after Qualcomm
`
`Corporation (“Qualcomm”)—defendants in parallel district court litigations—filed
`
`first and second petitions (IPR2020-00985 and IPR2020-01492, respectively)
`
`against the Challenged Claims of the ’134 Patent. The Board instituted trial on
`
`AMD’s petition on December 2, 2020, (IPR2020-00985, Paper 14) and recently
`
`instituted trial on Qualcomm’s petition (IPR2020-01492, Paper 9). Nanya’s Petition
`
`challenges the same claims of the ’134 Patent using a reference—Wada—that the
`
`Board has already confirmed does not anticipate the claims of the ’134 Patent.
`
`Granting institution of Nanya’s Petition would place a substantial and unnecessary
`
`burden on the Board by ensnaring the Board’s resources in multiple, cumulative
`
`proceedings against the same patent, and would also prejudice Monterey.
`
`Third, the Board should exercise its discretion to deny institution under 35
`
`U.S.C. § 325(d) because each of Nanya’s primary references—Zagar, Takasugi, and
`
`Wada—are substantially the same as and cumulative to prior art already considered
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`U.S. Patent No. 6,651,134
`and dismissed by the Examiner during prosecution of the ’134 Patent. Particularly,
`
`each of Zagar, Takasugi, and Wada are directed to continuous burst procedures—
`
`precisely the same feature described in U.S. Patent No. 5,729,504 to Cowles
`
`(“Cowles”) and over which the Examiner allowed the ’134 Patent. Moreover, four
`
`of Nanya’s Grounds—those based on Wada—are cumulative of grounds the Board
`
`already analyzed and dismissed in instituting trial on AMD’s prior petition.
`
`Accordingly, Patent Owner Monterey Research, LLC (“Monterey”)
`
`respectfully requests that the Board deny institution.
`
`II. Background
`A. Overview Of The ’134 Patent.
`The ’134 patent teaches a novel design and operation for memory devices,
`
`such as a Static Random Access Memory (SRAM) or a Dynamic Random Access
`
`Memory (DRAM), operating in burst mode. In burst mode, a memory device can
`
`provide data from multiple locations in the device using a single external address,
`
`thereby increasing efficiency and reducing activity on address and control buses
`
`connected to the device. (Ex-1001, 1:11-16.) Before the invention of the ’134
`
`Patent, burst mode in both conventional SRAMs and DRAMs had drawbacks,
`
`particularly a susceptibility to interruptions. In a conventional SRAM, burst mode
`
`could be “started and stopped in response to a control signal.” (Ex-1001, 1:16-18.)
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`And using burst mode in a conventional DRAM was “difficult because of the need
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`to refresh” data within the memory cell, which might necessitate interrupting the
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`burst application and thus greatly lengthen the amount of time required for accessing
`
`data. (Ex-1001, 1:20-36.) Because burst mode data transfers in both conventional
`
`SRAMs and DRAMs could be interrupted, the availability of data, address, and
`
`control busses varied, which “complicate[d] the design of systems with shared data,
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`address, and control busses.” (Ex-1001, 1:37-43.) As such, the ’134 Patent explains
`
`that it “would be desirable to have a memory device that has a fixed burst length.”
`
`(Ex-1001, 1:44-45.)
`
`To that end, the ’134 Patent proposes an integrated circuit comprising a
`
`memory and a logic circuit which fixes the length of the burst and renders it non-
`
`interruptible. (Ex-1001, Abstract, 1:44-45.) The inventions of the ’134 Patent
`
`present a number of benefits and advantages, including to:
`
`“(i) give network customers who typically burst large data lengths the
`
`ability to set a fixed burst length that suits particular needs; (ii) have
`
`non-interruptible bursts; (iii) free up the address bus and control bus for
`
`a number of cycles; (iv) provide programmability for setting the burst
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`length by using DC levels [Vss or Vcc] on external pins; (v) hide
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`required DRAM refreshes inside a known fixed burst length of data
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`words; and/or (vi) operate at higher frequencies without needed
`
`interrupts to perform refreshes of data.” (Ex-1001, 1:58-67.)
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`Fixing the burst length permits the ’134 Patent’s novel circuit to “allow shared
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`usage of data, address and control busses,” by “generally free[ing] up the address
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`bus and control bus for a known number of cycles,” e.g., during the burst mode, and
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`therefore “may provide a more reliable and/or accurate burst than is possible with
`
`multiple chips.” (Ex-1001, 3:54-61.)
`
`Among other things, the ’134 Patent provides a novel circuit integrating a
`
`memory device with a logic circuit, thereby providing a fixed burst length and
`
`ensuring non-interruptible generation of a predetermined number of internal
`
`addresses. Independent Claim 1 is illustrative:
`
`“A circuit comprising:
`
`a memory comprising a plurality of storage elements each configured
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`to read and write data in response to an internal address signal; and
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`a logic circuit configured to generate a predetermined number of said
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`internal address signals in response to (i) an external address signal,
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`(ii) a clock signal and (iii) one or more control signals, wherein said
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`generation of said predetermined number of internal address signals is
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`non-interruptible.” (Ex-1001, Claim 1.)
`
`The ’134 Patent illustrates aspects of the claims using four exemplary figures.
`
`For example, Figure 1, reproduced below, presents a circuit 100 comprising “a
`
`[logic] circuit 102 and a memory array” 104:
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`Ex-1001, Figure 1 (annotated1)
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`Circuit 102 includes inputs for receiving signals, including, for example, an
`
`external address signal (“ADDR_EXT” 106); an address load control signal
`
`(“LOAD” 108); a clock signal (“CLK” 110); a control signal (“ADV” 112); or a
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`configuration signal (“BURST” 114), as shown in Fig. 1, reproduced below.
`
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`1 All annotations in drawings are added.
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`(Ex-1001, Figure 1.)
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`
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`The external address signal ADDR_EXT may be “n-bits wide,” (Ex-1001,
`
`2:56-58), and presents an “initial address,” which “may determine the initial
`
`location where data transfers to and from the memory 104 will generally begin.”
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`(Ex-1001, 3:1-4.) Circuit 100 loads the initial address presented by the external
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`address signal ADDR_EXT in response to the address load control signal LOAD.
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`(Ex-1001, 2:66-3:2.)
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`Circuit 100 “may be configured to transfer a fixed number of words to or
`
`from the memory 104 in response to signals ADV, CLK, and R/Wb.” (Ex-1001,
`
`3:6-8.) For example, the ’134 Patent states:
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`“When the signal ADV is asserted, the circuit 100 will generally begin
`
`transferring a predetermined number of words. The transfer is
`
`generally non-interruptible. In one example, the signal ADV may
`
`initiate the generation of a number of addresses for presentation as the
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`signal ADDR_INT.” (Ex-1001, 3:6-13.)
`
`
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`Alternatively, the ’134 Patent notes that “signals ADV and LOAD may be, in
`
`one example, a single signal (e.g., ADV/LDb).” (Ex-1001, 3:14-15.) In that
`
`embodiment, when the signal ADV/LDb is in a first state, the “circuit 102 will
`
`generally load an address presented by the signal ADDR_EXT as an initial address.”
`
`(Ex-1001, 3:17-19.) Conversely, when the signal ADV/LDb is in a second state:
`
`“[T]he circuit 102 may be configured to generate the signal
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`ADDR_INT as a fixed number of addresses in response to the signal
`
`CLK. The signal ADDR_INT may be, in one example, an internal
`
`address signal. The signal ADDR_INT may be n-bits wide. Once the
`
`circuit 102 has started generating the fixed number of addresses, the
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`circuit 102 will generally not stop until the fixed number of addresses
`
`has been generated (e.g., a non-interruptible burst).” (Ex-1001, 3:20-
`
`28.)
`
`
`
`The ’134 Patent states that the fixed number of addresses generated by the
`
`circuit 102 in response to the signals CLK and ADV/LDb may be programmed by,
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`for example, the configuration signal BURST. (Ex-1001, 3:29-32.) The signal
`
`BURST may be generated, for example, by “(i) using bond options, (ii) voltage
`
`levels applied to external pins, or (iii) other appropriate signal generation means.”
`
`(Ex-1001, 3:32-35.) Figure 1, reproduced below, shows the generation of the signal
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`ADDR_INT as a fixed number of addresses as programmed by the signal BURST.
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`(Ex-1001, Figure 1.)
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`In one embodiment, after receiving the initial starting address from
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`ADDR_EXT, circuit 102 is configured to increment subsequent addresses a specific
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`number of times—thereby generating a predetermined number of internal
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`addresses—as programmed by the signal BURST. For example, Figure 2,
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`reproduced below, presents a detailed block diagram of the circuit 102 embodied as
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`an address counter register 126 and a burst counter 128.
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`(Ex-1001, Figure 2.)
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`
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`In one embodiment of the ’134 Patent, the address counter register 126
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`receives the signals ADDR_EXT, LOAD, and CLK, while the burst counter 128
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`receives the signals ADV and BURST. (Ex-1001, 3:65 – 4:2.) The burst counter
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`128 presents a signal BURST_CLK—which contains “a number of pulses that has
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`been programmed by the signal BURST”—to the address counter 126 when the
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`signal ADV is asserted. (Ex-1001, 4:10-14.) The address counter register 126 loads
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`an initial address—identifying the starting point for accessing the memory array—
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`by receiving the external address signal ADDR_EXT and asserting the signal
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`LOAD. (Ex-1001, 4:6-8.) The address counter register 126 then “increment[s] an
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`address in response to the signal BURST_CLK,” for a number of times that equals
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`the number of pulses in the signal BURST_CLK as programmed by the signal
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`BURST. (Ex-1001, 4:8-10.) As such, the predetermined number of internal
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`addresses is generated by incrementing the initial address based on the number of
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`pulses from the signal BURST_CLK.
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`In this way, this embodiment of the ’134 Patent generates a predetermined
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`number of internal address signals. For example, when the signal ADV is asserted,
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`the circuit 100 will “generate a number of address signals, for example, N, where N
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`is an integer” which address signals “will generally continue to be generated until
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`the Nth address signal is generated.” (Ex-1001, 4:42-48.)
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`For example, Figure 5a, reproduced below, illustrates an operation for a four-
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`word fixed burst memory. The circuit first loads an initial address (portions 150,
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`154, and 158), and starting with that initial address, transfers a fixed number of
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`words—4 words in Figure 5a—as shown in line DQ. (Ex-1001, 4:54-59.) During
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`the transfer of the fixed number of words, the address and control buses, including
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`ADDR, CEB, and R/WB, are “generally available to other devices” for a known
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`number of cycles, shown in in portions 152, 156, and 160 of Figure 5a. (Ex-1001,
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`4:60-63.)
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`(Ex-1001, Figure 5A.)
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`
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`The non-interruptible generation of internal address signals presents a
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`significant advancement over the prior art. Specifically, fixing the burst length in
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`advance and generating a predetermined number of internal address signals
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`“generally frees up the address bus and control bus for a known number of cycles.”
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`(Ex-1001, 3:56-58.) For memory devices that share the address and control buses,
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`the invention of the ’134 Patent provides “a more reliable and/or accurate burst than
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`is possible with multiple chips.” (Ex-1001, 3:58-61.) The’134 Patent, therefore,
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`presents an advantage over prior art solutions that merely read or write a preset
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`number of data words or presented options for continuously reading or writing data
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`from the memory device.
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`Case IPR2021-00167
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`For example, the United States Patent and Trademark Office (“PTO”) allowed
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`the ’134 Patent over prior art such as US Patent No. 6,289,138 to Yip et al, (“Yip”),
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`that prevent interrupting read or write bursts until a preset number of data words has
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`been transferred, which “is not the same as generating a predetermined number of
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`internal address signals that is non-interruptible.” (Ex-1002, ¶ 0065.)
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`Similarly, the ’134 Patent was allowed, and provides advantages, over prior
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`art that merely presented methods for continuously bursting data in and/or out of the
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`memory. For example, the PTO allowed the ’134 Patent over U.S. Patent No.
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`5,729,504 to Cowles (“Cowles”), which was “directed to a continuous burst EDO
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`memory device (Ex-2002, Title),” and specifically directed to “an ability to access a
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`second row of memory while bursting data out of a first row (a so-called “continuous
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`BEDO,” or “CBEDO” architecture . . . ).” (Ex-1002, ¶¶ 0107-0108). But as the
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`applicant argued, the “ability to access a second row of memory while bursting data
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`out of a first row has little or nothing to do with whether a “burst” can be
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`interrupted.” (Ex-1002, ¶¶ 0107-0108). Moreover, the examiner agreed that
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`Cowles’ continuous burst architecture did not disclose the claim limitation “wherein
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`said generation of said predetermined number of internal address signals is non-
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`interruptible” in the Notice of Allowance:
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`“[T]he prior art discloses an integrated circuit memory device which
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`can operate at high data speeds. The integrated circuit memory can
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`Case IPR2021-00167
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`output data of a “fixed burst length” in a continuous stream while rows
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`of the memory are accessed. However, to terminate a continuous burst
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`read operation, the WE signal merely has to transition high prior to a
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`falling edge of the CAS signal (see, for example, Cowles). [T]hus prior
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`art of record does not teach or fairly suggest the non-interruptible
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`generation of a predetermined number of internal address signals.”
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`(Ex-1002, ¶ 0172 (emphasis in original).)
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`III. Claim Construction
`The Board need only construe terms “that are in controversy, and only to the
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`extent necessary to resolve the controversy.” Vivid Techs., Inc. v. Am. Sci. & Eng’g,
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`Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Nanya argues that no terms require
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`construction. (Pet., 15.) Monterey agrees that no terms require construction, with
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`two exceptions: “non-interruptible,” found in all challenged claims; and two means-
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`plus-function terms in Claim 16, identified below.
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`A. All Challenged Claims: “Non-Interruptible.”
`Certain terms of the ʼ134 Patent, including “non-interruptible,” were
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`previously construed or agreed upon by the parties in two separate actions: (1)
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`Cypress Semiconductor Corp. v. GSI Tech., Inc., No. 3-13-cv-03757, ECF No. 57
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`(N.D. Cal. July 29, 201