IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`Civil Action No. 19-2083 (NIQA)
`
`MONTEREY RESEARCH, LLC,
`Plaintiff,
`
`vs.
`
`QUALCOMM INCORPORATED,
`QUALCOMM TECHNOLOGIES, INC., and
`QUALCOMM CDMA TECHNOLOGIES
`ASIA-PACIFIC PTE LTD.,
`
`Defendants.
`
`DEFENDANT QUALCOMM’S PROPOSED CLAIM CONSTRUCTIONS
`
`1
`
`IPR2021-00167
`Nanya Technology Corp. v. Monterey Research, LLC
`Monterey Research LLC Exhibit 2009
`Ex. 2009, Page 1
`
`
`FOR THE DISTRICT OF DELAWARE
`
`Civil Action No. 19-2083 (NIQA)
`
`MONTEREY RESEARCH, LLC,
`Plaintiff,
`
`vs.
`
`QUALCOMM INCORPORATED,
`QUALCOMM TECHNOLOGIES, INC., and
`QUALCOMM CDMA TECHNOLOGIES
`ASIA-PACIFIC PTE LTD.,
`
`Defendants.
`
`DEFENDANT QUALCOMM’S PROPOSED CLAIM CONSTRUCTIONS
`
`1
`
`IPR2021-00167
`Nanya Technology Corp. v. Monterey Research, LLC
`Monterey Research LLC Exhibit 2009
`Ex. 2009, Page 1
`
`
`
`
`
`Pursuant to the Court’s Scheduling Order (Dkt. 30 at 7), Defendants Qualcomm
`
`Incorporated, Qualcomm Technologies, Inc., and Qualcomm CDMA Technologies Asia-Pacific
`
`PTE Ltd., (collectively “Qualcomm”) hereby identify preliminary claim constructions for terms
`
`proposed by the parties on February 16, 2021.
`
`Qualcomm reserves the right to modify or supplement these disclosures to facilitate
`
`agreement with Monterey, to avoid duplication of terms or phrases, or to reflect newly received
`
`information. Furthermore, Qualcomm reserves the right to modify or supplement its preliminary
`
`proposed constructions once it has had an opportunity to review Monterey’s preliminary
`
`proposed constructions.
`
`Qualcomm’s list of proposed claim term as well as Qualcomm’s preliminary claim
`
`constructions have been prepared in response to Monterey’s November 20, 2020 Preliminary
`
`Disclosure of Asserted Claims and Infringement Contentions. To the extent that Monterey may
`
`amend its contentions, Qualcomm reserves the right to modify the list or constructions below.
`
`Qualcomm also reserves the right to modify the list or constructions in view of positions taken
`
`by Monterey in inter partes review proceedings. Qualcomm reserves the right to offer evidence
`
`and argument regarding the construction of any terms or elements that are identified by
`
`Monterey, or to argue for a plain meaning where it is evident that Monterey’s apparent
`
`interpretation deviates from that plain meaning.
`
`
`
`
`
`
`
`
`2
`
`Ex. 2009, Page 2
`
`
`
`U.S. Patent Number6,459,625
`
`“An electrical interconnection system to
`optimize layout of a periphery area in a
`memory
`device, comprising:”
`(cl. 10
`“periphery area of a silicon substrate” (cl. 10)|“section of a flash memory device outside the
`
`The preamble is limiting
`
`Indefinite
`
`core cell area” “first metal layer lines are fabricated to be
`
`
`
`“distinct process layer that exclusively
`
`performs local interconnect functions”
`;
`
`
`“a single local interconnect layer comprising|Plain and ordinary meaning, other than “local
`local interconnects correspondingto bitlines_|interconnect layer” construed as above
`
`and a global wordline”(cl. 8, 12, 14, 16, 18,
`
`
`20)
`
`
`
`
`“structure formedof polysilicon”
`polysilicon structure”
`“first metal layer”(cl. 53, 59)
`“first conductive layer abovethe local
`
`
`interconnect layer”
`
`
`oriented to extend substantially in one
`direction”(cl. 10) / “second metallayer lines
`are fabricated to be oriented to extend
`substantially perpendicular to said first metal
`layer lines”(cl. 10) / “said third metal layer
`lines are fabricated to be oriented to extend
`substantially parallel to said first metal layer
`lines”(cl. 10)
`
`U.S. Patent Number6,534,805
`
`Ex. 2009, Page 3
`
`
`
`U.S. Patent Number 6,642,573
`
`
`
`Term ProposedConstructionosed Construction
`
`“composite dielectric material”(cl. 1, 9, 10,
`11, 20)
`
`
`signals, wherein said generation of said
`
`Construction
`“once initiated, cannot be stopped or
`terminated until the fixed numberof internal
`addresses has been generated”
`“numberof said internal address signals
`determined prior to receipt of the external
`address signal, clock signal, and one or more
`control signals”
`“burst of a length determined prior to receipt
`of the external addresssignal, clock signal,
`and one or more control signals”
`“means for reading data from and writing data|Function: “reading data from and writing data
`to a plurality of storage elements inresponse|to a plurality of storage elements in response
`to a plurality of internal address signals” (cl._|to a plurality of internal address signals”
`16)
`
`more”
`
`from greater than 10 to about 20”
`“dielectric material comprising the elements
`ofat least two other dielectric materials
`formed by co-deposition of its component
`elements, or by sequential deposition
`following by a treatmentstep”
`
`“stacked structure consisting of a bottom
`oxide layer, a middle nitride layer, and a top
`oxide layer”
`
`“ONOstructure”(cl. 1)
`
`U.S. Patent Number6,651,134
`
`“non-interruptible” (cl. 1, 17)
`
`“predetermined numberof said internal
`address signals”(cl. 1, 2, 3, 4, 17, 18)
`
`“fixed burst length”(cl. 2, 5)
`
`Structure: the memory array 104 depicted in
`Figure | described as “a static random access
`memory (SRAM) or a dynamic random
`access memory (DRAM), or other appropriate
`memory to meet the design criteria of a
`particular implementation, or their
`equivalent”
`Function: “generating a predetermined
`“means for generating a predetermined
`numberofsaid internal address signals in
`numberofsaid internal address signals in
`responseto (i) an external address signal, (ii)|responseto (i) an external address signal, (11)
`a clock signal and(iii) one or more control
`a clock signal, and (iii) one or more control
`signals, wherein said generation of said
`
`Ex. 2009, Page 4
`
`
`
`
`predetermined numberofinternal address
`predetermined numberofinternal address
`signals is non-interruptible”(cl. 16)
`signals is non-interruptible”
`
`Structure: the “circuit 102” depicted in Figure
`2 and described at 3:62-4:14, the “circuit
`102’” depicted in Figure 3 and describedat
`4:16-40, or their equivalents.
`
`U.S. Patent Number6,680,516
`
`“semiconductor substrate”(cl. 5)
`
`“supporting semiconductor material upon
`which or within which elements of the
`semiconductor device are formed”
`“conductive layer comprised of metal, metal
`alloy, or metal compound.”
`“first layer used to significantly slow further
`progress of an etch of a second layer when the
`etch reachesthe first layer”
`“hole, through the insulating layer and
`
`exposing the substrate”
`
`“metallic layer”(cl. 5)
`
`“etch stop layer” (cl. 5)
`
`“via, through the insulating layer, on the
`substrate”(cl. 5
`
`U.S. Patent Number6,765,407
`
`Proposed Construction
`“programmable digital circuit block”(cl. 1, 3,|“programmable digital circuit block that
`7, 8, 10, 14, 15)
`cannot be programmedto perform arbitrary
`
`functions”
`
`Ex. 2009, Page 5
`
`
`
`U.S. Patent Number 7,572,727
`
`“forming a sub spacer region such that a
`substrate coupling area of said contact region
`is smaller than a metal layer coupling area of
`said contact region”(cl. 1)
`
`“forming a sub spacer region that controls,at
`least in part, the size of the substrate coupling
`area of said contact region to be smaller than
`a metal layer coupling area of said contact
`
`“etch stop layer”(cl. 1)
`
`“first layer used to significantly slow further
`progress of an etch of a second layer when the
`etch reachesthe first layer”
`
`Indefinite
`Indefinite
`
`“a spacer region that controls, at least in part,
`the size of the substrate coupling area of said
`contact region to be smaller than a metal layer
`coupling area of said contact region”
`“first layer used to significantly slow further
`progress of an etch of a second layer when the
`etch reachesthefirst layer”
`
`“wherein said second etch stop layer has
`similar selectivity characteristics as said first
`
`U.S. Patent Number 7,977,797
`
`“a spacer region such that a substrate coupling
`area of said contact region is smaller than a
`metal layer coupling area of said contact
`region”(cl. 1)
`“etch stop layer” (cl. 1)
`
`“wherein said second etch stop layer has
`similar selectivity characteristics as said first
`etch stop layer”
`
`Ex. 2009, Page 6
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`
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`Dated: March 1, 2021
`
`
`
`
`
`
`
`
`
`
`By:
`
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`
`/s/ David Nelson
`David Nelson
`Stephen Swedlow
`Nathan Hamstra
`191 N. Wacker Drive, Suite 2700
`Chicago, IL 60606
`Tel: 312-705-7400
`Fax: 312-705-7401
`davidnelson@quinnemanule.com
`stephenswedlow@quinnemanuel.com
`nathanhamstra@quinnemanuel.com
`
`
`for Qualcomm,
`Attorneys
`Qualcomm Technologies, Inc. and
`Qualomm CDMA Technologies Asia Pacific Pte
`Ltd.
`
`Incorporated,
`
`7
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`Ex. 2009, Page 7
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`
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`
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`I HEREBY CERTIFY that on March 1, 2021, I caused to be served true and correct copies
`
`CERTIFICATE OF SERVICE
`
`of the foregoing document by electronic mail on the following counsel:
`
`Brian E. Farnan
`Michael Farnan
`FARNAN LLP
`919 N. Market St., 12th Floor
`Wilmington, DE 19801
`(302) 777-0300
`bfarnan@farnanlaw.com
`mfarnan@farnanlaw.com
`
`
`
`
`
`
`
`
`
`
`
`
`
`Jonas R. McDavit
`Jordan N. Malz
`Edward B. Geist
`Michael Wueste
`Ryan G. Thorne
`DESMARAIS LLP
`230 Park Avenue
`New York, NY 10169
`Telephone: 212-351-3400
`Facsimile: 212-351-3401
`MontereyService@desmaraisllp.com
`
`
`
`/s/ Brianne M. Straka
`Brianne M. Straka
`briannestraka@quinnemanuel.com
`
`8
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`Ex. 2009, Page 8
`
`
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