IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`MONTEREY RESEARCH, LLC,
`
`Plaintiff,
`
`Civil Action No. 19-2083-NIQA-LAS
`
`v.
`
`Jury Trial Requested
`
`QUALCOMM INCORPORATED,
`QUALCOMM TECHNOLOGIES, INC.,
`AND QUALCOMM CDMA
`TECHNOLOGIES ASIA-PACIFIC PTE
`LTD,
`
`Defendants.
`
`QUALCOMM’S INVALIDITY CONTENTIONS
`
`IPR2021-00167
`Nanya Technology Corp. v. Monterey Research, LLC
`Monterey Research LLC Exhibit 2008
`Ex. 2008, Page 1
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`I.
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION ................................................................................................................ 1
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`II.
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`CLAIM CONSTRUCTION ................................................................................................. 7
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`III. ASSERTED PATENT AND CLAIMS ................................................................................ 8
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`IV. PRIORITY ............................................................................................................................ 9
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`V.
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`STATE OF THE ART .......................................................................................................... 9
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`VI.
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`INVALIDITY BASED ON THE PRIOR ART ................................................................. 25
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`VII.
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`INVALIDITY UNDER 35 U.S.C. § 112 ......................................................................... 142
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`VIII. ADDITIONAL INVALIDITY CONTENTIONS ............................................................ 161
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`IX. DOCUMENT PRODUCTION UNDER PARAGRAPH 5 OF THE SCHEDULING
`ORDER ....................................................................................................................................... 161
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`i
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`Ex. 2008, Page 2
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`Appendix A (A1-A15)
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`EXHIBITS AND APPENDICES
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`Invalidity claim charts for U.S. Patent No. 6,459,625
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`Appendix B (B1-B5)
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`Invalidity claim charts for U.S. Patent No. 6,534,805
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`Appendix C (C1-C7)
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`Invalidity claim charts for U.S. Patent No. 6,642,573
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`Appendix D (D1-D18)
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`Invalidity claim charts for U.S. Patent No. 6,651,134
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`Appendices E (E1-E7)
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`Invalidity claim charts for U.S. Patent No. 6,680,516
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`Appendix F (F1-F10)
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`Invalidity claim charts for U.S. Patent No. 6,765,407
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`Appendix G (G1-G9)
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`Invalidity claim charts for U.S. Patent No. 7,572,727
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`Appendix H (H1-H9)
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`Invalidity claim charts for U.S. Patent No. 7,977,797
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`Appendix OA
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`Appendix OB
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`Appendix OC
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`Appendix OD
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`Appendix OE
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`Appendix OF
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`Appendix OG
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`Appendix OH
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`Appendix AA
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`Appendix AB
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`Appendix AC
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`Appendix AD
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`Appendix AE
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`Appendix AG
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`Appendix AH
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`Obviousness references for U.S. Patent No. 6,459,625
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`Obviousness references for U.S. Patent No. 6,534,805
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`Obviousness references for U.S. Patent No. 6,642,573
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`Obviousness references for U.S. Patent No. 6,651,134
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`Obviousness references for U.S. Patent No. 6,680,516
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`Obviousness references for U.S. Patent No. 6,765,407
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`Obviousness references for U.S. Patent No. 7,572,727
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`Obviousness references for U.S. Patent No. 7,977,797
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`Applicant Admitted Prior Art for U.S. Patent No. 6,459,625
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`Applicant Admitted Prior Art for U.S. Patent No. 6,534,805
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`Applicant Admitted Prior Art for U.S. Patent No. 6,642,573
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`Applicant Admitted Prior Art for U.S. Patent No. 6,651,134
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`Applicant Admitted Prior Art for U.S. Patent No. 6,680,516
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`Applicant Admitted Prior Art for U.S. Patent No. 7,572,727
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`Applicant Admitted Prior Art for U.S. Patent No. 7,977,797
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`ii
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`Ex. 2008, Page 3
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`I.
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`INTRODUCTION
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`Pursuant to the Court’s Scheduling Order (D.I. 44) Qualcomm Technologies, Inc., and
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`Qualcomm CDMA Technologies Asia-Pacific PTE LTD
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`(“Qualcomm”)
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`(collectively
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`“Defendant” or “Qualcomm”) serves these Initial Invalidity Contentions on Plaintiff Monterey
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`Research, LLC (“Plaintiff” or “Monterey”) for U.S. Patent Nos. 6,459,625 (the “’625 Patent”),
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`6,534,805 (the “’805 Patent”), 6,642,573 (the “’573 Patent”), 6,651,134 (the “’134 Patent”),
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`6,680,516 (the “’516 Patent”), 6,765,407 (the “’407 Patent”), 7,572,727, and 7,977,797
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`(collectively the “Asserted Patents”). These Invalidity Contentions are based on Defendant’s
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`current knowledge of the Asserted Patents and prior art, along with its understanding of Plaintiff’s
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`infringement allegations set forth in its November 20, 2020 Preliminary Disclosure of Asserted
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`Claims and Infringement Contentions (“Infringement Contentions”). Defendant’s investigation of
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`the prior art is ongoing, and Defendant expressly reserves the right to supplement these Invalidity
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`Contentions as the case proceeds.
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`Nothing in these Invalidity Contentions is intended, nor should be construed, as a waiver
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`of any claim construction argument or non-infringement position. Defendant’s statements herein
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`(including the accompanying claim charts) reflect Defendant’s present understanding of the
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`purported potential scope of the claims that Monterey appears to be advocating by way of its
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`Infringement Contentions. They are not to be seen as any acquiescence to Plaintiff’s interpretation
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`of any claims. Defendant disagrees that any such claim scope is proper. Defendant reserves the
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`right to supplement these contentions to address any supplemental infringement contentions. For
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`purposes of these Invalidity Contentions, Defendant identifies prior art references and provides
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`element-by-element claim charts based on the apparent constructions of the Asserted Claims
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`advanced by Monterey in its Infringement Contentions (which, for at least some limitations,
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`contradict the plain language of the claim).
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`Ex. 2008, Page 4
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`Nothing herein shall be interpreted as an admission that: (1) the Asserted Claims are
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`infringed by any of Defendant’s instrumentalities, (2) any particular feature or aspect of any of the
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`accused instrumentalities practices any limitation of the Asserted Claims, (3) there is 35 U.S.C. §
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`112 support for any limitation of the Asserted Claims, or (4) any of Monterey’s proposed or
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`implied constructions are supportable or proper.
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`Consistent with the Court’s Scheduling Order and the Federal Rules of Civil Procedure,
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`Defendant reserves the right to amend these Invalidity Contentions. The information and
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`documents that Defendant produces are provisional and subject to further revision as follows.
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`Defendant expressly reserves the right to amend its disclosures and document production
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`referenced herein should Monterey provide any information that it failed to provide in its
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`Infringement Contention disclosures or should Monterey amend its disclosures in any way,
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`whether explicitly or implicitly. Further, because discovery has only recently begun and because
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`Qualcomm has not yet completed its search for and analysis of relevant prior art, Defendant
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`reserves the right to amend the information provided herein. Such amendments include, for
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`example, identifying and relying on additional references, should Defendant’s further search and
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`analysis yield additional information or references. Defendant reserves the right to supplement
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`these contentions in light of any additional prior art of which Plaintiff is aware, and did not disclose
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`to Defendant in discovery. Also, Defendant anticipates issuing subpoenas to third parties believed
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`to have knowledge, documentation and/or corroborating evidence concerning some of the prior art
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`listed herein and/or additional prior art. These third parties include, but are not limited to, the
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`authors, employers of authors, inventors, assignees, or former or current employee of assignees,
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`of the references identified or the Asserted Patents. Defendant reserves the right to supplement
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`2
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`Ex. 2008, Page 5
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`these contentions in light of any newly discovered information produced by these or other
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`companies from which Defendant may seek discovery.
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`Defendant also contends that the Asserted Claims are invalid in view of public knowledge
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`and uses and/or offers for sale or sales of products and services that are under 35 U.S.C. § 102(a)
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`and/or 35 U.S.C. § 102(b) and/or prior inventions made in this country by other inventors who had
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`not abandoned, suppressed, or concealed them under 35 U.S.C. § 102(g), and that anticipate or
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`render obvious the Asserted Claims. The following lists each system that is now known by
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`Defendant to constitute prior art under 35 U.S.C. §§ 102(a), (b), (f), and/or (g). Defendant
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`contends that the following descriptions and events are stated on information and belief, and are
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`supported by the information and documents that will be produced by Defendant and/or third
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`parties. As discovery is ongoing, Defendant continues to investigate these events.
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`Moreover, Defendant reserves the right to revise its contentions concerning the invalidity
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`of the claims of the Asserted Patents based upon the Court’s construction of the claims of the
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`Asserted Patents, any findings as to the priority dates of the Asserted Claims, and/or positions that
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`Monterey, Qualcomm, or any expert witness may take concerning claim interpretation,
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`infringement, and/or invalidity issues.
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`Prior art not included in this disclosure, whether known or not known to Defendant, may
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`become relevant. In particular, Defendant is currently unaware of the extent, if any, to which
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`Monterey will contend that limitations of the Asserted Claims are not disclosed in the prior art
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`identified by Defendant. To the extent that such an issue arises, Defendant reserves the right to
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`identify other references that would have made the addition of the allegedly missing limitation to
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`the disclosed device or method obvious or show that the allegedly missing limitation would have
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`3
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`Ex. 2008, Page 6
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`been known or readily apparent to one of ordinary skill in the art at the time of the alleged invention
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`in light of the disclosure of the prior art at issue.
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`Defendant’s claim charts in Appendices A through H, OA through OH, and AA through
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`AH cite to or reference particular teachings and disclosures of the prior art as applied to features
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`of the Asserted Claims, but persons having ordinary skill in the art generally may view an item of
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`prior art in the context of other publications, literature, products, and understanding. As such, the
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`cited portions are only examples, and Defendant reserves the right to rely on uncited portions of
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`the prior-art references and on other publications and expert testimony as aids in understanding
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`and interpreting the cited portions, as providing context thereto, and as additional evidence that
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`the prior art discloses a claim limitation. Defendant further reserves the right to rely on uncited
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`portions of the prior-art references, other publications, and testimony to establish reasons for
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`combining certain cited references that render the Asserted Claims obvious.
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`The references discussed below and in the claim charts in Appendices A-H, OA-OH, and
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`AA-AH may disclose the elements of the Asserted Claims explicitly and/or inherently, and/or they
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`may be relied upon to show the state of the art in the relevant time frame. The suggested
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`obviousness combinations are provided in the alternative to Defendant’s anticipation contentions
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`and are not to be construed to suggest that any reference included in the combinations is not by
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`itself anticipatory.
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`Depending on the Court’s construction of the claims of the Asserted Patents, and/or
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`positions that Monterey, Defendant, or any expert witness may take concerning claim
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`interpretation, infringement, and/or invalidity issues, one or more of the charted prior-art
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`references may be of greater or lesser relevance and different combinations of these references
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`4
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`Ex. 2008, Page 7
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`may be implicated. Given this uncertainty, the charts may reflect alternative applications of the
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`prior art against the Asserted Claims.
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`Defendant’s Invalidity Contentions are based at least in part on the filing dates of the
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`applications resulting in the Asserted Patents, and Monterey’s contention that the ’625 Patent, the
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`’407 Patent, and the ’797 Patent are entitled to the priority date of an earlier application. Defendant
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`reserves the right to challenge these priority dates and any priority date that Monterey later alleges
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`is appropriate.
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`Defendant reserves the right to assert invalidity under 35 U.S.C. §§ 101, 102(c), (d), or (f)
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`to the extent that discovery or further investigation yield information forming the basis for such
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`claims. Defendant reserves the right to assert that the Asserted Patents are invalid under 35 U.S.C.
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`§ 102(f) in the event Defendant obtains evidence that the named inventors of the Asserted Patents
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`did not invent the subject matter claimed in the Asserted Patent. Should Defendant obtain such
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`evidence, it will provide the name of the person(s) from whom and the circumstances under which
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`the invention or any part of it was derived.
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`Defendant incorporates in these Invalidity Contentions, in full, all prior art references cited
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`in the Asserted Patents and their prosecution histories and any applicable post-grant proceedings,
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`including ex parte reexaminations and inter partes reviews (currently pending or otherwise),
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`including but not limited to:
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2021-00130 (U.S. Patent
`No. 6,459,625)
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` Macronix International Co., Ltd. v. Spansion LLC, IPR2014-00104 (U.S. Patent No.
`6,459,625)
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` Ex Parte Reexamination of U.S. Patent No. 6,534,805 (90/011,833)
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` Advanced Micro Devices, Inc. v. Monterey Research, LLC, IPR2020-00990 (U.S.
`Patent No. 6,534,805)
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`5
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`Ex. 2008, Page 8
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2020-01491 (U.S. Patent
`No. 6,534,805)
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` STMicroelectronics, Inc. v. Monterey Research, LLC, IPR IPR2021-00356 (U.S.
`Patent No. Patent 6,534,805)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2021-00125 (U.S. Patent
`No. 6,642,573)
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` Advanced Micro Devices, Inc. v. Monterey Research, LLC, IPR2020-00985 (U.S.
`Patent No. 6,651,134)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2020-01492 (U.S. Patent
`No. 6,651,134)
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` Nanya Technology Corporation v. Monterey Research, LLC, IPR2021-00167 (U.S.
`Patent No. 6,651,134)
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` STMicroelectronics, Inc. v. Monterey Research, LLC, IPR2021-00355 (U.S. Patent
`No. 6,651,134)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2021-00119, (U.S. Patent
`No. 6,680,516)
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` Nanya Technology Corporation et al v. Monterey Research, LLC, IPR2021-00171,
`(U.S. Patent No. 6,680,516)
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` Advanced Micro Devices, Inc. v. Monterey Research, LLC, IPR2020-00989 (U.S.
`Patent No. 6,765,407)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2021-01493 (U.S. Patent
`No. 6,765,407)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2021-00120 (U.S. Patent
`No. 7,572,727)
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` Qualcomm Incorporated v. Monterey Research, LLC, IPR2021-00121 (U.S. Patent
`No. 7,977,797)
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`Qualcomm further incorporates in these Invalidity Contentions all invalidity theories
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`expressed by Defendants STMicroelectronics, Inc (“ST, Inc.”) and/or Nanya Technology
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`Corporation, Nanya Technology Corporation, U.S.A., and Nanya Technology Corporation
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`Delaware (“Nanya”) that are complementary and/or supplementary to those expressed by
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`Qualcomm as if those theories were set forth in full in Qualcomm’s contentions.
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`Defendant has provided disclosures and related documents pertaining only to the Asserted
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`Claims as identified by Monterey in its Infringement Contentions. Defendant reserves the right to
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`6
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`Ex. 2008, Page 9
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`modify, amend, or supplement these Invalidity Contentions to show the invalidity of any additional
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`claims that the Court may allow Monterey to later assert. Defendant further reserves the right to
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`supplement its document production should it later find additional, responsive documents.
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`II.
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`CLAIM CONSTRUCTION
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`To the extent that these Invalidity Contentions rely on or otherwise embody particular
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`constructions of terms or phrases in the Asserted Claims, Qualcomm is not proposing any such
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`constructions as proper constructions of those terms or phrases at this time. The Court established
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`separate deadlines for the parties’ proposed claim constructions, and Qualcomm will disclose its
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`proposed constructions accordingly. For purposes of these Invalidity Contentions, Qualcomm may
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`adopt alternative claim construction positions. In particular, portions of these Invalidity
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`Contentions, including the claim charts attached as Appendices, may be based on the underlying
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`claim constructions and/or interpretations as understood from Plaintiff’s Infringement Contentions
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`and/or Plaintiff’s proposed claim constructions. Qualcomm, however, does not concede that
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`Plaintiff’s apparent constructions are supportable or proper, and Qualcomm expressly reserves the
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`right to contest any such constructions. In addition, to the extent that these Invalidity Contentions
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`rely on or otherwise embody a particular order in which the steps of method claims are performed,
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`Qualcomm does not necessarily propose that the method claims must be limited to such order,
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`although Qualcomm reserves the right to propose such an order. Moreover, nothing disclosed
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`herein is an admission or acknowledgement that any Accused Instrumentality, or any of
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`Qualcomm’s other products or services, infringes any of the Asserted Claims. Qualcomm reserves
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`the right to supplement, modify, or otherwise amend these Invalidity Contentions, including based
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`on the Court’s claim construction ruling and/or arguments or positions taken during the claim
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`construction process.
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`7
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`Ex. 2008, Page 10
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`Throughout the attached Appendices, Qualcomm provides examples of where references
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`disclose subject matter recited in preambles, without regard to whether the preambles are properly
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`consideredto be limitations of the Asserted Claims. Qualcomm reservesthe right to argue, at the
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`appropriate stage of this case, that the preamblesare or are not limitations. Moreover, Qualcomm
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`reserves the right to argue that certain claim elements of the Asserted Claims do notin fact limit
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`the scope of the Asserted Claims.
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`Il.
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`ASSERTED PATENT AND CLAIMS
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`Plaintiff asserted the following patents and claims in its Infringement Contentions against
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`Defendant!:
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`
`
`Ssas|a
`EREee
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`2]US-PatentNo.6834-805 8, 12, 14,16, 18, 20, 22-25, 27-28, 30, 53-57, 59
`Peeeee
`Paeernee
`Pe
`eeeeee
`Pe
`[Pee
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`For the purposes of these contentions, Qualcomm addresses only those claimsspecifically
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`asserted by Plaintiff. Defendant reserves the right to amend or supplement this disclosure as
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`' The asserted patents and claims are collectively referenced throughout these contentions
`as the “Asserted Patents” and the “Asserted Claims.”
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`Ex. 2008, Page 11
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`necessary in light of any changes or amendments made, for any reason, to Plaintiff’s infringement
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`theories, Infringement Contentions, or asserted claims.
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`IV.
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`PRIORITY
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`To the extent Plaintiff alleges that any prior art relied on in these Invalidity Contentions
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`does not actually qualify as prior art to an Asserted Patent, Qualcomm reserves the right to rebut
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`those allegations (e.g., by demonstrating an earlier critical date for the challenged prior art and/or
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`a later priority date for the Asserted Patent and/or Asserted Claim).
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`V.
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`STATE OF THE ART
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`Defendant sets forth a summary of its current understanding of the state of the art for
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`general subject matter of the Asserted Patents. Defendant expressly reserves the right to rely on
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`each of the prior art references discussed in Section VI below with respect to each of the Asserted
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`Claims. Defendant also reserves the right to rely on the discussions of the state of the art and prior
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`art for the Asserted Patents and their file histories in explaining the state of the art and the
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`references’ correspondence with the claims of the Asserted Patent. Defendant further expressly
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`reserves the right to supplement its summary of the state of the art, including for example, by
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`information from any of the authors or named inventors on any of the prior art references, by
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`personnel familiar with systems based on any of the prior art, or by technical experts retained on
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`behalf of any party.
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`A.
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`State of the Art for the Asserted Patents
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`1.
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`U.S. Patent No. 6,459,625
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` The ’625 Patent was filed on January 23, 2001 with a claimed priority of February 25,
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`2000. The ’625 Patent is directed to “methods and systems for optimization of layout density in a
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`periphery area using a three-metal interconnection process” as opposed to two metal processes that
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`were the purported state of the art for interconnects on the periphery of memory devices in which
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`Ex. 2008, Page 12
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`the first metal was used for interconnections within sub-circuits and the second metal was used for
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`interconnections between sub-circuits. ’625 Patent at 1:10-13. According to the ’625 Patent, a
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`known problem with the use of this two metal process in the periphery area, and in particular use
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`of a single metal for interconnections internal to sub-circuits is the layout area consumed (i) by the
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`routing channels of the metal layers between sub-circuits in the periphery and (ii) by the routing
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`channels between components that form the sub-circuits. Id. at 2:18-20. The ’625 Patent states
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`that a reduction in the layout area consumed in the periphery area can result in increasing the
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`available area for the core area.
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`The ’625 Patent contends that in the prior art, the second metal interconnect layer is used
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`to electrically connect the first metal interconnect layer with the core memory cells by routing the
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`second metal lines of the second metal interconnect layer in routing channels between the sub-
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`circuits. Id. at 8:36-40. The routing of the second metal lines of the second metal interconnect
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`layer between the sub-circuits consumes layout area between the sub-circuits, thereby enlarging
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`the periphery area. Id. at 8:41-47. The ’625 Patent proposes interconnect structure in which: (1)
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`a first metal layer defines first lines that provide some local interconnects internal to each of a
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`plurality of sub-circuits, and (2) a second metal layer defines second lines, perpendicular to the
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`first lines, that complete the local interconnects internal to each of the sub-circuits. Id. at 3:14-30.
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`However, the ’625 Patent’s purported improvement was well-known.
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`During prosecution, claims 1-14 were rejected under 35 U.S. C. 102(e) as being anticipated
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`by Johnson et al. (U.S. Patent No. 6,034,882). MRL-DEL00022907 at 2974. The Applicants
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`argued that that “Johnson teaches an interconnect structure for a vertical three dimensional array
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`of memory elements that are fabricated on and above a substrate, whereas the present invention is
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`directed to an interconnect structure for circuit elements fabricated in a peripheral area of a silicon
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`10
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`Ex. 2008, Page 13
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`substrate. The claims have been amended to emphasize this distinction.” Id. at 2991. See id. at
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`2998 (“a plurality of sub-circuits in a periphery area of a silicon substrate, wherein each of said
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`sub-circuits includes at least one electric circuit with a plurality of circuit components”)(underline
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`was amended). The Applicants further argued that Johnson discloses a memory cell array which
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`is not a periphery area. Id. at 2992-93. But the use of a metal interconnect scheme in periphery
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`areas such as the one disclosed in the ’625 Patent was known in the prior art.
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`For example, How-767 explains in forming integrated circuits (ICs) requires several layers.
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`How-767 at 1:20-21. “Most active layer devices are formed independently of one another, i.e.,
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`they are not connected to form a circuit,” and therefore “metal layers are formed over the active
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`layers to interconnect the devices, thereby forming a circuit.” Id. at 1:24-26. How-767 explains
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`that several metal layers may be required to completely interconnect the devices to form a useful
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`circuit. Id at 1:26-30. How-767 example in Fig. 1 shows four metal layers, M1 120, M2 130, M3
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`140 and M4 150 although explains many different ICs require more or less than four metal layers.
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`Id. 1:30-34.
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`How-767 also describes using different metal layers to provide interconnections in between
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`function blocks and internal to function blocks. Id. at 1:62-65 (“To interconnect active devices
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`within each function block (i.e., form ‘local interconnections’) a series of horizontal and vertical
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`connection lines formed in the metal layers are utilized.”). How-767 explains that it “is well
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`understood in the art, any two points can be connected using a series of horizontal and vertical
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`connection lines.” Id. at 1:65-67.
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`How-767 further explains that an IC may be divided into multiple functional areas. For
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`example, ASIC 400 in How-767 contains an “array 410 of function blocks 420,” and “specialized
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`regions 421,” “which contain other circuitry such as memory blocks or logic cores” and “periphery
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`11
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`area 430 surrounding array 410,” which “includes circuitry such as 10 pads and other support
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`circuitry for array 410.” Id. at 5:42-52, 8:36-38, 11:4-7, FIG. 4. How-767 explains “[r]outing for
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`specialized regions 421 can be done” using the same scheme as discussed for array 410 “or by
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`their own routing structure.” Id. at 8:36-37. See also Qualcomm Incorporated v. Monterey
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`Research, LLC, IPR2021-00130, Paper 1 at 8-17 (PTAB Nov. 5, 2020).
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`Therefore the ’625 Patent’s use of metal interconnect scheme in periphery areas was well-
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`known and the claims of the ’625 Patent are invalid as anticipated or obvious over the prior art
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`discussed herein and in Appendices A, OA, and AA.
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`2.
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`U.S. Patent No. 6,534,805
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`The ’805 Patent was filed on April 9, 2001. The ’805 Patent is directed to “an improved
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`Static Random Access Memory (SRAM) cell design and method of manufacture.” ’805 Patent at
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`1:8-9. The ’805 Patent describes alleged problems with conventional memory design. For
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`example, although conventional SRAMs were quicker than Dynamic Random Access Memory
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`(DRAM), SRAMs had a lower memory cell density because the transistor-based cells were
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`intrinsically larger than the capacitor-based DRAM cells. ’805 Patent at 2:19-22. The ’805 Patent
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`further explains that smaller transistors are also faster, but smaller transistors with complex
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`geometries are more difficult to manufacture as their dimensions are reduced. ’805 Patent at 2:30-
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`64. The ’805 Patent is therefore directed to improved circuit design and methods of manufacture
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`to facilitate fabrication of smaller and faster SRAMs. In particular, the ’805 Patent describes a
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`design including four active regions (highlighted below in yellow) serving as the source, drain,
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`and channel of six transistors and perpendicular polysilicon structures (highlighted below in purple)
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`serving as the gates of the six transistors as well as local interconnects. Id., Abstract, 3:35-37, 6:17-
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`30, 6:53-64.
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`The SRAM cell in the ’805 Patent also includes contacts “formed through a dielectric
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`material arranged above the topography of the features shown in FIG. 2,” including “contact
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`regions 31-34” that connect upward to an interconnect layer and are “used for the local
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`interconnections of gates and drains,” and contacts 13c6, 13c5, 14c3, 14c2, 16c, 15c, 17c1, 17c4
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`that connect upward to an interconnect layer to ultimately couple to bitlines, global wordline, VSS
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`(ground), and VCC (power). Id., 10:44-46, 13:10-33. Those are illustrated below and highlighted
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`in blue.
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`Ex. 2008, Page 16
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`Further, in Figure 3 the ’805 Patent “illustrates a local interconnect layer” having local
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`interconnects 35-44, which have been highlighted in green below. Id., 11:50-51. The patent states
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`that “local interconnect layer” refers to “a distinct process layer that exclusively performs such
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`short connections,” while other layers “may perform local interconnecting functions, yet not be
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`termed a ‘local interconnect layer.’” Id., 11:22-25.
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`
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`During the prosecution of the ’805 Patent, the Examiner issued anticipation rejections over
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`Japanese Patent Publication No. 11-195716A (“Kim”) for Claims 1-16 and over Japanese Patent
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`No. 2000-243858A (“Ishida”) for Claims 17-19. In response, Applicants canceled certain claims,
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`and argued that Kim does not disclose substantially oblong active regions, substantially oblong
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`polysilicon structures, or shared contacts. Applicant also argued that the mapped interconnect in
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`Ishida is a “global interconnect,” rather than a local interconnect.
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`Subsequently, the ’805 Patent was reexamined. The Examiner issued a non-final office
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`action rejecting Claims 1-4 as anticipated by Ishida IEDM and Claims 5-6 and 8-10 as obvious in
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`view of Osada. The patentee amended Claim 8 and added new Claims 11-61. In a final office
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`action, the Examiner accepted Patentee’s arguments that the ’805 Patent’s “wordline on top of
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`bitlines” arrangement was patentable over Osada, showing “the reverse order of bitlines on top of
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`wordlines,” and allowed added Claims 53-61. The Examiner also allowed added Claims 26 and
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`29, among others, concluding the art of record did not disclose local interconnects “having an
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`upper surface that is substantially coplanar with an upper surface of the source/drain contact.” The
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`Examiner maintained the rejections of the original claims and issued rejections for the remaining
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`added claims. Patentee conducted a further examiner interview and made further claim
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`amendments, in response to which the Examiner issued an Advisory Action allowing additional
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`claims but maintaining the rejection of Claims 1-6. Patentee then amended Claim 8 and several
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`added claims to include “a single local interconnect layer comprising local interconnects
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`corresponding to bitlines and a global wordline,” and obtained allowance of several claims on that
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`basis. Patentee also argued that “wherein the substantially oblong local interconnect overlaps both
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`the polysilicon structure and said one of the inner active regions” in Claims 27, 28, and 30-32 was
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`not in the prior art, and obtained allowance on that basis.
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`However, SRAM cells including the same arrangement of active regions, polysilicon
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`structures, contacts, and a local interconnect layer were already known in the prior art. For
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`example, Oh describes an SRAM cell with active regions and polysilicon structures, contacts, and
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`a local interconnect layer in the same arrangement as the ’805 Patent. Oh Figure 3 shows the
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`active regions (highlighted in yellow) and polysilicon structures (highlighted in purple).
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`Ex. 2008, Page 18
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`Figure 4 shows the contacts highlighted below in blue.
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`Figure 5 illustrates a local interconnect layer highlighted in green below.
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`See also Qualcomm, Incorporated v. Monterey Research, LLC, IPR2020-01491, Paper 1
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`at 15-19 (PTAB Aug. 20, 2020); Advanced Micro Devices, Inc. v. Monterey Research, LLC,
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`IPR2020-00990, Paper 1 at 19-29 (PTAB May 26, 2020).
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`Therefore, as described further herein, the SRAM cell design disclosed in the ‘805 Patent
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`was well-known, and the claims of the ’805 Patent are invalid as anticipated or obvious over the
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`prior art discussed herein and at Appendices B, OB, and AB.
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`3.
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`U.S. Patent No. 6,642,573
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`The ’573 Patent was filed March 13, 2002, and is directed towards “a semiconductor device
`
`including a modified ONO structure” in particular “replac[ing] either or both silicon dioxide layers
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`of [a] conventional ONO structure” with “mid-K’ or “high-K dielectric materials,” which are also
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`oxides. ’573 patent at 3:2-11; 5:20-23, 12:58-61 The ’573 Patent acknowledges that memory
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`devices have used oxide-nitride-oxide (“ONO”) structures. ’573 at 1:13-2:67. However instead
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`claims a “composite dielectric material” having a higher dielectric constant (“mid-K or high-K”)
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`than the silicon oxide commonly used in commercial ONO structures. The ’573 Patent recites that
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`“the term ‘composite dielectric material’ refers to a dielectric material comprising the elements of